nds32: support FreeRTOS
[openocd.git] / src / rtos / rtos_standard_stackings.c
1 /***************************************************************************
2 * Copyright (C) 2011 by Broadcom Corporation *
3 * Evan Hunter - ehunter@broadcom.com *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include "rtos.h"
26
27 static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[] = {
28 { 0x20, 32 }, /* r0 */
29 { 0x24, 32 }, /* r1 */
30 { 0x28, 32 }, /* r2 */
31 { 0x2c, 32 }, /* r3 */
32 { 0x00, 32 }, /* r4 */
33 { 0x04, 32 }, /* r5 */
34 { 0x08, 32 }, /* r6 */
35 { 0x0c, 32 }, /* r7 */
36 { 0x10, 32 }, /* r8 */
37 { 0x14, 32 }, /* r9 */
38 { 0x18, 32 }, /* r10 */
39 { 0x1c, 32 }, /* r11 */
40 { 0x30, 32 }, /* r12 */
41 { -2, 32 }, /* sp */
42 { 0x34, 32 }, /* lr */
43 { 0x38, 32 }, /* pc */
44 { -1, 96 }, /* FPA1 */
45 { -1, 96 }, /* FPA2 */
46 { -1, 96 }, /* FPA3 */
47 { -1, 96 }, /* FPA4 */
48 { -1, 96 }, /* FPA5 */
49 { -1, 96 }, /* FPA6 */
50 { -1, 96 }, /* FPA7 */
51 { -1, 96 }, /* FPA8 */
52 { -1, 32 }, /* FPS */
53 { 0x3c, 32 }, /* xPSR */
54 };
55
56
57 static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = {
58 { 0x08, 32 }, /* r0 (a1) */
59 { 0x0c, 32 }, /* r1 (a2) */
60 { 0x10, 32 }, /* r2 (a3) */
61 { 0x14, 32 }, /* r3 (a4) */
62 { 0x18, 32 }, /* r4 (v1) */
63 { 0x1c, 32 }, /* r5 (v2) */
64 { 0x20, 32 }, /* r6 (v3) */
65 { 0x24, 32 }, /* r7 (v4) */
66 { 0x28, 32 }, /* r8 (a1) */
67 { 0x2c, 32 }, /* r9 (sb) */
68 { 0x30, 32 }, /* r10 (sl) */
69 { 0x34, 32 }, /* r11 (fp) */
70 { 0x38, 32 }, /* r12 (ip) */
71 { -2, 32 }, /* sp */
72 { 0x3c, 32 }, /* lr */
73 { 0x40, 32 }, /* pc */
74 { -1, 96 }, /* FPA1 */
75 { -1, 96 }, /* FPA2 */
76 { -1, 96 }, /* FPA3 */
77 { -1, 96 }, /* FPA4 */
78 { -1, 96 }, /* FPA5 */
79 { -1, 96 }, /* FPA6 */
80 { -1, 96 }, /* FPA7 */
81 { -1, 96 }, /* FPA8 */
82 { -1, 32 }, /* FPS */
83 { 0x04, 32 }, /* CSPR */
84 };
85
86 static const struct stack_register_offset rtos_standard_NDS32_N1068_stack_offsets[] = {
87 { 0x88, 32 }, /* R0 */
88 { 0x8C, 32 }, /* R1 */
89 { 0x14, 32 }, /* R2 */
90 { 0x18, 32 }, /* R3 */
91 { 0x1C, 32 }, /* R4 */
92 { 0x20, 32 }, /* R5 */
93 { 0x24, 32 }, /* R6 */
94 { 0x28, 32 }, /* R7 */
95 { 0x2C, 32 }, /* R8 */
96 { 0x30, 32 }, /* R9 */
97 { 0x34, 32 }, /* R10 */
98 { 0x38, 32 }, /* R11 */
99 { 0x3C, 32 }, /* R12 */
100 { 0x40, 32 }, /* R13 */
101 { 0x44, 32 }, /* R14 */
102 { 0x48, 32 }, /* R15 */
103 { 0x4C, 32 }, /* R16 */
104 { 0x50, 32 }, /* R17 */
105 { 0x54, 32 }, /* R18 */
106 { 0x58, 32 }, /* R19 */
107 { 0x5C, 32 }, /* R20 */
108 { 0x60, 32 }, /* R21 */
109 { 0x64, 32 }, /* R22 */
110 { 0x68, 32 }, /* R23 */
111 { 0x6C, 32 }, /* R24 */
112 { 0x70, 32 }, /* R25 */
113 { 0x74, 32 }, /* R26 */
114 { 0x78, 32 }, /* R27 */
115 { 0x7C, 32 }, /* R28 */
116 { 0x80, 32 }, /* R29 */
117 { 0x84, 32 }, /* R30 (LP) */
118 { 0x00, 32 }, /* R31 (SP) */
119 { 0x04, 32 }, /* PSW */
120 { 0x08, 32 }, /* IPC */
121 { 0x0C, 32 }, /* IPSW */
122 { 0x10, 32 }, /* IFC_LP */
123 };
124
125 const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
126 0x40, /* stack_registers_size */
127 -1, /* stack_growth_direction */
128 26, /* num_output_registers */
129 8, /* stack_alignment */
130 rtos_standard_Cortex_M3_stack_offsets /* register_offsets */
131 };
132
133
134 const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = {
135 0x48, /* stack_registers_size */
136 -1, /* stack_growth_direction */
137 26, /* num_output_registers */
138 8, /* stack_alignment */
139 rtos_standard_Cortex_R4_stack_offsets /* register_offsets */
140 };
141
142 const struct rtos_register_stacking rtos_standard_NDS32_N1068_stacking = {
143 0x90, /* stack_registers_size */
144 -1, /* stack_growth_direction */
145 32, /* num_output_registers */
146 8, /* stack_alignment */
147 rtos_standard_NDS32_N1068_stack_offsets /* register_offsets */
148 };