cmsis-dap: add initial cmsis-dap support
[openocd.git] / src / jtag / swd.h
1 /***************************************************************************
2 * Copyright (C) 2009-2010 by David Brownell *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
18 ***************************************************************************/
19
20 #ifndef SWD_H
21 #define SWD_H
22
23 /* Bits in SWD command packets, written from host to target
24 * first bit on the wire is START
25 */
26 #define SWD_CMD_START (1 << 0) /* always set */
27 #define SWD_CMD_APnDP (1 << 1) /* set only for AP access */
28 #define SWD_CMD_RnW (1 << 2) /* set only for read access */
29 #define SWD_CMD_A32 (3 << 3) /* bits A[3:2] of register addr */
30 #define SWD_CMD_PARITY (1 << 5) /* parity of APnDP|RnW|A32 */
31 #define SWD_CMD_STOP (0 << 6) /* always clear for synch SWD */
32 #define SWD_CMD_PARK (0 << 7) /* not driven by host (pull high) */
33 /* followed by TRN, 3-bits of ACK, TRN */
34
35 /* pbit16 holds precomputed parity bits for each nibble */
36 #define pbit(parity, nibble) (parity << nibble)
37
38 static const uint16_t pbit16 =
39 pbit(0, 0) | pbit(1, 1) | pbit(1, 2) | pbit(0, 3)
40 | pbit(1, 4) | pbit(0, 5) | pbit(0, 6) | pbit(1, 7)
41 | pbit(1, 8) | pbit(0, 9) | pbit(0, 0xa) | pbit(1, 0xb)
42 | pbit(0, 0xc) | pbit(1, 0xd) | pbit(1, 0xe) | pbit(0, 0xf);
43
44 #define nibble_parity(nibble) (pbit16 & pbit(1, nibble))
45
46 /**
47 * Construct a "cmd" byte, in lSB bit order, which swd_driver.read_reg()
48 * and swd_driver.write_reg() methods will use directly.
49 */
50 static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
51 {
52 uint8_t cmd = (is_ap ? SWD_CMD_APnDP : 0)
53 | (is_read ? SWD_CMD_RnW : 0)
54 | ((regnum & 0xc) << 1);
55
56 /* 8 cmd bits 4:1 may be set */
57 if (nibble_parity(cmd >> 1))
58 cmd |= SWD_CMD_PARITY;
59
60 /* driver handles START, STOP, and TRN */
61
62 return cmd;
63 }
64
65 /* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
66
67 /*
68 * FOR NOW ... SWD driver ops are synchronous and return ACK
69 * status ... no quueueing.
70 *
71 * Individual ops are request/response, and fast-fail permits much
72 * better fault handling. Upper layers may queue if desired.
73 */
74
75 struct swd_driver {
76 /**
77 * Initialize the debug link so it can perform
78 * synchronous SWD operations.
79 * @param trn value from WCR: how many clocks
80 * to not drive the SWDIO line at certain points in
81 * the SWD protocol (at least 1 clock).
82 *
83 * As an example, this would switch a dual-mode debug adapter
84 * into SWD mode and out of JTAG mode.
85 *
86 * @return ERROR_OK on success, else a negative fault code.
87 */
88 int (*init)(uint8_t trn);
89
90
91 /**
92 * Synchronous read of an AP or DP register.
93 *
94 * @param cmd with APnDP/RnW/addr/parity bits
95 * @param where to store value to read from register
96 *
97 * @return SWD_ACK_* code for the transaction
98 * or (negative) fault code
99 */
100 int (*read_reg)(uint8_t cmd, uint32_t *value);
101
102 /**
103 * Synchronous write of an AP or DP register.
104 *
105 * @param cmd with APnDP/RnW/addr/parity bits
106 * @param value to be written to the register
107 *
108 * @return SWD_ACK_* code for the transaction
109 * or (negative) fault code
110 */
111 int (*write_reg)(uint8_t cmd, uint32_t value);
112
113 /**
114 * Synchronous block read of an AP or DP register.
115 *
116 * @param cmd with APnDP/RnW/addr/parity bits
117 * @param number of reads from register to be executed
118 * @param buffer to store data read from register
119 *
120 * @return SWD_ACK_* code for the transaction
121 * or (negative) fault code
122 */
123 int (*read_block)(uint8_t cmd, uint32_t blocksize, uint8_t *buffer);
124
125 /**
126 * Configures data collection from the Single-wire
127 * trace (SWO) signal.
128 * @param swo true if SWO data collection should be routed.
129 *
130 * For example, some debug adapters include a UART which
131 * is normally connected to a microcontroller's UART TX,
132 * but which may instead be connected to SWO for use in
133 * collecting ITM (and possibly ETM) trace data.
134 *
135 * @return ERROR_OK on success, else a negative fault code.
136 */
137 int *(*trace)(bool swo);
138 };
139
140 int swd_init_reset(struct command_context *cmd_ctx);
141 void swd_add_reset(int req_srst);
142
143 bool transport_is_swd(void);
144 bool transport_is_cmsis_dap(void);
145
146 #endif /* SWD_H */