src/jtag/ep93xx.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "log.h"
  25 #include "jtag.h"
  26 #include "bitbang.h"
  27
  28 #define TDO_BIT         1
  29 #define TDI_BIT         2
  30 #define TCK_BIT         4
  31 #define TMS_BIT         8
  32 #define TRST_BIT        16
  33 #define SRST_BIT        32
  34 #define VCC_BIT         64
  35
  36 /* system includes */
  37 #include <string.h>
  38 #include <stdlib.h>
  39 #include <stdio.h>
  40 #include <time.h>
  41 #include <sys/mman.h>
  42 #include <unistd.h>
  43 #include <fcntl.h>
  44
  45 static u8 output_value = 0x0;
  46 static int dev_mem_fd;
  47 static void *gpio_controller;
  48 static volatile u8 *gpio_data_register;
  49 static volatile u8 *gpio_data_direction_register;
  50
  51 /* low level command set
  52  */
  53 int ep93xx_read(void);
  54 void ep93xx_write(int tck, int tms, int tdi);
  55 void ep93xx_reset(int trst, int srst);
  56
  57 int ep93xx_speed(int speed);
  58 int ep93xx_register_commands(struct command_context_s *cmd_ctx);
  59 int ep93xx_init(void);
  60 int ep93xx_quit(void);
  61
  62 struct timespec ep93xx_zzzz;
  63
  64 jtag_interface_t ep93xx_interface =
  65 {
  66         .name = "ep93xx",
  67
  68         .execute_queue = bitbang_execute_queue,
  69
  70         .speed = ep93xx_speed,
  71         .register_commands = ep93xx_register_commands,
  72         .init = ep93xx_init,
  73         .quit = ep93xx_quit,
  74 };
  75
  76 bitbang_interface_t ep93xx_bitbang =
  77 {
  78         .read = ep93xx_read,
  79         .write = ep93xx_write,
  80         .reset = ep93xx_reset,
  81         .blink = 0,
  82 };
  83
  84 int ep93xx_read(void)
  85 {
  86         return !!(*gpio_data_register & TDO_BIT);
  87 }
  88
  89 void ep93xx_write(int tck, int tms, int tdi)
  90 {
  91         if (tck)
  92                 output_value |= TCK_BIT;
  93         else
  94                 output_value &= ~TCK_BIT;
  95
  96         if (tms)
  97                 output_value |= TMS_BIT;
  98         else
  99                 output_value &= ~TMS_BIT;
 100
 101         if (tdi)
 102                 output_value |= TDI_BIT;
 103         else
 104                 output_value &= ~TDI_BIT;
 105
 106         *gpio_data_register = output_value;
 107         nanosleep(&ep93xx_zzzz, NULL);
 108 }
 109
 110 /* (1) assert or (0) deassert reset lines */
 111 void ep93xx_reset(int trst, int srst)
 112 {
 113         if (trst == 0)
 114                 output_value |= TRST_BIT;
 115         else if (trst == 1)
 116                 output_value &= ~TRST_BIT;
 117
 118         if (srst == 0)
 119                 output_value |= SRST_BIT;
 120         else if (srst == 1)
 121                 output_value &= ~SRST_BIT;
 122
 123         *gpio_data_register = output_value;
 124         nanosleep(&ep93xx_zzzz, NULL);
 125 }
 126
 127 int ep93xx_speed(int speed)
 128 {
 129
 130         return ERROR_OK;
 131 }
 132
 133 int ep93xx_register_commands(struct command_context_s *cmd_ctx)
 134 {
 135
 136         return ERROR_OK;
 137 }
 138
 139 static int set_gonk_mode(void)
 140 {
 141         void *syscon;
 142         u32 devicecfg;
 143
 144         syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 145                         MAP_SHARED, dev_mem_fd, 0x80930000);
 146         if (syscon == MAP_FAILED) {
 147                 perror("mmap");
 148                 return ERROR_JTAG_INIT_FAILED;
 149         }
 150
 151         devicecfg = *((volatile int *)(syscon + 0x80));
 152         *((volatile int *)(syscon + 0xc0)) = 0xaa;
 153         *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
 154
 155         munmap(syscon, 4096);
 156
 157         return ERROR_OK;
 158 }
 159
 160 int ep93xx_init(void)
 161 {
 162         int ret;
 163
 164         bitbang_interface = &ep93xx_bitbang;
 165
 166         ep93xx_zzzz.tv_sec = 0;
 167         ep93xx_zzzz.tv_nsec = 10000000;
 168
 169         dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
 170         if (dev_mem_fd < 0) {
 171                 perror("open");
 172                 return ERROR_JTAG_INIT_FAILED;
 173         }
 174
 175         gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 176                                 MAP_SHARED, dev_mem_fd, 0x80840000);
 177         if (gpio_controller == MAP_FAILED) {
 178                 perror("mmap");
 179                 close(dev_mem_fd);
 180                 return ERROR_JTAG_INIT_FAILED;
 181         }
 182
 183         ret = set_gonk_mode();
 184         if (ret != ERROR_OK) {
 185                 munmap(gpio_controller, 4096);
 186                 close(dev_mem_fd);
 187                 return ret;
 188         }
 189
 190 #if 0
 191         /* Use GPIO port A.  */
 192         gpio_data_register = gpio_controller + 0x00;
 193         gpio_data_direction_register = gpio_controller + 0x10;
 194
 195
 196         /* Use GPIO port B.  */
 197         gpio_data_register = gpio_controller + 0x04;
 198         gpio_data_direction_register = gpio_controller + 0x14;
 199
 200         /* Use GPIO port C.  */
 201         gpio_data_register = gpio_controller + 0x08;
 202         gpio_data_direction_register = gpio_controller + 0x18;
 203
 204         /* Use GPIO port D.  */
 205         gpio_data_register = gpio_controller + 0x0c;
 206         gpio_data_direction_register = gpio_controller + 0x1c;
 207 #endif
 208
 209         /* Use GPIO port C.  */
 210         gpio_data_register = gpio_controller + 0x08;
 211         gpio_data_direction_register = gpio_controller + 0x18;
 212
 213         LOG_INFO("gpio_data_register      = %p\n", gpio_data_register);
 214         LOG_INFO("gpio_data_direction_reg = %p\n", gpio_data_direction_register);
 215         /*
 216          * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
 217          * TMS, TRST, SRST) as outputs.  Drive TDI and TCK low, and
 218          * TMS/TRST/SRST high.
 219          */
 220         output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 221         *gpio_data_register = output_value;
 222         nanosleep(&ep93xx_zzzz, NULL);
 223
 224         /*
 225          * Configure the direction register.  1 = output, 0 = input.
 226          */
 227         *gpio_data_direction_register =
 228                 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 229
 230         nanosleep(&ep93xx_zzzz, NULL);
 231         return ERROR_OK;
 232 }
 233
 234 int ep93xx_quit(void)
 235 {
 236
 237         return ERROR_OK;
 238 }