src/jtag/drivers/ep93xx.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifdef HAVE_CONFIG_H
  20 #include "config.h"
  21 #endif
  22
  23 #include <jtag/interface.h>
  24 #include "bitbang.h"
  25
  26 #define TDO_BIT         1
  27 #define TDI_BIT         2
  28 #define TCK_BIT         4
  29 #define TMS_BIT         8
  30 #define TRST_BIT        16
  31 #define SRST_BIT        32
  32 #define VCC_BIT         64
  33
  34 #include <sys/mman.h>
  35
  36 static uint8_t output_value;
  37 static int dev_mem_fd;
  38 static void *gpio_controller;
  39 static volatile uint8_t *gpio_data_register;
  40 static volatile uint8_t *gpio_data_direction_register;
  41
  42 /* low level command set
  43  */
  44 static bb_value_t ep93xx_read(void);
  45 static int ep93xx_write(int tck, int tms, int tdi);
  46 static int ep93xx_reset(int trst, int srst);
  47
  48 static int ep93xx_init(void);
  49 static int ep93xx_quit(void);
  50
  51 struct timespec ep93xx_zzzz;
  52
  53 struct jtag_interface ep93xx_interface = {
  54         .name = "ep93xx",
  55
  56         .supported = DEBUG_CAP_TMS_SEQ,
  57         .execute_queue = bitbang_execute_queue,
  58         .transports = jtag_only,
  59
  60         .init = ep93xx_init,
  61         .quit = ep93xx_quit,
  62         .reset = ep93xx_reset,
  63 };
  64
  65 static struct bitbang_interface ep93xx_bitbang = {
  66         .read = ep93xx_read,
  67         .write = ep93xx_write,
  68         .blink = 0,
  69 };
  70
  71 static bb_value_t ep93xx_read(void)
  72 {
  73         return (*gpio_data_register & TDO_BIT) ? BB_HIGH : BB_LOW;
  74 }
  75
  76 static int ep93xx_write(int tck, int tms, int tdi)
  77 {
  78         if (tck)
  79                 output_value |= TCK_BIT;
  80         else
  81                 output_value &= ~TCK_BIT;
  82
  83         if (tms)
  84                 output_value |= TMS_BIT;
  85         else
  86                 output_value &= ~TMS_BIT;
  87
  88         if (tdi)
  89                 output_value |= TDI_BIT;
  90         else
  91                 output_value &= ~TDI_BIT;
  92
  93         *gpio_data_register = output_value;
  94         nanosleep(&ep93xx_zzzz, NULL);
  95
  96         return ERROR_OK;
  97 }
  98
  99 /* (1) assert or (0) deassert reset lines */
 100 static int ep93xx_reset(int trst, int srst)
 101 {
 102         if (trst == 0)
 103                 output_value |= TRST_BIT;
 104         else if (trst == 1)
 105                 output_value &= ~TRST_BIT;
 106
 107         if (srst == 0)
 108                 output_value |= SRST_BIT;
 109         else if (srst == 1)
 110                 output_value &= ~SRST_BIT;
 111
 112         *gpio_data_register = output_value;
 113         nanosleep(&ep93xx_zzzz, NULL);
 114
 115         return ERROR_OK;
 116 }
 117
 118 static int set_gonk_mode(void)
 119 {
 120         void *syscon;
 121         uint32_t devicecfg;
 122
 123         syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 124                         MAP_SHARED, dev_mem_fd, 0x80930000);
 125         if (syscon == MAP_FAILED) {
 126                 perror("mmap");
 127                 return ERROR_JTAG_INIT_FAILED;
 128         }
 129
 130         devicecfg = *((volatile int *)(syscon + 0x80));
 131         *((volatile int *)(syscon + 0xc0)) = 0xaa;
 132         *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
 133
 134         munmap(syscon, 4096);
 135
 136         return ERROR_OK;
 137 }
 138
 139 static int ep93xx_init(void)
 140 {
 141         int ret;
 142
 143         bitbang_interface = &ep93xx_bitbang;
 144
 145         ep93xx_zzzz.tv_sec = 0;
 146         ep93xx_zzzz.tv_nsec = 10000000;
 147
 148         dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
 149         if (dev_mem_fd < 0) {
 150                 perror("open");
 151                 return ERROR_JTAG_INIT_FAILED;
 152         }
 153
 154         gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 155                                 MAP_SHARED, dev_mem_fd, 0x80840000);
 156         if (gpio_controller == MAP_FAILED) {
 157                 perror("mmap");
 158                 close(dev_mem_fd);
 159                 return ERROR_JTAG_INIT_FAILED;
 160         }
 161
 162         ret = set_gonk_mode();
 163         if (ret != ERROR_OK) {
 164                 munmap(gpio_controller, 4096);
 165                 close(dev_mem_fd);
 166                 return ret;
 167         }
 168
 169 #if 0
 170         /* Use GPIO port A.  */
 171         gpio_data_register = gpio_controller + 0x00;
 172         gpio_data_direction_register = gpio_controller + 0x10;
 173
 174
 175         /* Use GPIO port B.  */
 176         gpio_data_register = gpio_controller + 0x04;
 177         gpio_data_direction_register = gpio_controller + 0x14;
 178
 179         /* Use GPIO port C.  */
 180         gpio_data_register = gpio_controller + 0x08;
 181         gpio_data_direction_register = gpio_controller + 0x18;
 182
 183         /* Use GPIO port D.  */
 184         gpio_data_register = gpio_controller + 0x0c;
 185         gpio_data_direction_register = gpio_controller + 0x1c;
 186 #endif
 187
 188         /* Use GPIO port C.  */
 189         gpio_data_register = gpio_controller + 0x08;
 190         gpio_data_direction_register = gpio_controller + 0x18;
 191
 192         LOG_INFO("gpio_data_register      = %p", gpio_data_register);
 193         LOG_INFO("gpio_data_direction_reg = %p", gpio_data_direction_register);
 194         /*
 195          * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
 196          * TMS, TRST, SRST) as outputs.  Drive TDI and TCK low, and
 197          * TMS/TRST/SRST high.
 198          */
 199         output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 200         *gpio_data_register = output_value;
 201         nanosleep(&ep93xx_zzzz, NULL);
 202
 203         /*
 204          * Configure the direction register.  1 = output, 0 = input.
 205          */
 206         *gpio_data_direction_register =
 207                 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 208
 209         nanosleep(&ep93xx_zzzz, NULL);
 210         return ERROR_OK;
 211 }
 212
 213 static int ep93xx_quit(void)
 214 {
 215
 216         return ERROR_OK;
 217 }