Remove support for the GPL incompatible FTDI D2XX library
[openocd.git] / src / jtag / drivers / ep93xx.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include <jtag/interface.h>
24 #include "bitbang.h"
25
26 #define TDO_BIT 1
27 #define TDI_BIT 2
28 #define TCK_BIT 4
29 #define TMS_BIT 8
30 #define TRST_BIT 16
31 #define SRST_BIT 32
32 #define VCC_BIT 64
33
34 #include <sys/mman.h>
35
36 static uint8_t output_value;
37 static int dev_mem_fd;
38 static void *gpio_controller;
39 static volatile uint8_t *gpio_data_register;
40 static volatile uint8_t *gpio_data_direction_register;
41
42 /* low level command set
43 */
44 static int ep93xx_read(void);
45 static void ep93xx_write(int tck, int tms, int tdi);
46 static void ep93xx_reset(int trst, int srst);
47
48 static int ep93xx_init(void);
49 static int ep93xx_quit(void);
50
51 struct timespec ep93xx_zzzz;
52
53 struct jtag_interface ep93xx_interface = {
54 .name = "ep93xx",
55
56 .supported = DEBUG_CAP_TMS_SEQ,
57 .execute_queue = bitbang_execute_queue,
58
59 .init = ep93xx_init,
60 .quit = ep93xx_quit,
61 };
62
63 static struct bitbang_interface ep93xx_bitbang = {
64 .read = ep93xx_read,
65 .write = ep93xx_write,
66 .reset = ep93xx_reset,
67 .blink = 0,
68 };
69
70 static int ep93xx_read(void)
71 {
72 return !!(*gpio_data_register & TDO_BIT);
73 }
74
75 static void ep93xx_write(int tck, int tms, int tdi)
76 {
77 if (tck)
78 output_value |= TCK_BIT;
79 else
80 output_value &= ~TCK_BIT;
81
82 if (tms)
83 output_value |= TMS_BIT;
84 else
85 output_value &= ~TMS_BIT;
86
87 if (tdi)
88 output_value |= TDI_BIT;
89 else
90 output_value &= ~TDI_BIT;
91
92 *gpio_data_register = output_value;
93 nanosleep(&ep93xx_zzzz, NULL);
94 }
95
96 /* (1) assert or (0) deassert reset lines */
97 static void ep93xx_reset(int trst, int srst)
98 {
99 if (trst == 0)
100 output_value |= TRST_BIT;
101 else if (trst == 1)
102 output_value &= ~TRST_BIT;
103
104 if (srst == 0)
105 output_value |= SRST_BIT;
106 else if (srst == 1)
107 output_value &= ~SRST_BIT;
108
109 *gpio_data_register = output_value;
110 nanosleep(&ep93xx_zzzz, NULL);
111 }
112
113 static int set_gonk_mode(void)
114 {
115 void *syscon;
116 uint32_t devicecfg;
117
118 syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
119 MAP_SHARED, dev_mem_fd, 0x80930000);
120 if (syscon == MAP_FAILED) {
121 perror("mmap");
122 return ERROR_JTAG_INIT_FAILED;
123 }
124
125 devicecfg = *((volatile int *)(syscon + 0x80));
126 *((volatile int *)(syscon + 0xc0)) = 0xaa;
127 *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
128
129 munmap(syscon, 4096);
130
131 return ERROR_OK;
132 }
133
134 static int ep93xx_init(void)
135 {
136 int ret;
137
138 bitbang_interface = &ep93xx_bitbang;
139
140 ep93xx_zzzz.tv_sec = 0;
141 ep93xx_zzzz.tv_nsec = 10000000;
142
143 dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
144 if (dev_mem_fd < 0) {
145 perror("open");
146 return ERROR_JTAG_INIT_FAILED;
147 }
148
149 gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
150 MAP_SHARED, dev_mem_fd, 0x80840000);
151 if (gpio_controller == MAP_FAILED) {
152 perror("mmap");
153 close(dev_mem_fd);
154 return ERROR_JTAG_INIT_FAILED;
155 }
156
157 ret = set_gonk_mode();
158 if (ret != ERROR_OK) {
159 munmap(gpio_controller, 4096);
160 close(dev_mem_fd);
161 return ret;
162 }
163
164 #if 0
165 /* Use GPIO port A. */
166 gpio_data_register = gpio_controller + 0x00;
167 gpio_data_direction_register = gpio_controller + 0x10;
168
169
170 /* Use GPIO port B. */
171 gpio_data_register = gpio_controller + 0x04;
172 gpio_data_direction_register = gpio_controller + 0x14;
173
174 /* Use GPIO port C. */
175 gpio_data_register = gpio_controller + 0x08;
176 gpio_data_direction_register = gpio_controller + 0x18;
177
178 /* Use GPIO port D. */
179 gpio_data_register = gpio_controller + 0x0c;
180 gpio_data_direction_register = gpio_controller + 0x1c;
181 #endif
182
183 /* Use GPIO port C. */
184 gpio_data_register = gpio_controller + 0x08;
185 gpio_data_direction_register = gpio_controller + 0x18;
186
187 LOG_INFO("gpio_data_register = %p", gpio_data_register);
188 LOG_INFO("gpio_data_direction_reg = %p", gpio_data_direction_register);
189 /*
190 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
191 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
192 * TMS/TRST/SRST high.
193 */
194 output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
195 *gpio_data_register = output_value;
196 nanosleep(&ep93xx_zzzz, NULL);
197
198 /*
199 * Configure the direction register. 1 = output, 0 = input.
200 */
201 *gpio_data_direction_register =
202 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
203
204 nanosleep(&ep93xx_zzzz, NULL);
205 return ERROR_OK;
206 }
207
208 static int ep93xx_quit(void)
209 {
210
211 return ERROR_OK;
212 }