src/jtag/drivers/ep93xx.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include <jtag/interface.h>
  26 #include "bitbang.h"
  27
  28 #define TDO_BIT         1
  29 #define TDI_BIT         2
  30 #define TCK_BIT         4
  31 #define TMS_BIT         8
  32 #define TRST_BIT        16
  33 #define SRST_BIT        32
  34 #define VCC_BIT         64
  35
  36 #include <sys/mman.h>
  37
  38 static uint8_t output_value;
  39 static int dev_mem_fd;
  40 static void *gpio_controller;
  41 static volatile uint8_t *gpio_data_register;
  42 static volatile uint8_t *gpio_data_direction_register;
  43
  44 /* low level command set
  45  */
  46 static int ep93xx_read(void);
  47 static void ep93xx_write(int tck, int tms, int tdi);
  48 static void ep93xx_reset(int trst, int srst);
  49
  50 static int ep93xx_init(void);
  51 static int ep93xx_quit(void);
  52
  53 struct timespec ep93xx_zzzz;
  54
  55 struct jtag_interface ep93xx_interface = {
  56         .name = "ep93xx",
  57
  58         .supported = DEBUG_CAP_TMS_SEQ,
  59         .execute_queue = bitbang_execute_queue,
  60
  61         .init = ep93xx_init,
  62         .quit = ep93xx_quit,
  63 };
  64
  65 static struct bitbang_interface ep93xx_bitbang = {
  66         .read = ep93xx_read,
  67         .write = ep93xx_write,
  68         .reset = ep93xx_reset,
  69         .blink = 0,
  70 };
  71
  72 static int ep93xx_read(void)
  73 {
  74         return !!(*gpio_data_register & TDO_BIT);
  75 }
  76
  77 static void ep93xx_write(int tck, int tms, int tdi)
  78 {
  79         if (tck)
  80                 output_value |= TCK_BIT;
  81         else
  82                 output_value &= ~TCK_BIT;
  83
  84         if (tms)
  85                 output_value |= TMS_BIT;
  86         else
  87                 output_value &= ~TMS_BIT;
  88
  89         if (tdi)
  90                 output_value |= TDI_BIT;
  91         else
  92                 output_value &= ~TDI_BIT;
  93
  94         *gpio_data_register = output_value;
  95         nanosleep(&ep93xx_zzzz, NULL);
  96 }
  97
  98 /* (1) assert or (0) deassert reset lines */
  99 static void ep93xx_reset(int trst, int srst)
 100 {
 101         if (trst == 0)
 102                 output_value |= TRST_BIT;
 103         else if (trst == 1)
 104                 output_value &= ~TRST_BIT;
 105
 106         if (srst == 0)
 107                 output_value |= SRST_BIT;
 108         else if (srst == 1)
 109                 output_value &= ~SRST_BIT;
 110
 111         *gpio_data_register = output_value;
 112         nanosleep(&ep93xx_zzzz, NULL);
 113 }
 114
 115 static int set_gonk_mode(void)
 116 {
 117         void *syscon;
 118         uint32_t devicecfg;
 119
 120         syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 121                         MAP_SHARED, dev_mem_fd, 0x80930000);
 122         if (syscon == MAP_FAILED) {
 123                 perror("mmap");
 124                 return ERROR_JTAG_INIT_FAILED;
 125         }
 126
 127         devicecfg = *((volatile int *)(syscon + 0x80));
 128         *((volatile int *)(syscon + 0xc0)) = 0xaa;
 129         *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
 130
 131         munmap(syscon, 4096);
 132
 133         return ERROR_OK;
 134 }
 135
 136 static int ep93xx_init(void)
 137 {
 138         int ret;
 139
 140         bitbang_interface = &ep93xx_bitbang;
 141
 142         ep93xx_zzzz.tv_sec = 0;
 143         ep93xx_zzzz.tv_nsec = 10000000;
 144
 145         dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
 146         if (dev_mem_fd < 0) {
 147                 perror("open");
 148                 return ERROR_JTAG_INIT_FAILED;
 149         }
 150
 151         gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 152                                 MAP_SHARED, dev_mem_fd, 0x80840000);
 153         if (gpio_controller == MAP_FAILED) {
 154                 perror("mmap");
 155                 close(dev_mem_fd);
 156                 return ERROR_JTAG_INIT_FAILED;
 157         }
 158
 159         ret = set_gonk_mode();
 160         if (ret != ERROR_OK) {
 161                 munmap(gpio_controller, 4096);
 162                 close(dev_mem_fd);
 163                 return ret;
 164         }
 165
 166 #if 0
 167         /* Use GPIO port A.  */
 168         gpio_data_register = gpio_controller + 0x00;
 169         gpio_data_direction_register = gpio_controller + 0x10;
 170
 171
 172         /* Use GPIO port B.  */
 173         gpio_data_register = gpio_controller + 0x04;
 174         gpio_data_direction_register = gpio_controller + 0x14;
 175
 176         /* Use GPIO port C.  */
 177         gpio_data_register = gpio_controller + 0x08;
 178         gpio_data_direction_register = gpio_controller + 0x18;
 179
 180         /* Use GPIO port D.  */
 181         gpio_data_register = gpio_controller + 0x0c;
 182         gpio_data_direction_register = gpio_controller + 0x1c;
 183 #endif
 184
 185         /* Use GPIO port C.  */
 186         gpio_data_register = gpio_controller + 0x08;
 187         gpio_data_direction_register = gpio_controller + 0x18;
 188
 189         LOG_INFO("gpio_data_register      = %p", gpio_data_register);
 190         LOG_INFO("gpio_data_direction_reg = %p", gpio_data_direction_register);
 191         /*
 192          * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
 193          * TMS, TRST, SRST) as outputs.  Drive TDI and TCK low, and
 194          * TMS/TRST/SRST high.
 195          */
 196         output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 197         *gpio_data_register = output_value;
 198         nanosleep(&ep93xx_zzzz, NULL);
 199
 200         /*
 201          * Configure the direction register.  1 = output, 0 = input.
 202          */
 203         *gpio_data_direction_register =
 204                 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 205
 206         nanosleep(&ep93xx_zzzz, NULL);
 207         return ERROR_OK;
 208 }
 209
 210 static int ep93xx_quit(void)
 211 {
 212
 213         return ERROR_OK;
 214 }