src/jtag/drivers/ep93xx.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifdef HAVE_CONFIG_H
  20 #include "config.h"
  21 #endif
  22
  23 #include <jtag/interface.h>
  24 #include "bitbang.h"
  25
  26 #define TDO_BIT         1
  27 #define TDI_BIT         2
  28 #define TCK_BIT         4
  29 #define TMS_BIT         8
  30 #define TRST_BIT        16
  31 #define SRST_BIT        32
  32 #define VCC_BIT         64
  33
  34 #include <sys/mman.h>
  35
  36 static uint8_t output_value;
  37 static int dev_mem_fd;
  38 static void *gpio_controller;
  39 static volatile uint8_t *gpio_data_register;
  40 static volatile uint8_t *gpio_data_direction_register;
  41
  42 /* low level command set
  43  */
  44 static bb_value_t ep93xx_read(void);
  45 static int ep93xx_write(int tck, int tms, int tdi);
  46 static int ep93xx_reset(int trst, int srst);
  47
  48 static int ep93xx_init(void);
  49 static int ep93xx_quit(void);
  50
  51 struct timespec ep93xx_zzzz;
  52
  53 static struct jtag_interface ep93xx_interface = {
  54         .supported = DEBUG_CAP_TMS_SEQ,
  55         .execute_queue = bitbang_execute_queue,
  56 };
  57
  58 struct adapter_driver ep93xx_adapter_driver = {
  59         .name = "ep93xx",
  60         .transports = jtag_only,
  61
  62         .init = ep93xx_init,
  63         .quit = ep93xx_quit,
  64         .reset = ep93xx_reset,
  65
  66         .jtag_ops = &ep93xx_interface,
  67 };
  68
  69 static struct bitbang_interface ep93xx_bitbang = {
  70         .read = ep93xx_read,
  71         .write = ep93xx_write,
  72         .blink = 0,
  73 };
  74
  75 static bb_value_t ep93xx_read(void)
  76 {
  77         return (*gpio_data_register & TDO_BIT) ? BB_HIGH : BB_LOW;
  78 }
  79
  80 static int ep93xx_write(int tck, int tms, int tdi)
  81 {
  82         if (tck)
  83                 output_value |= TCK_BIT;
  84         else
  85                 output_value &= ~TCK_BIT;
  86
  87         if (tms)
  88                 output_value |= TMS_BIT;
  89         else
  90                 output_value &= ~TMS_BIT;
  91
  92         if (tdi)
  93                 output_value |= TDI_BIT;
  94         else
  95                 output_value &= ~TDI_BIT;
  96
  97         *gpio_data_register = output_value;
  98         nanosleep(&ep93xx_zzzz, NULL);
  99
 100         return ERROR_OK;
 101 }
 102
 103 /* (1) assert or (0) deassert reset lines */
 104 static int ep93xx_reset(int trst, int srst)
 105 {
 106         if (trst == 0)
 107                 output_value |= TRST_BIT;
 108         else if (trst == 1)
 109                 output_value &= ~TRST_BIT;
 110
 111         if (srst == 0)
 112                 output_value |= SRST_BIT;
 113         else if (srst == 1)
 114                 output_value &= ~SRST_BIT;
 115
 116         *gpio_data_register = output_value;
 117         nanosleep(&ep93xx_zzzz, NULL);
 118
 119         return ERROR_OK;
 120 }
 121
 122 static int set_gonk_mode(void)
 123 {
 124         void *syscon;
 125         uint32_t devicecfg;
 126
 127         syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 128                         MAP_SHARED, dev_mem_fd, 0x80930000);
 129         if (syscon == MAP_FAILED) {
 130                 perror("mmap");
 131                 return ERROR_JTAG_INIT_FAILED;
 132         }
 133
 134         devicecfg = *((volatile int *)(syscon + 0x80));
 135         *((volatile int *)(syscon + 0xc0)) = 0xaa;
 136         *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
 137
 138         munmap(syscon, 4096);
 139
 140         return ERROR_OK;
 141 }
 142
 143 static int ep93xx_init(void)
 144 {
 145         int ret;
 146
 147         bitbang_interface = &ep93xx_bitbang;
 148
 149         ep93xx_zzzz.tv_sec = 0;
 150         ep93xx_zzzz.tv_nsec = 10000000;
 151
 152         dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
 153         if (dev_mem_fd < 0) {
 154                 perror("open");
 155                 return ERROR_JTAG_INIT_FAILED;
 156         }
 157
 158         gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 159                                 MAP_SHARED, dev_mem_fd, 0x80840000);
 160         if (gpio_controller == MAP_FAILED) {
 161                 perror("mmap");
 162                 close(dev_mem_fd);
 163                 return ERROR_JTAG_INIT_FAILED;
 164         }
 165
 166         ret = set_gonk_mode();
 167         if (ret != ERROR_OK) {
 168                 munmap(gpio_controller, 4096);
 169                 close(dev_mem_fd);
 170                 return ret;
 171         }
 172
 173 #if 0
 174         /* Use GPIO port A.  */
 175         gpio_data_register = gpio_controller + 0x00;
 176         gpio_data_direction_register = gpio_controller + 0x10;
 177
 178
 179         /* Use GPIO port B.  */
 180         gpio_data_register = gpio_controller + 0x04;
 181         gpio_data_direction_register = gpio_controller + 0x14;
 182
 183         /* Use GPIO port C.  */
 184         gpio_data_register = gpio_controller + 0x08;
 185         gpio_data_direction_register = gpio_controller + 0x18;
 186
 187         /* Use GPIO port D.  */
 188         gpio_data_register = gpio_controller + 0x0c;
 189         gpio_data_direction_register = gpio_controller + 0x1c;
 190 #endif
 191
 192         /* Use GPIO port C.  */
 193         gpio_data_register = gpio_controller + 0x08;
 194         gpio_data_direction_register = gpio_controller + 0x18;
 195
 196         LOG_INFO("gpio_data_register      = %p", gpio_data_register);
 197         LOG_INFO("gpio_data_direction_reg = %p", gpio_data_direction_register);
 198         /*
 199          * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
 200          * TMS, TRST, SRST) as outputs.  Drive TDI and TCK low, and
 201          * TMS/TRST/SRST high.
 202          */
 203         output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 204         *gpio_data_register = output_value;
 205         nanosleep(&ep93xx_zzzz, NULL);
 206
 207         /*
 208          * Configure the direction register.  1 = output, 0 = input.
 209          */
 210         *gpio_data_direction_register =
 211                 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 212
 213         nanosleep(&ep93xx_zzzz, NULL);
 214         return ERROR_OK;
 215 }
 216
 217 static int ep93xx_quit(void)
 218 {
 219
 220         return ERROR_OK;
 221 }