da4fb334819755405b83c39f66d596a8c4821c0f
[openocd.git] / src / jtag / drivers / bitbang.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
21
22 /* 2014-12: Addition of the SWD protocol support is based on the initial work
23 * by Paul Fertser and modifications by Jean-Christian de Rivaz. */
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "bitbang.h"
30 #include <jtag/interface.h>
31 #include <jtag/commands.h>
32
33 /**
34 * Function bitbang_stableclocks
35 * issues a number of clock cycles while staying in a stable state.
36 * Because the TMS value required to stay in the RESET state is a 1, whereas
37 * the TMS value required to stay in any of the other stable states is a 0,
38 * this function checks the current stable state to decide on the value of TMS
39 * to use.
40 */
41 static int bitbang_stableclocks(int num_cycles);
42
43 static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk);
44
45 struct bitbang_interface *bitbang_interface;
46
47 /* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
48 *
49 * Set this to 1 and str912 reset halt will fail.
50 *
51 * If someone can submit a patch with an explanation it will be greatly
52 * appreciated, but as far as I can tell (ØH) DCLK is generated upon
53 * clk = 0 in TAP_IDLE. Good luck deducing that from the ARM documentation!
54 * The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE
55 * state". With hardware there is no such thing as *while* in a state. There
56 * are only edges. So clk => 0 is in fact a very subtle state transition that
57 * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#&
58 *
59 * For "reset halt" the last thing that happens before srst is asserted
60 * is that the breakpoint is set up. If DCLK is not wiggled one last
61 * time before the reset, then the breakpoint is not set up and
62 * "reset halt" will fail to halt.
63 *
64 */
65 #define CLOCK_IDLE() 0
66
67 /* The bitbang driver leaves the TCK 0 when in idle */
68 static void bitbang_end_state(tap_state_t state)
69 {
70 assert(tap_is_state_stable(state));
71 tap_set_end_state(state);
72 }
73
74 static int bitbang_state_move(int skip)
75 {
76 int i = 0, tms = 0;
77 uint8_t tms_scan = tap_get_tms_path(tap_get_state(), tap_get_end_state());
78 int tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
79
80 for (i = skip; i < tms_count; i++) {
81 tms = (tms_scan >> i) & 1;
82 if (bitbang_interface->write(0, tms, 0) != ERROR_OK)
83 return ERROR_FAIL;
84 if (bitbang_interface->write(1, tms, 0) != ERROR_OK)
85 return ERROR_FAIL;
86 }
87 if (bitbang_interface->write(CLOCK_IDLE(), tms, 0) != ERROR_OK)
88 return ERROR_FAIL;
89
90 tap_set_state(tap_get_end_state());
91 return ERROR_OK;
92 }
93
94 /**
95 * Clock a bunch of TMS (or SWDIO) transitions, to change the JTAG
96 * (or SWD) state machine.
97 */
98 static int bitbang_execute_tms(struct jtag_command *cmd)
99 {
100 unsigned num_bits = cmd->cmd.tms->num_bits;
101 const uint8_t *bits = cmd->cmd.tms->bits;
102
103 DEBUG_JTAG_IO("TMS: %d bits", num_bits);
104
105 int tms = 0;
106 for (unsigned i = 0; i < num_bits; i++) {
107 tms = ((bits[i/8] >> (i % 8)) & 1);
108 if (bitbang_interface->write(0, tms, 0) != ERROR_OK)
109 return ERROR_FAIL;
110 if (bitbang_interface->write(1, tms, 0) != ERROR_OK)
111 return ERROR_FAIL;
112 }
113 if (bitbang_interface->write(CLOCK_IDLE(), tms, 0) != ERROR_OK)
114 return ERROR_FAIL;
115
116 return ERROR_OK;
117 }
118
119 static int bitbang_path_move(struct pathmove_command *cmd)
120 {
121 int num_states = cmd->num_states;
122 int state_count;
123 int tms = 0;
124
125 state_count = 0;
126 while (num_states) {
127 if (tap_state_transition(tap_get_state(), false) == cmd->path[state_count])
128 tms = 0;
129 else if (tap_state_transition(tap_get_state(), true) == cmd->path[state_count])
130 tms = 1;
131 else {
132 LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition",
133 tap_state_name(tap_get_state()),
134 tap_state_name(cmd->path[state_count]));
135 exit(-1);
136 }
137
138 if (bitbang_interface->write(0, tms, 0) != ERROR_OK)
139 return ERROR_FAIL;
140 if (bitbang_interface->write(1, tms, 0) != ERROR_OK)
141 return ERROR_FAIL;
142
143 tap_set_state(cmd->path[state_count]);
144 state_count++;
145 num_states--;
146 }
147
148 if (bitbang_interface->write(CLOCK_IDLE(), tms, 0) != ERROR_OK)
149 return ERROR_FAIL;
150
151 tap_set_end_state(tap_get_state());
152 return ERROR_OK;
153 }
154
155 static int bitbang_runtest(int num_cycles)
156 {
157 int i;
158
159 tap_state_t saved_end_state = tap_get_end_state();
160
161 /* only do a state_move when we're not already in IDLE */
162 if (tap_get_state() != TAP_IDLE) {
163 bitbang_end_state(TAP_IDLE);
164 if (bitbang_state_move(0) != ERROR_OK)
165 return ERROR_FAIL;
166 }
167
168 /* execute num_cycles */
169 for (i = 0; i < num_cycles; i++) {
170 if (bitbang_interface->write(0, 0, 0) != ERROR_OK)
171 return ERROR_FAIL;
172 if (bitbang_interface->write(1, 0, 0) != ERROR_OK)
173 return ERROR_FAIL;
174 }
175 if (bitbang_interface->write(CLOCK_IDLE(), 0, 0) != ERROR_OK)
176 return ERROR_FAIL;
177
178 /* finish in end_state */
179 bitbang_end_state(saved_end_state);
180 if (tap_get_state() != tap_get_end_state())
181 if (bitbang_state_move(0) != ERROR_OK)
182 return ERROR_FAIL;
183
184 return ERROR_OK;
185 }
186
187 static int bitbang_stableclocks(int num_cycles)
188 {
189 int tms = (tap_get_state() == TAP_RESET ? 1 : 0);
190 int i;
191
192 /* send num_cycles clocks onto the cable */
193 for (i = 0; i < num_cycles; i++) {
194 if (bitbang_interface->write(1, tms, 0) != ERROR_OK)
195 return ERROR_FAIL;
196 if (bitbang_interface->write(0, tms, 0) != ERROR_OK)
197 return ERROR_FAIL;
198 }
199
200 return ERROR_OK;
201 }
202
203 static int bitbang_scan(bool ir_scan, enum scan_type type, uint8_t *buffer,
204 unsigned scan_size)
205 {
206 tap_state_t saved_end_state = tap_get_end_state();
207 unsigned bit_cnt;
208
209 if (!((!ir_scan &&
210 (tap_get_state() == TAP_DRSHIFT)) ||
211 (ir_scan && (tap_get_state() == TAP_IRSHIFT)))) {
212 if (ir_scan)
213 bitbang_end_state(TAP_IRSHIFT);
214 else
215 bitbang_end_state(TAP_DRSHIFT);
216
217 if (bitbang_state_move(0) != ERROR_OK)
218 return ERROR_FAIL;
219 bitbang_end_state(saved_end_state);
220 }
221
222 size_t buffered = 0;
223 for (bit_cnt = 0; bit_cnt < scan_size; bit_cnt++) {
224 int tms = (bit_cnt == scan_size-1) ? 1 : 0;
225 int tdi;
226 int bytec = bit_cnt/8;
227 int bcval = 1 << (bit_cnt % 8);
228
229 /* if we're just reading the scan, but don't care about the output
230 * default to outputting 'low', this also makes valgrind traces more readable,
231 * as it removes the dependency on an uninitialised value
232 */
233 tdi = 0;
234 if ((type != SCAN_IN) && (buffer[bytec] & bcval))
235 tdi = 1;
236
237 if (bitbang_interface->write(0, tms, tdi) != ERROR_OK)
238 return ERROR_FAIL;
239
240 if (type != SCAN_OUT) {
241 if (bitbang_interface->buf_size) {
242 if (bitbang_interface->sample() != ERROR_OK)
243 return ERROR_FAIL;
244 buffered++;
245 } else {
246 switch (bitbang_interface->read()) {
247 case BB_LOW:
248 buffer[bytec] &= ~bcval;
249 break;
250 case BB_HIGH:
251 buffer[bytec] |= bcval;
252 break;
253 default:
254 return ERROR_FAIL;
255 }
256 }
257 }
258
259 if (bitbang_interface->write(1, tms, tdi) != ERROR_OK)
260 return ERROR_FAIL;
261
262 if (type != SCAN_OUT && bitbang_interface->buf_size &&
263 (buffered == bitbang_interface->buf_size ||
264 bit_cnt == scan_size - 1)) {
265 for (unsigned i = bit_cnt + 1 - buffered; i <= bit_cnt; i++) {
266 switch (bitbang_interface->read_sample()) {
267 case BB_LOW:
268 buffer[i/8] &= ~(1 << (i % 8));
269 break;
270 case BB_HIGH:
271 buffer[i/8] |= 1 << (i % 8);
272 break;
273 default:
274 return ERROR_FAIL;
275 }
276 }
277 buffered = 0;
278 }
279 }
280
281 if (tap_get_state() != tap_get_end_state()) {
282 /* we *KNOW* the above loop transitioned out of
283 * the shift state, so we skip the first state
284 * and move directly to the end state.
285 */
286 if (bitbang_state_move(1) != ERROR_OK)
287 return ERROR_FAIL;
288 }
289 return ERROR_OK;
290 }
291
292 int bitbang_execute_queue(void)
293 {
294 struct jtag_command *cmd = jtag_command_queue; /* currently processed command */
295 int scan_size;
296 enum scan_type type;
297 uint8_t *buffer;
298 int retval;
299
300 if (!bitbang_interface) {
301 LOG_ERROR("BUG: Bitbang interface called, but not yet initialized");
302 exit(-1);
303 }
304
305 /* return ERROR_OK, unless a jtag_read_buffer returns a failed check
306 * that wasn't handled by a caller-provided error handler
307 */
308 retval = ERROR_OK;
309
310 if (bitbang_interface->blink) {
311 if (bitbang_interface->blink(1) != ERROR_OK)
312 return ERROR_FAIL;
313 }
314
315 while (cmd) {
316 switch (cmd->type) {
317 case JTAG_RESET:
318 #ifdef _DEBUG_JTAG_IO_
319 LOG_DEBUG("reset trst: %i srst %i",
320 cmd->cmd.reset->trst,
321 cmd->cmd.reset->srst);
322 #endif
323 if ((cmd->cmd.reset->trst == 1) ||
324 (cmd->cmd.reset->srst && (jtag_get_reset_config() & RESET_SRST_PULLS_TRST)))
325 tap_set_state(TAP_RESET);
326 if (bitbang_interface->reset(cmd->cmd.reset->trst,
327 cmd->cmd.reset->srst) != ERROR_OK)
328 return ERROR_FAIL;
329 break;
330 case JTAG_RUNTEST:
331 #ifdef _DEBUG_JTAG_IO_
332 LOG_DEBUG("runtest %i cycles, end in %s",
333 cmd->cmd.runtest->num_cycles,
334 tap_state_name(cmd->cmd.runtest->end_state));
335 #endif
336 bitbang_end_state(cmd->cmd.runtest->end_state);
337 if (bitbang_runtest(cmd->cmd.runtest->num_cycles) != ERROR_OK)
338 return ERROR_FAIL;
339 break;
340
341 case JTAG_STABLECLOCKS:
342 /* this is only allowed while in a stable state. A check for a stable
343 * state was done in jtag_add_clocks()
344 */
345 if (bitbang_stableclocks(cmd->cmd.stableclocks->num_cycles) != ERROR_OK)
346 return ERROR_FAIL;
347 break;
348
349 case JTAG_TLR_RESET:
350 #ifdef _DEBUG_JTAG_IO_
351 LOG_DEBUG("statemove end in %s",
352 tap_state_name(cmd->cmd.statemove->end_state));
353 #endif
354 bitbang_end_state(cmd->cmd.statemove->end_state);
355 if (bitbang_state_move(0) != ERROR_OK)
356 return ERROR_FAIL;
357 break;
358 case JTAG_PATHMOVE:
359 #ifdef _DEBUG_JTAG_IO_
360 LOG_DEBUG("pathmove: %i states, end in %s",
361 cmd->cmd.pathmove->num_states,
362 tap_state_name(cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]));
363 #endif
364 if (bitbang_path_move(cmd->cmd.pathmove) != ERROR_OK)
365 return ERROR_FAIL;
366 break;
367 case JTAG_SCAN:
368 bitbang_end_state(cmd->cmd.scan->end_state);
369 scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
370 #ifdef _DEBUG_JTAG_IO_
371 LOG_DEBUG("%s scan %d bits; end in %s",
372 (cmd->cmd.scan->ir_scan) ? "IR" : "DR",
373 scan_size,
374 tap_state_name(cmd->cmd.scan->end_state));
375 #endif
376 type = jtag_scan_type(cmd->cmd.scan);
377 if (bitbang_scan(cmd->cmd.scan->ir_scan, type, buffer,
378 scan_size) != ERROR_OK)
379 return ERROR_FAIL;
380 if (jtag_read_buffer(buffer, cmd->cmd.scan) != ERROR_OK)
381 retval = ERROR_JTAG_QUEUE_FAILED;
382 if (buffer)
383 free(buffer);
384 break;
385 case JTAG_SLEEP:
386 #ifdef _DEBUG_JTAG_IO_
387 LOG_DEBUG("sleep %" PRIi32, cmd->cmd.sleep->us);
388 #endif
389 jtag_sleep(cmd->cmd.sleep->us);
390 break;
391 case JTAG_TMS:
392 retval = bitbang_execute_tms(cmd);
393 break;
394 default:
395 LOG_ERROR("BUG: unknown JTAG command type encountered");
396 exit(-1);
397 }
398 cmd = cmd->next;
399 }
400 if (bitbang_interface->blink) {
401 if (bitbang_interface->blink(0) != ERROR_OK)
402 return ERROR_FAIL;
403 }
404
405 return retval;
406 }
407
408
409 bool swd_mode;
410 static int queued_retval;
411
412 static int bitbang_swd_init(void)
413 {
414 LOG_DEBUG("bitbang_swd_init");
415 swd_mode = true;
416 return ERROR_OK;
417 }
418
419 static void bitbang_exchange(bool rnw, uint8_t buf[], unsigned int offset, unsigned int bit_cnt)
420 {
421 LOG_DEBUG("bitbang_exchange");
422 int tdi;
423
424 for (unsigned int i = offset; i < bit_cnt + offset; i++) {
425 int bytec = i/8;
426 int bcval = 1 << (i % 8);
427 tdi = !rnw && (buf[bytec] & bcval);
428
429 bitbang_interface->write(0, 0, tdi);
430
431 if (rnw && buf) {
432 if (bitbang_interface->swdio_read())
433 buf[bytec] |= bcval;
434 else
435 buf[bytec] &= ~bcval;
436 }
437
438 bitbang_interface->write(1, 0, tdi);
439 }
440 }
441
442 int bitbang_swd_switch_seq(enum swd_special_seq seq)
443 {
444 LOG_DEBUG("bitbang_swd_switch_seq");
445
446 switch (seq) {
447 case LINE_RESET:
448 LOG_DEBUG("SWD line reset");
449 bitbang_exchange(false, (uint8_t *)swd_seq_line_reset, 0, swd_seq_line_reset_len);
450 break;
451 case JTAG_TO_SWD:
452 LOG_DEBUG("JTAG-to-SWD");
453 bitbang_exchange(false, (uint8_t *)swd_seq_jtag_to_swd, 0, swd_seq_jtag_to_swd_len);
454 break;
455 case SWD_TO_JTAG:
456 LOG_DEBUG("SWD-to-JTAG");
457 bitbang_exchange(false, (uint8_t *)swd_seq_swd_to_jtag, 0, swd_seq_swd_to_jtag_len);
458 break;
459 default:
460 LOG_ERROR("Sequence %d not supported", seq);
461 return ERROR_FAIL;
462 }
463
464 return ERROR_OK;
465 }
466
467 void bitbang_switch_to_swd(void)
468 {
469 LOG_DEBUG("bitbang_switch_to_swd");
470 bitbang_exchange(false, (uint8_t *)swd_seq_jtag_to_swd, 0, swd_seq_jtag_to_swd_len);
471 }
472
473 static void swd_clear_sticky_errors(void)
474 {
475 bitbang_swd_write_reg(swd_cmd(false, false, DP_ABORT),
476 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
477 }
478
479 static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk)
480 {
481 LOG_DEBUG("bitbang_swd_read_reg");
482 assert(cmd & SWD_CMD_RnW);
483
484 if (queued_retval != ERROR_OK) {
485 LOG_DEBUG("Skip bitbang_swd_read_reg because queued_retval=%d", queued_retval);
486 return;
487 }
488
489 for (;;) {
490 uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
491
492 cmd |= SWD_CMD_START | (1 << 7);
493 bitbang_exchange(false, &cmd, 0, 8);
494
495 bitbang_interface->swdio_drive(false);
496 bitbang_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3 + 32 + 1 + 1);
497 bitbang_interface->swdio_drive(true);
498
499 int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
500 uint32_t data = buf_get_u32(trn_ack_data_parity_trn, 1 + 3, 32);
501 int parity = buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 32, 1);
502
503 LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
504 ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
505 cmd & SWD_CMD_APnDP ? "AP" : "DP",
506 cmd & SWD_CMD_RnW ? "read" : "write",
507 (cmd & SWD_CMD_A32) >> 1,
508 data);
509
510 switch (ack) {
511 case SWD_ACK_OK:
512 if (parity != parity_u32(data)) {
513 LOG_DEBUG("Wrong parity detected");
514 queued_retval = ERROR_FAIL;
515 return;
516 }
517 if (value)
518 *value = data;
519 if (cmd & SWD_CMD_APnDP)
520 bitbang_exchange(true, NULL, 0, ap_delay_clk);
521 return;
522 case SWD_ACK_WAIT:
523 LOG_DEBUG("SWD_ACK_WAIT");
524 swd_clear_sticky_errors();
525 break;
526 case SWD_ACK_FAULT:
527 LOG_DEBUG("SWD_ACK_FAULT");
528 queued_retval = ack;
529 return;
530 default:
531 LOG_DEBUG("No valid acknowledge: ack=%d", ack);
532 queued_retval = ack;
533 return;
534 }
535 }
536 }
537
538 static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk)
539 {
540 LOG_DEBUG("bitbang_swd_write_reg");
541 assert(!(cmd & SWD_CMD_RnW));
542
543 if (queued_retval != ERROR_OK) {
544 LOG_DEBUG("Skip bitbang_swd_write_reg because queued_retval=%d", queued_retval);
545 return;
546 }
547
548 for (;;) {
549 uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
550 buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32, value);
551 buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1 + 32, 1, parity_u32(value));
552
553 cmd |= SWD_CMD_START | (1 << 7);
554 bitbang_exchange(false, &cmd, 0, 8);
555
556 bitbang_interface->swdio_drive(false);
557 bitbang_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3 + 1);
558 bitbang_interface->swdio_drive(true);
559 bitbang_exchange(false, trn_ack_data_parity_trn, 1 + 3 + 1, 32 + 1);
560
561 int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
562 LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
563 ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
564 cmd & SWD_CMD_APnDP ? "AP" : "DP",
565 cmd & SWD_CMD_RnW ? "read" : "write",
566 (cmd & SWD_CMD_A32) >> 1,
567 buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32));
568
569 switch (ack) {
570 case SWD_ACK_OK:
571 if (cmd & SWD_CMD_APnDP)
572 bitbang_exchange(true, NULL, 0, ap_delay_clk);
573 return;
574 case SWD_ACK_WAIT:
575 LOG_DEBUG("SWD_ACK_WAIT");
576 swd_clear_sticky_errors();
577 break;
578 case SWD_ACK_FAULT:
579 LOG_DEBUG("SWD_ACK_FAULT");
580 queued_retval = ack;
581 return;
582 default:
583 LOG_DEBUG("No valid acknowledge: ack=%d", ack);
584 queued_retval = ack;
585 return;
586 }
587 }
588 }
589
590 static int bitbang_swd_run_queue(void)
591 {
592 LOG_DEBUG("bitbang_swd_run_queue");
593 /* A transaction must be followed by another transaction or at least 8 idle cycles to
594 * ensure that data is clocked through the AP. */
595 bitbang_exchange(true, NULL, 0, 8);
596
597 int retval = queued_retval;
598 queued_retval = ERROR_OK;
599 LOG_DEBUG("SWD queue return value: %02x", retval);
600 return retval;
601 }
602
603 const struct swd_driver bitbang_swd = {
604 .init = bitbang_swd_init,
605 .switch_seq = bitbang_swd_switch_seq,
606 .read_reg = bitbang_swd_read_reg,
607 .write_reg = bitbang_swd_write_reg,
608 .run = bitbang_swd_run_queue,
609 };