1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
24 /* 2014-12: Addition of the SWD protocol support is based on the initial work
25 * by Paul Fertser and modifications by Jean-Christian de Rivaz. */
32 #include <jtag/interface.h>
33 #include <jtag/commands.h>
35 /* YUK! - but this is currently a global.... */
36 extern struct jtag_interface
*jtag_interface
;
39 * Function bitbang_stableclocks
40 * issues a number of clock cycles while staying in a stable state.
41 * Because the TMS value required to stay in the RESET state is a 1, whereas
42 * the TMS value required to stay in any of the other stable states is a 0,
43 * this function checks the current stable state to decide on the value of TMS
46 static void bitbang_stableclocks(int num_cycles
);
48 static void bitbang_swd_write_reg(uint8_t cmd
, uint32_t value
, uint32_t ap_delay_clk
);
50 struct bitbang_interface
*bitbang_interface
;
52 /* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
54 * Set this to 1 and str912 reset halt will fail.
56 * If someone can submit a patch with an explanation it will be greatly
57 * appreciated, but as far as I can tell (ØH) DCLK is generated upon
58 * clk = 0 in TAP_IDLE. Good luck deducing that from the ARM documentation!
59 * The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE
60 * state". With hardware there is no such thing as *while* in a state. There
61 * are only edges. So clk => 0 is in fact a very subtle state transition that
62 * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#&
64 * For "reset halt" the last thing that happens before srst is asserted
65 * is that the breakpoint is set up. If DCLK is not wiggled one last
66 * time before the reset, then the breakpoint is not set up and
67 * "reset halt" will fail to halt.
70 #define CLOCK_IDLE() 0
72 /* The bitbang driver leaves the TCK 0 when in idle */
73 static void bitbang_end_state(tap_state_t state
)
75 if (tap_is_state_stable(state
))
76 tap_set_end_state(state
);
78 LOG_ERROR("BUG: %i is not a valid end state", state
);
83 static void bitbang_state_move(int skip
)
86 uint8_t tms_scan
= tap_get_tms_path(tap_get_state(), tap_get_end_state());
87 int tms_count
= tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
89 for (i
= skip
; i
< tms_count
; i
++) {
90 tms
= (tms_scan
>> i
) & 1;
91 bitbang_interface
->write(0, tms
, 0);
92 bitbang_interface
->write(1, tms
, 0);
94 bitbang_interface
->write(CLOCK_IDLE(), tms
, 0);
96 tap_set_state(tap_get_end_state());
100 * Clock a bunch of TMS (or SWDIO) transitions, to change the JTAG
101 * (or SWD) state machine.
103 static int bitbang_execute_tms(struct jtag_command
*cmd
)
105 unsigned num_bits
= cmd
->cmd
.tms
->num_bits
;
106 const uint8_t *bits
= cmd
->cmd
.tms
->bits
;
108 DEBUG_JTAG_IO("TMS: %d bits", num_bits
);
111 for (unsigned i
= 0; i
< num_bits
; i
++) {
112 tms
= ((bits
[i
/8] >> (i
% 8)) & 1);
113 bitbang_interface
->write(0, tms
, 0);
114 bitbang_interface
->write(1, tms
, 0);
116 bitbang_interface
->write(CLOCK_IDLE(), tms
, 0);
121 static void bitbang_path_move(struct pathmove_command
*cmd
)
123 int num_states
= cmd
->num_states
;
129 if (tap_state_transition(tap_get_state(), false) == cmd
->path
[state_count
])
131 else if (tap_state_transition(tap_get_state(), true) == cmd
->path
[state_count
])
134 LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition",
135 tap_state_name(tap_get_state()),
136 tap_state_name(cmd
->path
[state_count
]));
140 bitbang_interface
->write(0, tms
, 0);
141 bitbang_interface
->write(1, tms
, 0);
143 tap_set_state(cmd
->path
[state_count
]);
148 bitbang_interface
->write(CLOCK_IDLE(), tms
, 0);
150 tap_set_end_state(tap_get_state());
153 static void bitbang_runtest(int num_cycles
)
157 tap_state_t saved_end_state
= tap_get_end_state();
159 /* only do a state_move when we're not already in IDLE */
160 if (tap_get_state() != TAP_IDLE
) {
161 bitbang_end_state(TAP_IDLE
);
162 bitbang_state_move(0);
165 /* execute num_cycles */
166 for (i
= 0; i
< num_cycles
; i
++) {
167 bitbang_interface
->write(0, 0, 0);
168 bitbang_interface
->write(1, 0, 0);
170 bitbang_interface
->write(CLOCK_IDLE(), 0, 0);
172 /* finish in end_state */
173 bitbang_end_state(saved_end_state
);
174 if (tap_get_state() != tap_get_end_state())
175 bitbang_state_move(0);
178 static void bitbang_stableclocks(int num_cycles
)
180 int tms
= (tap_get_state() == TAP_RESET
? 1 : 0);
183 /* send num_cycles clocks onto the cable */
184 for (i
= 0; i
< num_cycles
; i
++) {
185 bitbang_interface
->write(1, tms
, 0);
186 bitbang_interface
->write(0, tms
, 0);
190 static void bitbang_scan(bool ir_scan
, enum scan_type type
, uint8_t *buffer
, int scan_size
)
192 tap_state_t saved_end_state
= tap_get_end_state();
196 (tap_get_state() == TAP_DRSHIFT
)) ||
197 (ir_scan
&& (tap_get_state() == TAP_IRSHIFT
)))) {
199 bitbang_end_state(TAP_IRSHIFT
);
201 bitbang_end_state(TAP_DRSHIFT
);
203 bitbang_state_move(0);
204 bitbang_end_state(saved_end_state
);
207 for (bit_cnt
= 0; bit_cnt
< scan_size
; bit_cnt
++) {
209 int tms
= (bit_cnt
== scan_size
-1) ? 1 : 0;
211 int bytec
= bit_cnt
/8;
212 int bcval
= 1 << (bit_cnt
% 8);
214 /* if we're just reading the scan, but don't care about the output
215 * default to outputting 'low', this also makes valgrind traces more readable,
216 * as it removes the dependency on an uninitialised value
219 if ((type
!= SCAN_IN
) && (buffer
[bytec
] & bcval
))
222 bitbang_interface
->write(0, tms
, tdi
);
224 if (type
!= SCAN_OUT
)
225 val
= bitbang_interface
->read();
227 bitbang_interface
->write(1, tms
, tdi
);
229 if (type
!= SCAN_OUT
) {
231 buffer
[bytec
] |= bcval
;
233 buffer
[bytec
] &= ~bcval
;
237 if (tap_get_state() != tap_get_end_state()) {
238 /* we *KNOW* the above loop transitioned out of
239 * the shift state, so we skip the first state
240 * and move directly to the end state.
242 bitbang_state_move(1);
246 int bitbang_execute_queue(void)
248 struct jtag_command
*cmd
= jtag_command_queue
; /* currently processed command */
254 if (!bitbang_interface
) {
255 LOG_ERROR("BUG: Bitbang interface called, but not yet initialized");
259 /* return ERROR_OK, unless a jtag_read_buffer returns a failed check
260 * that wasn't handled by a caller-provided error handler
264 if (bitbang_interface
->blink
)
265 bitbang_interface
->blink(1);
270 #ifdef _DEBUG_JTAG_IO_
271 LOG_DEBUG("reset trst: %i srst %i",
272 cmd
->cmd
.reset
->trst
,
273 cmd
->cmd
.reset
->srst
);
275 if ((cmd
->cmd
.reset
->trst
== 1) ||
276 (cmd
->cmd
.reset
->srst
&& (jtag_get_reset_config() & RESET_SRST_PULLS_TRST
)))
277 tap_set_state(TAP_RESET
);
278 bitbang_interface
->reset(cmd
->cmd
.reset
->trst
, cmd
->cmd
.reset
->srst
);
281 #ifdef _DEBUG_JTAG_IO_
282 LOG_DEBUG("runtest %i cycles, end in %s",
283 cmd
->cmd
.runtest
->num_cycles
,
284 tap_state_name(cmd
->cmd
.runtest
->end_state
));
286 bitbang_end_state(cmd
->cmd
.runtest
->end_state
);
287 bitbang_runtest(cmd
->cmd
.runtest
->num_cycles
);
290 case JTAG_STABLECLOCKS
:
291 /* this is only allowed while in a stable state. A check for a stable
292 * state was done in jtag_add_clocks()
294 bitbang_stableclocks(cmd
->cmd
.stableclocks
->num_cycles
);
298 #ifdef _DEBUG_JTAG_IO_
299 LOG_DEBUG("statemove end in %s",
300 tap_state_name(cmd
->cmd
.statemove
->end_state
));
302 bitbang_end_state(cmd
->cmd
.statemove
->end_state
);
303 bitbang_state_move(0);
306 #ifdef _DEBUG_JTAG_IO_
307 LOG_DEBUG("pathmove: %i states, end in %s",
308 cmd
->cmd
.pathmove
->num_states
,
309 tap_state_name(cmd
->cmd
.pathmove
->path
[cmd
->cmd
.pathmove
->num_states
- 1]));
311 bitbang_path_move(cmd
->cmd
.pathmove
);
314 #ifdef _DEBUG_JTAG_IO_
315 LOG_DEBUG("%s scan end in %s",
316 (cmd
->cmd
.scan
->ir_scan
) ? "IR" : "DR",
317 tap_state_name(cmd
->cmd
.scan
->end_state
));
319 bitbang_end_state(cmd
->cmd
.scan
->end_state
);
320 scan_size
= jtag_build_buffer(cmd
->cmd
.scan
, &buffer
);
321 type
= jtag_scan_type(cmd
->cmd
.scan
);
322 bitbang_scan(cmd
->cmd
.scan
->ir_scan
, type
, buffer
, scan_size
);
323 if (jtag_read_buffer(buffer
, cmd
->cmd
.scan
) != ERROR_OK
)
324 retval
= ERROR_JTAG_QUEUE_FAILED
;
329 #ifdef _DEBUG_JTAG_IO_
330 LOG_DEBUG("sleep %" PRIi32
, cmd
->cmd
.sleep
->us
);
332 jtag_sleep(cmd
->cmd
.sleep
->us
);
335 retval
= bitbang_execute_tms(cmd
);
338 LOG_ERROR("BUG: unknown JTAG command type encountered");
343 if (bitbang_interface
->blink
)
344 bitbang_interface
->blink(0);
351 static int queued_retval
;
353 static int bitbang_swd_init(void)
355 LOG_DEBUG("bitbang_swd_init");
360 static void bitbang_exchange(bool rnw
, uint8_t buf
[], unsigned int offset
, unsigned int bit_cnt
)
362 LOG_DEBUG("bitbang_exchange");
365 for (unsigned int i
= offset
; i
< bit_cnt
+ offset
; i
++) {
367 int bcval
= 1 << (i
% 8);
368 tdi
= !rnw
&& (buf
[bytec
] & bcval
);
370 bitbang_interface
->write(0, 0, tdi
);
373 if (bitbang_interface
->swdio_read())
376 buf
[bytec
] &= ~bcval
;
379 bitbang_interface
->write(1, 0, tdi
);
383 int bitbang_swd_switch_seq(enum swd_special_seq seq
)
385 LOG_DEBUG("bitbang_swd_switch_seq");
389 LOG_DEBUG("SWD line reset");
390 bitbang_exchange(false, (uint8_t *)swd_seq_line_reset
, 0, swd_seq_line_reset_len
);
393 LOG_DEBUG("JTAG-to-SWD");
394 bitbang_exchange(false, (uint8_t *)swd_seq_jtag_to_swd
, 0, swd_seq_jtag_to_swd_len
);
397 LOG_DEBUG("SWD-to-JTAG");
398 bitbang_exchange(false, (uint8_t *)swd_seq_swd_to_jtag
, 0, swd_seq_swd_to_jtag_len
);
401 LOG_ERROR("Sequence %d not supported", seq
);
408 void bitbang_switch_to_swd(void)
410 LOG_DEBUG("bitbang_switch_to_swd");
411 bitbang_exchange(false, (uint8_t *)swd_seq_jtag_to_swd
, 0, swd_seq_jtag_to_swd_len
);
414 static void swd_clear_sticky_errors(void)
416 bitbang_swd_write_reg(swd_cmd(false, false, DP_ABORT
),
417 STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
, 0);
420 static void bitbang_swd_read_reg(uint8_t cmd
, uint32_t *value
, uint32_t ap_delay_clk
)
422 LOG_DEBUG("bitbang_swd_read_reg");
423 assert(cmd
& SWD_CMD_RnW
);
425 if (queued_retval
!= ERROR_OK
) {
426 LOG_DEBUG("Skip bitbang_swd_read_reg because queued_retval=%d", queued_retval
);
431 uint8_t trn_ack_data_parity_trn
[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
433 cmd
|= SWD_CMD_START
| (1 << 7);
434 bitbang_exchange(false, &cmd
, 0, 8);
436 bitbang_interface
->swdio_drive(false);
437 bitbang_exchange(true, trn_ack_data_parity_trn
, 0, 1 + 3 + 32 + 1 + 1);
438 bitbang_interface
->swdio_drive(true);
440 int ack
= buf_get_u32(trn_ack_data_parity_trn
, 1, 3);
441 uint32_t data
= buf_get_u32(trn_ack_data_parity_trn
, 1 + 3, 32);
442 int parity
= buf_get_u32(trn_ack_data_parity_trn
, 1 + 3 + 32, 1);
444 LOG_DEBUG("%s %s %s reg %X = %08"PRIx32
,
445 ack
== SWD_ACK_OK
? "OK" : ack
== SWD_ACK_WAIT
? "WAIT" : ack
== SWD_ACK_FAULT
? "FAULT" : "JUNK",
446 cmd
& SWD_CMD_APnDP
? "AP" : "DP",
447 cmd
& SWD_CMD_RnW
? "read" : "write",
448 (cmd
& SWD_CMD_A32
) >> 1,
453 if (parity
!= parity_u32(data
)) {
454 LOG_DEBUG("Wrong parity detected");
455 queued_retval
= ERROR_FAIL
;
460 if (cmd
& SWD_CMD_APnDP
)
461 bitbang_exchange(true, NULL
, 0, ap_delay_clk
);
464 LOG_DEBUG("SWD_ACK_WAIT");
465 swd_clear_sticky_errors();
468 LOG_DEBUG("SWD_ACK_FAULT");
472 LOG_DEBUG("No valid acknowledge: ack=%d", ack
);
479 static void bitbang_swd_write_reg(uint8_t cmd
, uint32_t value
, uint32_t ap_delay_clk
)
481 LOG_DEBUG("bitbang_swd_write_reg");
482 assert(!(cmd
& SWD_CMD_RnW
));
484 if (queued_retval
!= ERROR_OK
) {
485 LOG_DEBUG("Skip bitbang_swd_write_reg because queued_retval=%d", queued_retval
);
490 uint8_t trn_ack_data_parity_trn
[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
491 buf_set_u32(trn_ack_data_parity_trn
, 1 + 3 + 1, 32, value
);
492 buf_set_u32(trn_ack_data_parity_trn
, 1 + 3 + 1 + 32, 1, parity_u32(value
));
494 cmd
|= SWD_CMD_START
| (1 << 7);
495 bitbang_exchange(false, &cmd
, 0, 8);
497 bitbang_interface
->swdio_drive(false);
498 bitbang_exchange(true, trn_ack_data_parity_trn
, 0, 1 + 3 + 1);
499 bitbang_interface
->swdio_drive(true);
500 bitbang_exchange(false, trn_ack_data_parity_trn
, 1 + 3 + 1, 32 + 1);
502 int ack
= buf_get_u32(trn_ack_data_parity_trn
, 1, 3);
503 LOG_DEBUG("%s %s %s reg %X = %08"PRIx32
,
504 ack
== SWD_ACK_OK
? "OK" : ack
== SWD_ACK_WAIT
? "WAIT" : ack
== SWD_ACK_FAULT
? "FAULT" : "JUNK",
505 cmd
& SWD_CMD_APnDP
? "AP" : "DP",
506 cmd
& SWD_CMD_RnW
? "read" : "write",
507 (cmd
& SWD_CMD_A32
) >> 1,
508 buf_get_u32(trn_ack_data_parity_trn
, 1 + 3 + 1, 32));
512 if (cmd
& SWD_CMD_APnDP
)
513 bitbang_exchange(true, NULL
, 0, ap_delay_clk
);
516 LOG_DEBUG("SWD_ACK_WAIT");
517 swd_clear_sticky_errors();
520 LOG_DEBUG("SWD_ACK_FAULT");
524 LOG_DEBUG("No valid acknowledge: ack=%d", ack
);
531 static int bitbang_swd_run_queue(void)
533 LOG_DEBUG("bitbang_swd_run_queue");
534 /* A transaction must be followed by another transaction or at least 8 idle cycles to
535 * ensure that data is clocked through the AP. */
536 bitbang_exchange(true, NULL
, 0, 8);
538 int retval
= queued_retval
;
539 queued_retval
= ERROR_OK
;
540 LOG_DEBUG("SWD queue return value: %02x", retval
);
544 const struct swd_driver bitbang_swd
= {
545 .init
= bitbang_swd_init
,
546 .switch_seq
= bitbang_swd_switch_seq
,
547 .read_reg
= bitbang_swd_read_reg
,
548 .write_reg
= bitbang_swd_write_reg
,
549 .run
= bitbang_swd_run_queue
,
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