1 /***************************************************************************
2 * Copyright (C) 2013 by Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
24 #include <jtag/drivers/libusb_common.h>
25 #include <helper/log.h>
26 #include <helper/time_support.h>
27 #include <target/target.h>
28 #include <jtag/jtag.h>
29 #include <target/nds32_insn.h>
30 #include <target/nds32_reg.h>
34 /* Global USB buffers */
35 static uint8_t usb_in_buffer
[AICE_IN_BUFFER_SIZE
];
36 static uint8_t usb_out_buffer
[AICE_OUT_BUFFER_SIZE
];
37 static uint8_t current_target_id
;
38 static uint32_t jtag_clock
;
39 static struct aice_usb_handler_s aice_handler
;
40 /* AICE max retry times. If AICE command timeout, retry it. */
41 static int aice_max_retry_times
= 10;
42 /* Default endian is little endian. */
43 static enum aice_target_endian data_endian
;
46 /***************************************************************************/
47 /* AICE commands' pack/unpack functions */
48 static void aice_pack_htda(uint8_t cmd_code
, uint8_t extra_word_length
,
51 usb_out_buffer
[0] = cmd_code
;
52 usb_out_buffer
[1] = extra_word_length
;
53 usb_out_buffer
[2] = (uint8_t)(address
& 0xFF);
56 static void aice_pack_htdc(uint8_t cmd_code
, uint8_t extra_word_length
,
57 uint32_t address
, uint32_t word
, enum aice_target_endian access_endian
)
59 usb_out_buffer
[0] = cmd_code
;
60 usb_out_buffer
[1] = extra_word_length
;
61 usb_out_buffer
[2] = (uint8_t)(address
& 0xFF);
62 if (access_endian
== AICE_BIG_ENDIAN
) {
63 usb_out_buffer
[6] = (uint8_t)((word
>> 24) & 0xFF);
64 usb_out_buffer
[5] = (uint8_t)((word
>> 16) & 0xFF);
65 usb_out_buffer
[4] = (uint8_t)((word
>> 8) & 0xFF);
66 usb_out_buffer
[3] = (uint8_t)(word
& 0xFF);
68 usb_out_buffer
[3] = (uint8_t)((word
>> 24) & 0xFF);
69 usb_out_buffer
[4] = (uint8_t)((word
>> 16) & 0xFF);
70 usb_out_buffer
[5] = (uint8_t)((word
>> 8) & 0xFF);
71 usb_out_buffer
[6] = (uint8_t)(word
& 0xFF);
75 static void aice_pack_htdma(uint8_t cmd_code
, uint8_t target_id
,
76 uint8_t extra_word_length
, uint32_t address
)
78 usb_out_buffer
[0] = cmd_code
;
79 usb_out_buffer
[1] = target_id
;
80 usb_out_buffer
[2] = extra_word_length
;
81 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
84 static void aice_pack_htdmb(uint8_t cmd_code
, uint8_t target_id
,
85 uint8_t extra_word_length
, uint32_t address
)
87 usb_out_buffer
[0] = cmd_code
;
88 usb_out_buffer
[1] = target_id
;
89 usb_out_buffer
[2] = extra_word_length
;
90 usb_out_buffer
[3] = 0;
91 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
92 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
93 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
94 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
97 static void aice_pack_htdmc(uint8_t cmd_code
, uint8_t target_id
,
98 uint8_t extra_word_length
, uint32_t address
, uint32_t word
,
99 enum aice_target_endian access_endian
)
101 usb_out_buffer
[0] = cmd_code
;
102 usb_out_buffer
[1] = target_id
;
103 usb_out_buffer
[2] = extra_word_length
;
104 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
105 if (access_endian
== AICE_BIG_ENDIAN
) {
106 usb_out_buffer
[7] = (uint8_t)((word
>> 24) & 0xFF);
107 usb_out_buffer
[6] = (uint8_t)((word
>> 16) & 0xFF);
108 usb_out_buffer
[5] = (uint8_t)((word
>> 8) & 0xFF);
109 usb_out_buffer
[4] = (uint8_t)(word
& 0xFF);
111 usb_out_buffer
[4] = (uint8_t)((word
>> 24) & 0xFF);
112 usb_out_buffer
[5] = (uint8_t)((word
>> 16) & 0xFF);
113 usb_out_buffer
[6] = (uint8_t)((word
>> 8) & 0xFF);
114 usb_out_buffer
[7] = (uint8_t)(word
& 0xFF);
118 static void aice_pack_htdmc_multiple_data(uint8_t cmd_code
, uint8_t target_id
,
119 uint8_t extra_word_length
, uint32_t address
, uint32_t *word
,
120 uint8_t num_of_words
, enum aice_target_endian access_endian
)
122 usb_out_buffer
[0] = cmd_code
;
123 usb_out_buffer
[1] = target_id
;
124 usb_out_buffer
[2] = extra_word_length
;
125 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
128 for (i
= 0 ; i
< num_of_words
; i
++, word
++) {
129 if (access_endian
== AICE_BIG_ENDIAN
) {
130 usb_out_buffer
[7 + i
* 4] = (uint8_t)((*word
>> 24) & 0xFF);
131 usb_out_buffer
[6 + i
* 4] = (uint8_t)((*word
>> 16) & 0xFF);
132 usb_out_buffer
[5 + i
* 4] = (uint8_t)((*word
>> 8) & 0xFF);
133 usb_out_buffer
[4 + i
* 4] = (uint8_t)(*word
& 0xFF);
135 usb_out_buffer
[4 + i
* 4] = (uint8_t)((*word
>> 24) & 0xFF);
136 usb_out_buffer
[5 + i
* 4] = (uint8_t)((*word
>> 16) & 0xFF);
137 usb_out_buffer
[6 + i
* 4] = (uint8_t)((*word
>> 8) & 0xFF);
138 usb_out_buffer
[7 + i
* 4] = (uint8_t)(*word
& 0xFF);
143 static void aice_pack_htdmd(uint8_t cmd_code
, uint8_t target_id
,
144 uint8_t extra_word_length
, uint32_t address
, uint32_t word
,
145 enum aice_target_endian access_endian
)
147 usb_out_buffer
[0] = cmd_code
;
148 usb_out_buffer
[1] = target_id
;
149 usb_out_buffer
[2] = extra_word_length
;
150 usb_out_buffer
[3] = 0;
151 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
152 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
153 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
154 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
155 if (access_endian
== AICE_BIG_ENDIAN
) {
156 usb_out_buffer
[11] = (uint8_t)((word
>> 24) & 0xFF);
157 usb_out_buffer
[10] = (uint8_t)((word
>> 16) & 0xFF);
158 usb_out_buffer
[9] = (uint8_t)((word
>> 8) & 0xFF);
159 usb_out_buffer
[8] = (uint8_t)(word
& 0xFF);
161 usb_out_buffer
[8] = (uint8_t)((word
>> 24) & 0xFF);
162 usb_out_buffer
[9] = (uint8_t)((word
>> 16) & 0xFF);
163 usb_out_buffer
[10] = (uint8_t)((word
>> 8) & 0xFF);
164 usb_out_buffer
[11] = (uint8_t)(word
& 0xFF);
168 static void aice_pack_htdmd_multiple_data(uint8_t cmd_code
, uint8_t target_id
,
169 uint8_t extra_word_length
, uint32_t address
, const uint8_t *word
,
170 enum aice_target_endian access_endian
)
172 usb_out_buffer
[0] = cmd_code
;
173 usb_out_buffer
[1] = target_id
;
174 usb_out_buffer
[2] = extra_word_length
;
175 usb_out_buffer
[3] = 0;
176 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
177 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
178 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
179 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
182 /* num_of_words may be over 0xFF, so use uint32_t */
183 uint32_t num_of_words
= extra_word_length
+ 1;
185 for (i
= 0 ; i
< num_of_words
; i
++, word
+= 4) {
186 if (access_endian
== AICE_BIG_ENDIAN
) {
187 usb_out_buffer
[11 + i
* 4] = word
[3];
188 usb_out_buffer
[10 + i
* 4] = word
[2];
189 usb_out_buffer
[9 + i
* 4] = word
[1];
190 usb_out_buffer
[8 + i
* 4] = word
[0];
192 usb_out_buffer
[8 + i
* 4] = word
[3];
193 usb_out_buffer
[9 + i
* 4] = word
[2];
194 usb_out_buffer
[10 + i
* 4] = word
[1];
195 usb_out_buffer
[11 + i
* 4] = word
[0];
200 static void aice_unpack_dtha(uint8_t *cmd_ack_code
, uint8_t *extra_word_length
,
201 uint32_t *word
, enum aice_target_endian access_endian
)
203 *cmd_ack_code
= usb_in_buffer
[0];
204 *extra_word_length
= usb_in_buffer
[1];
206 if (access_endian
== AICE_BIG_ENDIAN
) {
207 *word
= (usb_in_buffer
[5] << 24) |
208 (usb_in_buffer
[4] << 16) |
209 (usb_in_buffer
[3] << 8) |
212 *word
= (usb_in_buffer
[2] << 24) |
213 (usb_in_buffer
[3] << 16) |
214 (usb_in_buffer
[4] << 8) |
219 static void aice_unpack_dtha_multiple_data(uint8_t *cmd_ack_code
,
220 uint8_t *extra_word_length
, uint32_t *word
, uint8_t num_of_words
,
221 enum aice_target_endian access_endian
)
223 *cmd_ack_code
= usb_in_buffer
[0];
224 *extra_word_length
= usb_in_buffer
[1];
227 for (i
= 0 ; i
< num_of_words
; i
++, word
++) {
228 if (access_endian
== AICE_BIG_ENDIAN
) {
229 *word
= (usb_in_buffer
[5 + i
* 4] << 24) |
230 (usb_in_buffer
[4 + i
* 4] << 16) |
231 (usb_in_buffer
[3 + i
* 4] << 8) |
232 (usb_in_buffer
[2 + i
* 4]);
234 *word
= (usb_in_buffer
[2 + i
* 4] << 24) |
235 (usb_in_buffer
[3 + i
* 4] << 16) |
236 (usb_in_buffer
[4 + i
* 4] << 8) |
237 (usb_in_buffer
[5 + i
* 4]);
242 static void aice_unpack_dthb(uint8_t *cmd_ack_code
, uint8_t *extra_word_length
)
244 *cmd_ack_code
= usb_in_buffer
[0];
245 *extra_word_length
= usb_in_buffer
[1];
248 static void aice_unpack_dthma(uint8_t *cmd_ack_code
, uint8_t *target_id
,
249 uint8_t *extra_word_length
, uint32_t *word
,
250 enum aice_target_endian access_endian
)
252 *cmd_ack_code
= usb_in_buffer
[0];
253 *target_id
= usb_in_buffer
[1];
254 *extra_word_length
= usb_in_buffer
[2];
255 if (access_endian
== AICE_BIG_ENDIAN
) {
256 *word
= (usb_in_buffer
[7] << 24) |
257 (usb_in_buffer
[6] << 16) |
258 (usb_in_buffer
[5] << 8) |
261 *word
= (usb_in_buffer
[4] << 24) |
262 (usb_in_buffer
[5] << 16) |
263 (usb_in_buffer
[6] << 8) |
268 static void aice_unpack_dthma_multiple_data(uint8_t *cmd_ack_code
,
269 uint8_t *target_id
, uint8_t *extra_word_length
, uint8_t *word
,
270 enum aice_target_endian access_endian
)
272 *cmd_ack_code
= usb_in_buffer
[0];
273 *target_id
= usb_in_buffer
[1];
274 *extra_word_length
= usb_in_buffer
[2];
275 if (access_endian
== AICE_BIG_ENDIAN
) {
276 word
[0] = usb_in_buffer
[4];
277 word
[1] = usb_in_buffer
[5];
278 word
[2] = usb_in_buffer
[6];
279 word
[3] = usb_in_buffer
[7];
281 word
[0] = usb_in_buffer
[7];
282 word
[1] = usb_in_buffer
[6];
283 word
[2] = usb_in_buffer
[5];
284 word
[3] = usb_in_buffer
[4];
289 for (i
= 0; i
< *extra_word_length
; i
++) {
290 if (access_endian
== AICE_BIG_ENDIAN
) {
291 word
[0] = usb_in_buffer
[8 + i
* 4];
292 word
[1] = usb_in_buffer
[9 + i
* 4];
293 word
[2] = usb_in_buffer
[10 + i
* 4];
294 word
[3] = usb_in_buffer
[11 + i
* 4];
296 word
[0] = usb_in_buffer
[11 + i
* 4];
297 word
[1] = usb_in_buffer
[10 + i
* 4];
298 word
[2] = usb_in_buffer
[9 + i
* 4];
299 word
[3] = usb_in_buffer
[8 + i
* 4];
305 static void aice_unpack_dthmb(uint8_t *cmd_ack_code
, uint8_t *target_id
,
306 uint8_t *extra_word_length
)
308 *cmd_ack_code
= usb_in_buffer
[0];
309 *target_id
= usb_in_buffer
[1];
310 *extra_word_length
= usb_in_buffer
[2];
313 /***************************************************************************/
314 /* End of AICE commands' pack/unpack functions */
316 /* calls the given usb_bulk_* function, allowing for the data to
317 * trickle in with some timeouts */
318 static int usb_bulk_with_retries(
319 int (*f
)(jtag_libusb_device_handle
*, int, char *, int, int),
320 jtag_libusb_device_handle
*dev
, int ep
,
321 char *bytes
, int size
, int timeout
)
323 int tries
= 3, count
= 0;
325 while (tries
&& (count
< size
)) {
326 int result
= f(dev
, ep
, bytes
+ count
, size
- count
, timeout
);
329 else if ((-ETIMEDOUT
!= result
) || !--tries
)
335 static int wrap_usb_bulk_write(jtag_libusb_device_handle
*dev
, int ep
,
336 char *buff
, int size
, int timeout
)
338 /* usb_bulk_write() takes const char *buff */
339 return jtag_libusb_bulk_write(dev
, ep
, buff
, size
, timeout
);
342 static inline int usb_bulk_write_ex(jtag_libusb_device_handle
*dev
, int ep
,
343 char *bytes
, int size
, int timeout
)
345 return usb_bulk_with_retries(&wrap_usb_bulk_write
,
346 dev
, ep
, bytes
, size
, timeout
);
349 static inline int usb_bulk_read_ex(jtag_libusb_device_handle
*dev
, int ep
,
350 char *bytes
, int size
, int timeout
)
352 return usb_bulk_with_retries(&jtag_libusb_bulk_read
,
353 dev
, ep
, bytes
, size
, timeout
);
356 /* Write data from out_buffer to USB. */
357 static int aice_usb_write(uint8_t *out_buffer
, int out_length
)
361 if (out_length
> AICE_OUT_BUFFER_SIZE
) {
362 LOG_ERROR("aice_write illegal out_length=%d (max=%d)",
363 out_length
, AICE_OUT_BUFFER_SIZE
);
367 result
= usb_bulk_write_ex(aice_handler
.usb_handle
, aice_handler
.usb_write_ep
,
368 (char *)out_buffer
, out_length
, AICE_USB_TIMEOUT
);
370 DEBUG_JTAG_IO("aice_usb_write, out_length = %d, result = %d",
376 /* Read data from USB into in_buffer. */
377 static int aice_usb_read(uint8_t *in_buffer
, int expected_size
)
379 int result
= usb_bulk_read_ex(aice_handler
.usb_handle
, aice_handler
.usb_read_ep
,
380 (char *)in_buffer
, expected_size
, AICE_USB_TIMEOUT
);
382 DEBUG_JTAG_IO("aice_usb_read, result = %d", result
);
387 static uint8_t usb_out_packets_buffer
[AICE_OUT_PACKETS_BUFFER_SIZE
];
388 static uint8_t usb_in_packets_buffer
[AICE_IN_PACKETS_BUFFER_SIZE
];
389 static uint32_t usb_out_packets_buffer_length
;
390 static uint32_t usb_in_packets_buffer_length
;
391 static bool usb_pack_command
;
393 static int aice_usb_packet_flush(void)
395 if (usb_out_packets_buffer_length
== 0)
398 LOG_DEBUG("Flush usb packets");
402 aice_usb_write(usb_out_packets_buffer
, usb_out_packets_buffer_length
);
403 result
= aice_usb_read(usb_in_packets_buffer
, usb_in_packets_buffer_length
);
405 usb_out_packets_buffer_length
= 0;
406 usb_in_packets_buffer_length
= 0;
411 static void aice_usb_packet_append(uint8_t *out_buffer
, int out_length
,
414 if (usb_out_packets_buffer_length
+ out_length
> AICE_OUT_PACKETS_BUFFER_SIZE
)
415 aice_usb_packet_flush();
417 LOG_DEBUG("Append usb packets 0x%02x", out_buffer
[0]);
419 memcpy(usb_out_packets_buffer
+ usb_out_packets_buffer_length
,
422 usb_out_packets_buffer_length
+= out_length
;
423 usb_in_packets_buffer_length
+= in_length
;
426 /***************************************************************************/
428 static int aice_scan_chain(uint32_t *id_codes
, uint8_t *num_of_ids
)
433 if (usb_pack_command
)
434 aice_usb_packet_flush();
437 aice_pack_htda(AICE_CMD_SCAN_CHAIN
, 0x0F, 0x0);
439 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDA
);
441 LOG_DEBUG("SCAN_CHAIN, length: 0x0F");
443 /** TODO: modify receive length */
444 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHA
);
445 if (AICE_FORMAT_DTHA
!= result
) {
446 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
447 AICE_FORMAT_DTHA
, result
);
451 uint8_t cmd_ack_code
;
452 aice_unpack_dtha_multiple_data(&cmd_ack_code
, num_of_ids
, id_codes
,
453 0x10, AICE_LITTLE_ENDIAN
);
455 LOG_DEBUG("SCAN_CHAIN response, # of IDs: %d", *num_of_ids
);
457 if (cmd_ack_code
!= AICE_CMD_SCAN_CHAIN
) {
458 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
459 AICE_CMD_SCAN_CHAIN
, cmd_ack_code
);
461 if (retry_times
> aice_max_retry_times
)
464 /* clear timeout and retry */
465 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
472 if (*num_of_ids
== 0xFF) {
473 LOG_ERROR("No target connected");
475 } else if (*num_of_ids
== 0x10) {
476 LOG_INFO("The ice chain over 16 targets");
486 int aice_read_ctrl(uint32_t address
, uint32_t *data
)
490 if (usb_pack_command
)
491 aice_usb_packet_flush();
493 aice_pack_htda(AICE_CMD_READ_CTRL
, 0, address
);
495 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDA
);
497 LOG_DEBUG("READ_CTRL, address: 0x%x", address
);
499 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHA
);
500 if (AICE_FORMAT_DTHA
!= result
) {
501 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
502 AICE_FORMAT_DTHA
, result
);
506 uint8_t cmd_ack_code
;
507 uint8_t extra_length
;
508 aice_unpack_dtha(&cmd_ack_code
, &extra_length
, data
, AICE_LITTLE_ENDIAN
);
510 LOG_DEBUG("READ_CTRL response, data: 0x%x", *data
);
512 if (cmd_ack_code
!= AICE_CMD_READ_CTRL
) {
513 LOG_ERROR("aice command error (command=0x%x, response=0x%x)",
514 AICE_CMD_READ_CTRL
, cmd_ack_code
);
521 int aice_write_ctrl(uint32_t address
, uint32_t data
)
525 if (usb_pack_command
)
526 aice_usb_packet_flush();
528 aice_pack_htdc(AICE_CMD_WRITE_CTRL
, 0, address
, data
, AICE_LITTLE_ENDIAN
);
530 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDC
);
532 LOG_DEBUG("WRITE_CTRL, address: 0x%x, data: 0x%x", address
, data
);
534 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHB
);
535 if (AICE_FORMAT_DTHB
!= result
) {
536 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
537 AICE_FORMAT_DTHB
, result
);
541 uint8_t cmd_ack_code
;
542 uint8_t extra_length
;
543 aice_unpack_dthb(&cmd_ack_code
, &extra_length
);
545 LOG_DEBUG("WRITE_CTRL response");
547 if (cmd_ack_code
!= AICE_CMD_WRITE_CTRL
) {
548 LOG_ERROR("aice command error (command=0x%x, response=0x%x)",
549 AICE_CMD_WRITE_CTRL
, cmd_ack_code
);
556 int aice_read_dtr(uint8_t target_id
, uint32_t *data
)
561 if (usb_pack_command
)
562 aice_usb_packet_flush();
565 aice_pack_htdma(AICE_CMD_T_READ_DTR
, target_id
, 0, 0);
567 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
569 LOG_DEBUG("READ_DTR");
571 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
572 if (AICE_FORMAT_DTHMA
!= result
) {
573 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
574 AICE_FORMAT_DTHMA
, result
);
578 uint8_t cmd_ack_code
;
579 uint8_t extra_length
;
580 uint8_t res_target_id
;
581 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
582 data
, AICE_LITTLE_ENDIAN
);
584 LOG_DEBUG("READ_DTR response, data: 0x%x", *data
);
586 if (cmd_ack_code
== AICE_CMD_T_READ_DTR
) {
589 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
590 AICE_CMD_T_READ_DTR
, cmd_ack_code
);
592 if (retry_times
> aice_max_retry_times
)
595 /* clear timeout and retry */
596 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
606 int aice_write_dtr(uint8_t target_id
, uint32_t data
)
611 if (usb_pack_command
)
612 aice_usb_packet_flush();
615 aice_pack_htdmc(AICE_CMD_T_WRITE_DTR
, target_id
, 0, 0, data
,
618 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
620 LOG_DEBUG("WRITE_DTR, data: 0x%x", data
);
622 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
623 if (AICE_FORMAT_DTHMB
!= result
) {
624 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
625 AICE_FORMAT_DTHMB
, result
);
629 uint8_t cmd_ack_code
;
630 uint8_t extra_length
;
631 uint8_t res_target_id
;
632 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
634 LOG_DEBUG("WRITE_DTR response");
636 if (cmd_ack_code
== AICE_CMD_T_WRITE_DTR
) {
639 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
640 AICE_CMD_T_WRITE_DTR
, cmd_ack_code
);
642 if (retry_times
> aice_max_retry_times
)
645 /* clear timeout and retry */
646 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
656 int aice_read_misc(uint8_t target_id
, uint32_t address
, uint32_t *data
)
661 if (usb_pack_command
)
662 aice_usb_packet_flush();
665 aice_pack_htdma(AICE_CMD_T_READ_MISC
, target_id
, 0, address
);
667 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
669 LOG_DEBUG("READ_MISC, address: 0x%x", address
);
671 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
672 if (AICE_FORMAT_DTHMA
!= result
) {
673 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
674 AICE_FORMAT_DTHMA
, result
);
675 return ERROR_AICE_DISCONNECT
;
678 uint8_t cmd_ack_code
;
679 uint8_t extra_length
;
680 uint8_t res_target_id
;
681 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
682 data
, AICE_LITTLE_ENDIAN
);
684 LOG_DEBUG("READ_MISC response, data: 0x%x", *data
);
686 if (cmd_ack_code
== AICE_CMD_T_READ_MISC
) {
689 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
690 AICE_CMD_T_READ_MISC
, cmd_ack_code
);
692 if (retry_times
> aice_max_retry_times
)
695 /* clear timeout and retry */
696 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
706 int aice_write_misc(uint8_t target_id
, uint32_t address
, uint32_t data
)
711 if (usb_pack_command
)
712 aice_usb_packet_flush();
715 aice_pack_htdmc(AICE_CMD_T_WRITE_MISC
, target_id
, 0, address
,
716 data
, AICE_LITTLE_ENDIAN
);
718 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
720 LOG_DEBUG("WRITE_MISC, address: 0x%x, data: 0x%x", address
, data
);
722 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
723 if (AICE_FORMAT_DTHMB
!= result
) {
724 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
725 AICE_FORMAT_DTHMB
, result
);
729 uint8_t cmd_ack_code
;
730 uint8_t extra_length
;
731 uint8_t res_target_id
;
732 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
734 LOG_DEBUG("WRITE_MISC response");
736 if (cmd_ack_code
== AICE_CMD_T_WRITE_MISC
) {
739 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
740 AICE_CMD_T_WRITE_MISC
, cmd_ack_code
);
742 if (retry_times
> aice_max_retry_times
)
745 /* clear timeout and retry */
746 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
756 int aice_read_edmsr(uint8_t target_id
, uint32_t address
, uint32_t *data
)
761 if (usb_pack_command
)
762 aice_usb_packet_flush();
765 aice_pack_htdma(AICE_CMD_T_READ_EDMSR
, target_id
, 0, address
);
767 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
769 LOG_DEBUG("READ_EDMSR, address: 0x%x", address
);
771 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
772 if (AICE_FORMAT_DTHMA
!= result
) {
773 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
774 AICE_FORMAT_DTHMA
, result
);
778 uint8_t cmd_ack_code
;
779 uint8_t extra_length
;
780 uint8_t res_target_id
;
781 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
782 data
, AICE_LITTLE_ENDIAN
);
784 LOG_DEBUG("READ_EDMSR response, data: 0x%x", *data
);
786 if (cmd_ack_code
== AICE_CMD_T_READ_EDMSR
) {
789 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
790 AICE_CMD_T_READ_EDMSR
, cmd_ack_code
);
792 if (retry_times
> aice_max_retry_times
)
795 /* clear timeout and retry */
796 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
806 int aice_write_edmsr(uint8_t target_id
, uint32_t address
, uint32_t data
)
811 if (usb_pack_command
)
812 aice_usb_packet_flush();
815 aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR
, target_id
, 0, address
,
816 data
, AICE_LITTLE_ENDIAN
);
818 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
820 LOG_DEBUG("WRITE_EDMSR, address: 0x%x, data: 0x%x", address
, data
);
822 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
823 if (AICE_FORMAT_DTHMB
!= result
) {
824 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
825 AICE_FORMAT_DTHMB
, result
);
829 uint8_t cmd_ack_code
;
830 uint8_t extra_length
;
831 uint8_t res_target_id
;
832 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
834 LOG_DEBUG("WRITE_EDMSR response");
836 if (cmd_ack_code
== AICE_CMD_T_WRITE_EDMSR
) {
839 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
840 AICE_CMD_T_WRITE_EDMSR
, cmd_ack_code
);
842 if (retry_times
> aice_max_retry_times
)
845 /* clear timeout and retry */
846 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
856 static int aice_switch_to_big_endian(uint32_t *word
, uint8_t num_of_words
)
860 for (uint8_t i
= 0 ; i
< num_of_words
; i
++) {
861 tmp
= ((word
[i
] >> 24) & 0x000000FF) |
862 ((word
[i
] >> 8) & 0x0000FF00) |
863 ((word
[i
] << 8) & 0x00FF0000) |
864 ((word
[i
] << 24) & 0xFF000000);
871 static int aice_write_dim(uint8_t target_id
, uint32_t *word
, uint8_t num_of_words
)
874 uint32_t big_endian_word
[4];
877 if (usb_pack_command
)
878 aice_usb_packet_flush();
880 memcpy(big_endian_word
, word
, sizeof(big_endian_word
));
882 /** instruction is big-endian */
883 aice_switch_to_big_endian(big_endian_word
, num_of_words
);
886 aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM
, target_id
,
888 big_endian_word
, num_of_words
, AICE_LITTLE_ENDIAN
);
890 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
+ (num_of_words
- 1) * 4);
892 LOG_DEBUG("WRITE_DIM, data: 0x%08x, 0x%08x, 0x%08x, 0x%08x",
898 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
899 if (AICE_FORMAT_DTHMB
!= result
) {
900 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
901 AICE_FORMAT_DTHMB
, result
);
905 uint8_t cmd_ack_code
;
906 uint8_t extra_length
;
907 uint8_t res_target_id
;
908 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
910 LOG_DEBUG("WRITE_DIM response");
912 if (cmd_ack_code
== AICE_CMD_T_WRITE_DIM
) {
915 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
916 AICE_CMD_T_WRITE_DIM
, cmd_ack_code
);
918 if (retry_times
> aice_max_retry_times
)
921 /* clear timeout and retry */
922 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
932 static int aice_do_execute(uint8_t target_id
)
937 if (usb_pack_command
)
938 aice_usb_packet_flush();
941 aice_pack_htdmc(AICE_CMD_T_EXECUTE
, target_id
, 0, 0, 0, AICE_LITTLE_ENDIAN
);
943 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
945 LOG_DEBUG("EXECUTE");
947 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
948 if (AICE_FORMAT_DTHMB
!= result
) {
949 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
950 AICE_FORMAT_DTHMB
, result
);
954 uint8_t cmd_ack_code
;
955 uint8_t extra_length
;
956 uint8_t res_target_id
;
957 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
959 LOG_DEBUG("EXECUTE response");
961 if (cmd_ack_code
== AICE_CMD_T_EXECUTE
) {
964 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
965 AICE_CMD_T_EXECUTE
, cmd_ack_code
);
967 if (retry_times
> aice_max_retry_times
)
970 /* clear timeout and retry */
971 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
981 int aice_write_mem_b(uint8_t target_id
, uint32_t address
, uint32_t data
)
986 LOG_DEBUG("WRITE_MEM_B, ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
990 if (usb_pack_command
) {
991 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B
, target_id
, 0, address
,
992 data
& 0x000000FF, data_endian
);
993 aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
, AICE_FORMAT_DTHMB
);
996 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B
, target_id
, 0,
997 address
, data
& 0x000000FF, data_endian
);
998 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1000 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1001 if (AICE_FORMAT_DTHMB
!= result
) {
1002 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1003 AICE_FORMAT_DTHMB
, result
);
1007 uint8_t cmd_ack_code
;
1008 uint8_t extra_length
;
1009 uint8_t res_target_id
;
1010 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1012 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM_B
) {
1015 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1016 AICE_CMD_T_WRITE_MEM_B
, cmd_ack_code
);
1018 if (retry_times
> aice_max_retry_times
)
1021 /* clear timeout and retry */
1022 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1033 int aice_write_mem_h(uint8_t target_id
, uint32_t address
, uint32_t data
)
1036 int retry_times
= 0;
1038 LOG_DEBUG("WRITE_MEM_H, ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1042 if (usb_pack_command
) {
1043 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H
, target_id
, 0,
1044 (address
>> 1) & 0x7FFFFFFF, data
& 0x0000FFFF, data_endian
);
1045 aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
, AICE_FORMAT_DTHMB
);
1048 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H
, target_id
, 0,
1049 (address
>> 1) & 0x7FFFFFFF, data
& 0x0000FFFF, data_endian
);
1050 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1052 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1053 if (AICE_FORMAT_DTHMB
!= result
) {
1054 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1055 AICE_FORMAT_DTHMB
, result
);
1059 uint8_t cmd_ack_code
;
1060 uint8_t extra_length
;
1061 uint8_t res_target_id
;
1062 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1064 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM_H
) {
1067 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1068 AICE_CMD_T_WRITE_MEM_H
, cmd_ack_code
);
1070 if (retry_times
> aice_max_retry_times
)
1073 /* clear timeout and retry */
1074 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1085 int aice_write_mem(uint8_t target_id
, uint32_t address
, uint32_t data
)
1088 int retry_times
= 0;
1090 LOG_DEBUG("WRITE_MEM, ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1094 if (usb_pack_command
) {
1095 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM
, target_id
, 0,
1096 (address
>> 2) & 0x3FFFFFFF, data
, data_endian
);
1097 aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
, AICE_FORMAT_DTHMB
);
1100 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM
, target_id
, 0,
1101 (address
>> 2) & 0x3FFFFFFF, data
, data_endian
);
1102 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1104 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1105 if (AICE_FORMAT_DTHMB
!= result
) {
1106 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1107 AICE_FORMAT_DTHMB
, result
);
1111 uint8_t cmd_ack_code
;
1112 uint8_t extra_length
;
1113 uint8_t res_target_id
;
1114 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1116 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM
) {
1119 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1120 AICE_CMD_T_WRITE_MEM
, cmd_ack_code
);
1122 if (retry_times
> aice_max_retry_times
)
1125 /* clear timeout and retry */
1126 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1137 int aice_fastread_mem(uint8_t target_id
, uint8_t *word
, uint32_t num_of_words
)
1140 int retry_times
= 0;
1142 if (usb_pack_command
)
1143 aice_usb_packet_flush();
1146 aice_pack_htdmb(AICE_CMD_T_FASTREAD_MEM
, target_id
, num_of_words
- 1, 0);
1148 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1150 LOG_DEBUG("FASTREAD_MEM, # of DATA %08" PRIx32
, num_of_words
);
1152 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4);
1154 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1155 AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4, result
);
1159 uint8_t cmd_ack_code
;
1160 uint8_t extra_length
;
1161 uint8_t res_target_id
;
1162 aice_unpack_dthma_multiple_data(&cmd_ack_code
, &res_target_id
,
1163 &extra_length
, word
, data_endian
);
1165 if (cmd_ack_code
== AICE_CMD_T_FASTREAD_MEM
) {
1168 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1169 AICE_CMD_T_FASTREAD_MEM
, cmd_ack_code
);
1171 if (retry_times
> aice_max_retry_times
)
1174 /* clear timeout and retry */
1175 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1185 int aice_fastwrite_mem(uint8_t target_id
, const uint8_t *word
, uint32_t num_of_words
)
1188 int retry_times
= 0;
1190 if (usb_pack_command
)
1191 aice_usb_packet_flush();
1194 aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM
, target_id
,
1195 num_of_words
- 1, 0, word
, data_endian
);
1197 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
+ (num_of_words
- 1) * 4);
1199 LOG_DEBUG("FASTWRITE_MEM, # of DATA %08" PRIx32
, num_of_words
);
1201 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1202 if (AICE_FORMAT_DTHMB
!= result
) {
1203 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1204 AICE_FORMAT_DTHMB
, result
);
1208 uint8_t cmd_ack_code
;
1209 uint8_t extra_length
;
1210 uint8_t res_target_id
;
1211 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1213 if (cmd_ack_code
== AICE_CMD_T_FASTWRITE_MEM
) {
1216 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1217 AICE_CMD_T_FASTWRITE_MEM
, cmd_ack_code
);
1219 if (retry_times
> aice_max_retry_times
)
1222 /* clear timeout and retry */
1223 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1233 int aice_read_mem_b(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1236 int retry_times
= 0;
1238 if (usb_pack_command
)
1239 aice_usb_packet_flush();
1242 aice_pack_htdmb(AICE_CMD_T_READ_MEM_B
, target_id
, 0, address
);
1244 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1246 LOG_DEBUG("READ_MEM_B");
1248 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1249 if (AICE_FORMAT_DTHMA
!= result
) {
1250 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1251 AICE_FORMAT_DTHMA
, result
);
1255 uint8_t cmd_ack_code
;
1256 uint8_t extra_length
;
1257 uint8_t res_target_id
;
1258 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1261 LOG_DEBUG("READ_MEM_B response, data: 0x%x", *data
);
1263 if (cmd_ack_code
== AICE_CMD_T_READ_MEM_B
) {
1266 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1267 AICE_CMD_T_READ_MEM_B
, cmd_ack_code
);
1269 if (retry_times
> aice_max_retry_times
)
1272 /* clear timeout and retry */
1273 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1283 int aice_read_mem_h(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1286 int retry_times
= 0;
1288 if (usb_pack_command
)
1289 aice_usb_packet_flush();
1292 aice_pack_htdmb(AICE_CMD_T_READ_MEM_H
, target_id
, 0, (address
>> 1) & 0x7FFFFFFF);
1294 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1296 LOG_DEBUG("READ_MEM_H");
1298 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1299 if (AICE_FORMAT_DTHMA
!= result
) {
1300 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1301 AICE_FORMAT_DTHMA
, result
);
1305 uint8_t cmd_ack_code
;
1306 uint8_t extra_length
;
1307 uint8_t res_target_id
;
1308 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1311 LOG_DEBUG("READ_MEM_H response, data: 0x%x", *data
);
1313 if (cmd_ack_code
== AICE_CMD_T_READ_MEM_H
) {
1316 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1317 AICE_CMD_T_READ_MEM_H
, cmd_ack_code
);
1319 if (retry_times
> aice_max_retry_times
)
1322 /* clear timeout and retry */
1323 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1333 int aice_read_mem(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1336 int retry_times
= 0;
1338 if (usb_pack_command
)
1339 aice_usb_packet_flush();
1342 aice_pack_htdmb(AICE_CMD_T_READ_MEM
, target_id
, 0,
1343 (address
>> 2) & 0x3FFFFFFF);
1345 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1347 LOG_DEBUG("READ_MEM");
1349 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1350 if (AICE_FORMAT_DTHMA
!= result
) {
1351 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1352 AICE_FORMAT_DTHMA
, result
);
1356 uint8_t cmd_ack_code
;
1357 uint8_t extra_length
;
1358 uint8_t res_target_id
;
1359 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1362 LOG_DEBUG("READ_MEM response, data: 0x%x", *data
);
1364 if (cmd_ack_code
== AICE_CMD_T_READ_MEM
) {
1367 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1368 AICE_CMD_T_READ_MEM
, cmd_ack_code
);
1370 if (retry_times
> aice_max_retry_times
)
1373 /* clear timeout and retry */
1374 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1384 /***************************************************************************/
1385 /* End of AICE commands */
1387 typedef int (*read_mem_func_t
)(uint32_t address
, uint32_t *data
);
1388 typedef int (*write_mem_func_t
)(uint32_t address
, uint32_t data
);
1395 uint32_t log2_line_size
;
1398 static uint32_t r0_backup
;
1399 static uint32_t r1_backup
;
1400 static uint32_t host_dtr_backup
;
1401 static uint32_t target_dtr_backup
;
1402 static uint32_t edmsw_backup
;
1403 static uint32_t edm_ctl_backup
;
1404 static bool debug_under_dex_on
;
1405 static bool dex_use_psw_on
;
1406 static bool host_dtr_valid
;
1407 static bool target_dtr_valid
;
1408 static enum nds_memory_access access_channel
= NDS_MEMORY_ACC_CPU
;
1409 static enum nds_memory_select memory_select
= NDS_MEMORY_SELECT_AUTO
;
1410 static enum aice_target_state_s core_state
= AICE_TARGET_UNKNOWN
;
1411 static uint32_t edm_version
;
1412 static struct cache_info icache
= {0, 0, 0, 0, 0};
1413 static struct cache_info dcache
= {0, 0, 0, 0, 0};
1414 static bool cache_init
;
1415 static char *custom_srst_script
;
1416 static char *custom_trst_script
;
1417 static char *custom_restart_script
;
1418 static uint32_t aice_count_to_check_dbger
= 30;
1420 static int aice_read_reg(uint32_t num
, uint32_t *val
);
1421 static int aice_write_reg(uint32_t num
, uint32_t val
);
1423 static int check_suppressed_exception(uint32_t dbger_value
)
1427 /* the default value of handling_suppressed_exception is false */
1428 static bool handling_suppressed_exception
;
1430 if (handling_suppressed_exception
)
1433 if ((dbger_value
& NDS_DBGER_ALL_SUPRS_EX
) == NDS_DBGER_ALL_SUPRS_EX
) {
1434 LOG_ERROR("<-- TARGET WARNING! Exception is detected and suppressed. -->");
1435 handling_suppressed_exception
= true;
1437 aice_read_reg(IR4
, &ir4_value
);
1438 /* Clear IR6.SUPRS_EXC, IR6.IMP_EXC */
1439 aice_read_reg(IR6
, &ir6_value
);
1441 * For MCU version(MSC_CFG.MCU == 1) like V3m
1442 * | SWID[30:16] | Reserved[15:10] | SUPRS_EXC[9] | IMP_EXC[8]
1443 * |VECTOR[7:5] | INST[4] | Exc Type[3:0] |
1445 * For non-MCU version(MSC_CFG.MCU == 0) like V3
1446 * | SWID[30:16] | Reserved[15:14] | SUPRS_EXC[13] | IMP_EXC[12]
1447 * | VECTOR[11:5] | INST[4] | Exc Type[3:0] |
1449 LOG_INFO("EVA: 0x%08x", ir4_value
);
1450 LOG_INFO("ITYPE: 0x%08x", ir6_value
);
1452 ir6_value
= ir6_value
& (~0x300); /* for MCU */
1453 ir6_value
= ir6_value
& (~0x3000); /* for non-MCU */
1454 aice_write_reg(IR6
, ir6_value
);
1456 handling_suppressed_exception
= false;
1462 static int check_privilege(uint32_t dbger_value
)
1464 if ((dbger_value
& NDS_DBGER_ILL_SEC_ACC
) == NDS_DBGER_ILL_SEC_ACC
) {
1465 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege "
1466 "to execute the debug operations. -->");
1468 /* Clear DBGER.ILL_SEC_ACC */
1469 if (aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
,
1470 NDS_DBGER_ILL_SEC_ACC
) != ERROR_OK
)
1477 static int aice_check_dbger(uint32_t expect_status
)
1480 uint32_t value_dbger
;
1483 aice_read_misc(current_target_id
, NDS_EDM_MISC_DBGER
, &value_dbger
);
1485 if ((value_dbger
& expect_status
) == expect_status
) {
1486 if (ERROR_OK
!= check_suppressed_exception(value_dbger
))
1488 if (ERROR_OK
!= check_privilege(value_dbger
))
1497 if (i
== aice_count_to_check_dbger
)
1498 then
= timeval_ms();
1499 if (i
>= aice_count_to_check_dbger
) {
1500 if ((timeval_ms() - then
) > 1000) {
1501 LOG_ERROR("Timeout (1000ms) waiting for $DBGER status "
1502 "being 0x%08x", expect_status
);
1512 static int aice_execute_dim(uint32_t *insts
, uint8_t n_inst
)
1515 if (aice_write_dim(current_target_id
, insts
, n_inst
) != ERROR_OK
)
1518 /** clear DBGER.DPED */
1519 if (aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
, NDS_DBGER_DPED
) != ERROR_OK
)
1523 if (aice_do_execute(current_target_id
) != ERROR_OK
)
1526 /** read DBGER.DPED */
1527 if (aice_check_dbger(NDS_DBGER_DPED
) != ERROR_OK
) {
1528 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly: "
1529 "0x%08x 0x%08x 0x%08x 0x%08x. -->",
1540 static int aice_read_reg(uint32_t num
, uint32_t *val
)
1542 LOG_DEBUG("aice_read_reg, reg_no: 0x%08x", num
);
1544 uint32_t instructions
[4]; /** execute instructions in DIM */
1546 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(num
)) { /* general registers */
1547 instructions
[0] = MTSR_DTR(num
);
1548 instructions
[1] = DSB
;
1549 instructions
[2] = NOP
;
1550 instructions
[3] = BEQ_MINUS_12
;
1551 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(num
)) { /* user special registers */
1552 instructions
[0] = MFUSR_G0(0, nds32_reg_sr_index(num
));
1553 instructions
[1] = MTSR_DTR(0);
1554 instructions
[2] = DSB
;
1555 instructions
[3] = BEQ_MINUS_12
;
1556 } else if (NDS32_REG_TYPE_AUMR
== nds32_reg_type(num
)) { /* audio registers */
1557 if ((CB_CTL
<= num
) && (num
<= CBE3
)) {
1558 instructions
[0] = AMFAR2(0, nds32_reg_sr_index(num
));
1559 instructions
[1] = MTSR_DTR(0);
1560 instructions
[2] = DSB
;
1561 instructions
[3] = BEQ_MINUS_12
;
1563 instructions
[0] = AMFAR(0, nds32_reg_sr_index(num
));
1564 instructions
[1] = MTSR_DTR(0);
1565 instructions
[2] = DSB
;
1566 instructions
[3] = BEQ_MINUS_12
;
1568 } else if (NDS32_REG_TYPE_FPU
== nds32_reg_type(num
)) { /* fpu registers */
1570 instructions
[0] = FMFCSR
;
1571 instructions
[1] = MTSR_DTR(0);
1572 instructions
[2] = DSB
;
1573 instructions
[3] = BEQ_MINUS_12
;
1574 } else if (FPCFG
== num
) {
1575 instructions
[0] = FMFCFG
;
1576 instructions
[1] = MTSR_DTR(0);
1577 instructions
[2] = DSB
;
1578 instructions
[3] = BEQ_MINUS_12
;
1580 if (FS0
<= num
&& num
<= FS31
) { /* single precision */
1581 instructions
[0] = FMFSR(0, nds32_reg_sr_index(num
));
1582 instructions
[1] = MTSR_DTR(0);
1583 instructions
[2] = DSB
;
1584 instructions
[3] = BEQ_MINUS_12
;
1585 } else if (FD0
<= num
&& num
<= FD31
) { /* double precision */
1586 instructions
[0] = FMFDR(0, nds32_reg_sr_index(num
));
1587 instructions
[1] = MTSR_DTR(0);
1588 instructions
[2] = DSB
;
1589 instructions
[3] = BEQ_MINUS_12
;
1592 } else { /* system registers */
1593 instructions
[0] = MFSR(0, nds32_reg_sr_index(num
));
1594 instructions
[1] = MTSR_DTR(0);
1595 instructions
[2] = DSB
;
1596 instructions
[3] = BEQ_MINUS_12
;
1599 aice_execute_dim(instructions
, 4);
1601 uint32_t value_edmsw
;
1602 aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
1603 if (value_edmsw
& NDS_EDMSW_WDV
)
1604 aice_read_dtr(current_target_id
, val
);
1606 LOG_ERROR("<-- TARGET ERROR! The debug target failed to update "
1607 "the DTR register. -->");
1614 static int aice_usb_read_reg(uint32_t num
, uint32_t *val
)
1616 LOG_DEBUG("aice_usb_read_reg");
1620 } else if (num
== R1
) {
1622 } else if (num
== DR41
) {
1623 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
1624 * As user wants to read these registers, OpenOCD should return
1625 * the backup values, instead of reading the real values.
1626 * As user wants to write these registers, OpenOCD should write
1627 * to the backup values, instead of writing to real registers. */
1628 *val
= edmsw_backup
;
1629 } else if (num
== DR42
) {
1630 *val
= edm_ctl_backup
;
1631 } else if ((target_dtr_valid
== true) && (num
== DR43
)) {
1632 *val
= target_dtr_backup
;
1634 if (ERROR_OK
!= aice_read_reg(num
, val
))
1641 static int aice_write_reg(uint32_t num
, uint32_t val
)
1643 LOG_DEBUG("aice_write_reg, reg_no: 0x%08x, value: 0x%08x", num
, val
);
1645 uint32_t instructions
[4]; /** execute instructions in DIM */
1646 uint32_t value_edmsw
;
1648 aice_write_dtr(current_target_id
, val
);
1649 aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
1650 if (0 == (value_edmsw
& NDS_EDMSW_RDV
)) {
1651 LOG_ERROR("<-- TARGET ERROR! AICE failed to write to the DTR register. -->");
1655 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(num
)) { /* general registers */
1656 instructions
[0] = MFSR_DTR(num
);
1657 instructions
[1] = DSB
;
1658 instructions
[2] = NOP
;
1659 instructions
[3] = BEQ_MINUS_12
;
1660 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(num
)) { /* user special registers */
1661 instructions
[0] = MFSR_DTR(0);
1662 instructions
[1] = MTUSR_G0(0, nds32_reg_sr_index(num
));
1663 instructions
[2] = DSB
;
1664 instructions
[3] = BEQ_MINUS_12
;
1665 } else if (NDS32_REG_TYPE_AUMR
== nds32_reg_type(num
)) { /* audio registers */
1666 if ((CB_CTL
<= num
) && (num
<= CBE3
)) {
1667 instructions
[0] = MFSR_DTR(0);
1668 instructions
[1] = AMTAR2(0, nds32_reg_sr_index(num
));
1669 instructions
[2] = DSB
;
1670 instructions
[3] = BEQ_MINUS_12
;
1672 instructions
[0] = MFSR_DTR(0);
1673 instructions
[1] = AMTAR(0, nds32_reg_sr_index(num
));
1674 instructions
[2] = DSB
;
1675 instructions
[3] = BEQ_MINUS_12
;
1677 } else if (NDS32_REG_TYPE_FPU
== nds32_reg_type(num
)) { /* fpu registers */
1679 instructions
[0] = MFSR_DTR(0);
1680 instructions
[1] = FMTCSR
;
1681 instructions
[2] = DSB
;
1682 instructions
[3] = BEQ_MINUS_12
;
1683 } else if (FPCFG
== num
) {
1684 /* FPCFG is readonly */
1686 if (FS0
<= num
&& num
<= FS31
) { /* single precision */
1687 instructions
[0] = MFSR_DTR(0);
1688 instructions
[1] = FMTSR(0, nds32_reg_sr_index(num
));
1689 instructions
[2] = DSB
;
1690 instructions
[3] = BEQ_MINUS_12
;
1691 } else if (FD0
<= num
&& num
<= FD31
) { /* double precision */
1692 instructions
[0] = MFSR_DTR(0);
1693 instructions
[1] = FMTDR(0, nds32_reg_sr_index(num
));
1694 instructions
[2] = DSB
;
1695 instructions
[3] = BEQ_MINUS_12
;
1699 instructions
[0] = MFSR_DTR(0);
1700 instructions
[1] = MTSR(0, nds32_reg_sr_index(num
));
1701 instructions
[2] = DSB
;
1702 instructions
[3] = BEQ_MINUS_12
;
1705 return aice_execute_dim(instructions
, 4);
1708 static int aice_usb_write_reg(uint32_t num
, uint32_t val
)
1710 LOG_DEBUG("aice_usb_write_reg");
1716 else if (num
== DR42
)
1717 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
1718 * As user wants to read these registers, OpenOCD should return
1719 * the backup values, instead of reading the real values.
1720 * As user wants to write these registers, OpenOCD should write
1721 * to the backup values, instead of writing to real registers. */
1722 edm_ctl_backup
= val
;
1723 else if ((target_dtr_valid
== true) && (num
== DR43
))
1724 target_dtr_backup
= val
;
1726 return aice_write_reg(num
, val
);
1731 static int aice_usb_open(struct aice_port_param_s
*param
)
1733 const uint16_t vids
[] = { param
->vid
, 0 };
1734 const uint16_t pids
[] = { param
->pid
, 0 };
1735 struct jtag_libusb_device_handle
*devh
;
1737 if (jtag_libusb_open(vids
, pids
, &devh
) != ERROR_OK
)
1740 /* BE ***VERY CAREFUL*** ABOUT MAKING CHANGES IN THIS
1741 * AREA!!!!!!!!!!! The behavior of libusb is not completely
1742 * consistent across Windows, Linux, and Mac OS X platforms.
1743 * The actions taken in the following compiler conditionals may
1744 * not agree with published documentation for libusb, but were
1745 * found to be necessary through trials and tribulations. Even
1746 * little tweaks can break one or more platforms, so if you do
1747 * make changes test them carefully on all platforms before
1753 jtag_libusb_reset_device(devh
);
1758 /* reopen jlink after usb_reset
1759 * on win32 this may take a second or two to re-enumerate */
1761 while ((retval
= jtag_libusb_open(vids
, pids
, &devh
)) != ERROR_OK
) {
1767 if (ERROR_OK
!= retval
)
1773 /* usb_set_configuration required under win32 */
1774 struct jtag_libusb_device
*udev
= jtag_libusb_get_device(devh
);
1775 jtag_libusb_set_configuration(devh
, 0);
1776 jtag_libusb_claim_interface(devh
, 0);
1778 unsigned int aice_read_ep
;
1779 unsigned int aice_write_ep
;
1780 jtag_libusb_get_endpoints(udev
, &aice_read_ep
, &aice_write_ep
);
1782 aice_handler
.usb_read_ep
= aice_read_ep
;
1783 aice_handler
.usb_write_ep
= aice_write_ep
;
1784 aice_handler
.usb_handle
= devh
;
1789 static int aice_usb_read_reg_64(uint32_t num
, uint64_t *val
)
1791 LOG_DEBUG("aice_usb_read_reg_64, %s", nds32_reg_simple_name(num
));
1794 uint32_t high_value
;
1796 if (ERROR_OK
!= aice_read_reg(num
, &value
))
1799 aice_read_reg(R1
, &high_value
);
1801 LOG_DEBUG("low: 0x%08x, high: 0x%08x\n", value
, high_value
);
1803 if (data_endian
== AICE_BIG_ENDIAN
)
1804 *val
= (((uint64_t)high_value
) << 32) | value
;
1806 *val
= (((uint64_t)value
) << 32) | high_value
;
1811 static int aice_usb_write_reg_64(uint32_t num
, uint64_t val
)
1814 uint32_t high_value
;
1816 if (data_endian
== AICE_BIG_ENDIAN
) {
1817 value
= val
& 0xFFFFFFFF;
1818 high_value
= (val
>> 32) & 0xFFFFFFFF;
1820 high_value
= val
& 0xFFFFFFFF;
1821 value
= (val
>> 32) & 0xFFFFFFFF;
1824 LOG_DEBUG("aice_usb_write_reg_64, %s, low: 0x%08x, high: 0x%08x\n",
1825 nds32_reg_simple_name(num
), value
, high_value
);
1827 aice_write_reg(R1
, high_value
);
1828 return aice_write_reg(num
, value
);
1831 static int aice_get_version_info(void)
1833 uint32_t hardware_version
;
1834 uint32_t firmware_version
;
1835 uint32_t fpga_version
;
1837 if (aice_read_ctrl(AICE_READ_CTRL_GET_HARDWARE_VERSION
, &hardware_version
) != ERROR_OK
)
1840 if (aice_read_ctrl(AICE_READ_CTRL_GET_FIRMWARE_VERSION
, &firmware_version
) != ERROR_OK
)
1843 if (aice_read_ctrl(AICE_READ_CTRL_GET_FPGA_VERSION
, &fpga_version
) != ERROR_OK
)
1846 LOG_INFO("AICE version: hw_ver = 0x%x, fw_ver = 0x%x, fpga_ver = 0x%x",
1847 hardware_version
, firmware_version
, fpga_version
);
1852 #define LINE_BUFFER_SIZE 1024
1854 static int aice_execute_custom_script(const char *script
)
1857 char line_buffer
[LINE_BUFFER_SIZE
];
1861 uint32_t write_ctrl_value
;
1864 script_fd
= fopen(script
, "r");
1865 if (script_fd
== NULL
) {
1868 while (fgets(line_buffer
, LINE_BUFFER_SIZE
, script_fd
) != NULL
) {
1869 /* execute operations */
1871 op_str
= strstr(line_buffer
, "set");
1872 if (op_str
!= NULL
) {
1874 goto get_reset_type
;
1877 op_str
= strstr(line_buffer
, "clear");
1881 reset_str
= strstr(op_str
, "srst");
1882 if (reset_str
!= NULL
) {
1884 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_SRST
;
1886 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_SRST
;
1889 reset_str
= strstr(op_str
, "dbgi");
1890 if (reset_str
!= NULL
) {
1892 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_DBGI
;
1894 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_DBGI
;
1897 reset_str
= strstr(op_str
, "trst");
1898 if (reset_str
!= NULL
) {
1900 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_TRST
;
1902 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_TRST
;
1908 delay
= strtoul(reset_str
+ 4, NULL
, 0);
1909 write_ctrl_value
|= (delay
<< 16);
1911 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY
,
1912 write_ctrl_value
) != ERROR_OK
) {
1923 static int aice_edm_reset(void)
1925 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
1931 static int aice_usb_set_clock(int set_clock
)
1933 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL
,
1934 AICE_TCK_CONTROL_TCK_SCAN
) != ERROR_OK
)
1937 /* Read out TCK_SCAN clock value */
1938 uint32_t scan_clock
;
1939 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &scan_clock
) != ERROR_OK
)
1944 uint32_t scan_base_freq
;
1945 if (scan_clock
& 0x8)
1946 scan_base_freq
= 48000; /* 48 MHz */
1948 scan_base_freq
= 30000; /* 30 MHz */
1950 uint32_t set_base_freq
;
1951 if (set_clock
& 0x8)
1952 set_base_freq
= 48000;
1954 set_base_freq
= 30000;
1958 set_freq
= set_base_freq
>> (set_clock
& 0x7);
1959 scan_freq
= scan_base_freq
>> (scan_clock
& 0x7);
1961 if (scan_freq
< set_freq
) {
1962 LOG_ERROR("User specifies higher jtag clock than TCK_SCAN clock");
1966 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL
, set_clock
) != ERROR_OK
)
1969 uint32_t check_speed
;
1970 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &check_speed
) != ERROR_OK
)
1973 if (((int)check_speed
& 0x0F) != set_clock
) {
1974 LOG_ERROR("Set jtag clock failed");
1981 static int aice_edm_init(void)
1983 aice_write_edmsr(current_target_id
, NDS_EDM_SR_DIMBR
, 0xFFFF0000);
1985 /* unconditionally try to turn on V3_EDM_MODE */
1986 uint32_t edm_ctl_value
;
1987 aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, &edm_ctl_value
);
1988 aice_write_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
| 0x00000040);
1990 aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
,
1991 NDS_DBGER_DPED
| NDS_DBGER_CRST
| NDS_DBGER_AT_MAX
);
1992 aice_write_misc(current_target_id
, NDS_EDM_MISC_DIMIR
, 0);
1994 /* get EDM version */
1995 uint32_t value_edmcfg
;
1996 aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDM_CFG
, &value_edmcfg
);
1997 edm_version
= (value_edmcfg
>> 16) & 0xFFFF;
2002 static bool is_v2_edm(void)
2004 if ((edm_version
& 0x1000) == 0)
2010 static int aice_init_edm_registers(bool clear_dex_use_psw
)
2012 /* enable DEH_SEL & MAX_STOP & V3_EDM_MODE & DBGI_MASK */
2013 uint32_t host_edm_ctl
= edm_ctl_backup
| 0xA000004F;
2014 if (clear_dex_use_psw
)
2015 /* After entering debug mode, OpenOCD may set
2016 * DEX_USE_PSW accidentally through backup value
2017 * of target EDM_CTL.
2018 * So, clear DEX_USE_PSW by force. */
2019 host_edm_ctl
&= ~(0x40000000);
2021 LOG_DEBUG("aice_init_edm_registers - EDM_CTL: 0x%08x", host_edm_ctl
);
2023 int result
= aice_write_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, host_edm_ctl
);
2029 * EDM_CTL will be modified by OpenOCD as debugging. OpenOCD has the
2030 * responsibility to keep EDM_CTL untouched after debugging.
2032 * There are two scenarios to consider:
2033 * 1. single step/running as debugging (running under debug session)
2034 * 2. detached from gdb (exit debug session)
2036 * So, we need to bakcup EDM_CTL before halted and restore it after
2037 * running. The difference of these two scenarios is EDM_CTL.DEH_SEL
2038 * is on for scenario 1, and off for scenario 2.
2040 static int aice_backup_edm_registers(void)
2042 int result
= aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, &edm_ctl_backup
);
2044 /* To call aice_backup_edm_registers() after DEX on, DEX_USE_PSW
2045 * may be not correct. (For example, hit breakpoint, then backup
2046 * EDM_CTL. EDM_CTL.DEX_USE_PSW will be cleared.) Because debug
2047 * interrupt will clear DEX_USE_PSW, DEX_USE_PSW is always off after
2048 * DEX is on. It only backups correct value before OpenOCD issues DBGI.
2049 * (Backup EDM_CTL, then issue DBGI actively (refer aice_usb_halt())) */
2050 if (edm_ctl_backup
& 0x40000000)
2051 dex_use_psw_on
= true;
2053 dex_use_psw_on
= false;
2055 LOG_DEBUG("aice_backup_edm_registers - EDM_CTL: 0x%08x, DEX_USE_PSW: %s",
2056 edm_ctl_backup
, dex_use_psw_on
? "on" : "off");
2061 static int aice_restore_edm_registers(void)
2063 LOG_DEBUG("aice_restore_edm_registers -");
2065 /* set DEH_SEL, because target still under EDM control */
2066 int result
= aice_write_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
,
2067 edm_ctl_backup
| 0x80000000);
2072 static int aice_backup_tmp_registers(void)
2074 LOG_DEBUG("backup_tmp_registers -");
2076 /* backup target DTR first(if the target DTR is valid) */
2077 uint32_t value_edmsw
;
2078 aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
2079 edmsw_backup
= value_edmsw
;
2080 if (value_edmsw
& 0x1) { /* EDMSW.WDV == 1 */
2081 aice_read_dtr(current_target_id
, &target_dtr_backup
);
2082 target_dtr_valid
= true;
2084 LOG_DEBUG("Backup target DTR: 0x%08x", target_dtr_backup
);
2086 target_dtr_valid
= false;
2089 /* Target DTR has been backup, then backup $R0 and $R1 */
2090 aice_read_reg(R0
, &r0_backup
);
2091 aice_read_reg(R1
, &r1_backup
);
2093 /* backup host DTR(if the host DTR is valid) */
2094 if (value_edmsw
& 0x2) { /* EDMSW.RDV == 1*/
2095 /* read out host DTR and write into target DTR, then use aice_read_edmsr to
2097 uint32_t instructions
[4] = {
2098 MFSR_DTR(R0
), /* R0 has already been backup */
2103 aice_execute_dim(instructions
, 4);
2105 aice_read_dtr(current_target_id
, &host_dtr_backup
);
2106 host_dtr_valid
= true;
2108 LOG_DEBUG("Backup host DTR: 0x%08x", host_dtr_backup
);
2110 host_dtr_valid
= false;
2113 LOG_DEBUG("r0: 0x%08x, r1: 0x%08x", r0_backup
, r1_backup
);
2118 static int aice_restore_tmp_registers(void)
2120 LOG_DEBUG("restore_tmp_registers - r0: 0x%08x, r1: 0x%08x", r0_backup
, r1_backup
);
2122 if (target_dtr_valid
) {
2123 uint32_t instructions
[4] = {
2124 SETHI(R0
, target_dtr_backup
>> 12),
2125 ORI(R0
, R0
, target_dtr_backup
& 0x00000FFF),
2129 aice_execute_dim(instructions
, 4);
2131 instructions
[0] = MTSR_DTR(R0
);
2132 instructions
[1] = DSB
;
2133 instructions
[2] = NOP
;
2134 instructions
[3] = BEQ_MINUS_12
;
2135 aice_execute_dim(instructions
, 4);
2137 LOG_DEBUG("Restore target DTR: 0x%08x", target_dtr_backup
);
2140 aice_write_reg(R0
, r0_backup
);
2141 aice_write_reg(R1
, r1_backup
);
2143 if (host_dtr_valid
) {
2144 aice_write_dtr(current_target_id
, host_dtr_backup
);
2146 LOG_DEBUG("Restore host DTR: 0x%08x", host_dtr_backup
);
2152 static int aice_open_device(struct aice_port_param_s
*param
)
2154 if (ERROR_OK
!= aice_usb_open(param
))
2157 if (ERROR_FAIL
== aice_get_version_info()) {
2158 LOG_ERROR("Cannot get AICE version!");
2162 LOG_INFO("AICE initialization started");
2164 /* attempt to reset Andes EDM */
2165 if (ERROR_FAIL
== aice_edm_reset()) {
2166 LOG_ERROR("Cannot initial AICE Interface!");
2170 if (ERROR_OK
!= aice_edm_init()) {
2171 LOG_ERROR("Cannot initial EDM!");
2178 static int aice_usb_set_jtag_clock(uint32_t a_clock
)
2180 jtag_clock
= a_clock
;
2182 if (ERROR_OK
!= aice_usb_set_clock(a_clock
)) {
2183 LOG_ERROR("Cannot set AICE JTAG clock!");
2190 static int aice_usb_close(void)
2192 jtag_libusb_close(aice_handler
.usb_handle
);
2194 if (custom_srst_script
)
2195 free(custom_srst_script
);
2197 if (custom_trst_script
)
2198 free(custom_trst_script
);
2200 if (custom_restart_script
)
2201 free(custom_restart_script
);
2206 static int aice_usb_idcode(uint32_t *idcode
, uint8_t *num_of_idcode
)
2208 return aice_scan_chain(idcode
, num_of_idcode
);
2211 static int aice_usb_halt(void)
2213 if (core_state
== AICE_TARGET_HALTED
) {
2214 LOG_DEBUG("aice_usb_halt check halted");
2218 LOG_DEBUG("aice_usb_halt");
2220 /** backup EDM registers */
2221 aice_backup_edm_registers();
2222 /** init EDM for host debugging */
2223 /** no need to clear dex_use_psw, because dbgi will clear it */
2224 aice_init_edm_registers(false);
2226 /** Clear EDM_CTL.DBGIM & EDM_CTL.DBGACKM */
2227 uint32_t edm_ctl_value
;
2228 aice_read_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, &edm_ctl_value
);
2229 if (edm_ctl_value
& 0x3)
2230 aice_write_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
& ~(0x3));
2233 uint32_t acc_ctl_value
;
2235 debug_under_dex_on
= false;
2236 aice_read_misc(current_target_id
, NDS_EDM_MISC_DBGER
, &dbger
);
2238 if (dbger
& NDS_DBGER_AT_MAX
)
2239 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level. -->");
2241 if (dbger
& NDS_DBGER_DEX
) {
2242 if (is_v2_edm() == false) {
2243 /** debug 'debug mode'. use force_debug to issue dbgi */
2244 aice_read_misc(current_target_id
, NDS_EDM_MISC_ACC_CTL
, &acc_ctl_value
);
2245 acc_ctl_value
|= 0x8;
2246 aice_write_misc(current_target_id
, NDS_EDM_MISC_ACC_CTL
, acc_ctl_value
);
2247 debug_under_dex_on
= true;
2249 aice_write_misc(current_target_id
, NDS_EDM_MISC_EDM_CMDR
, 0);
2250 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2251 if (dbger
& NDS_DBGER_AT_MAX
)
2252 aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
, NDS_DBGER_AT_MAX
);
2255 /** Issue DBGI normally */
2256 aice_write_misc(current_target_id
, NDS_EDM_MISC_EDM_CMDR
, 0);
2257 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2258 if (dbger
& NDS_DBGER_AT_MAX
)
2259 aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
, NDS_DBGER_AT_MAX
);
2262 if (aice_check_dbger(NDS_DBGER_DEX
) != ERROR_OK
) {
2263 LOG_ERROR("<-- TARGET ERROR! Unable to stop the debug target through DBGI. -->");
2267 if (debug_under_dex_on
) {
2268 if (dex_use_psw_on
== false) {
2269 /* under debug 'debug mode', force $psw to 'debug mode' bahavior */
2270 /* !!!NOTICE!!! this is workaround for debug 'debug mode'.
2271 * it is only for debugging 'debug exception handler' purpose.
2272 * after openocd detaches from target, target behavior is
2275 uint32_t debug_mode_ir0_value
;
2276 aice_read_reg(IR0
, &ir0_value
);
2277 debug_mode_ir0_value
= ir0_value
| 0x408; /* turn on DEX, set POM = 1 */
2278 debug_mode_ir0_value
&= ~(0x000000C1); /* turn off DT/IT/GIE */
2279 aice_write_reg(IR0
, debug_mode_ir0_value
);
2283 /** set EDM_CTL.DBGIM & EDM_CTL.DBGACKM after halt */
2284 if (edm_ctl_value
& 0x3)
2285 aice_write_edmsr(current_target_id
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
);
2287 /* backup r0 & r1 */
2288 aice_backup_tmp_registers();
2289 core_state
= AICE_TARGET_HALTED
;
2294 static int aice_usb_state(enum aice_target_state_s
*state
)
2296 uint32_t dbger_value
;
2299 int result
= aice_read_misc(current_target_id
, NDS_EDM_MISC_DBGER
, &dbger_value
);
2301 if (ERROR_AICE_TIMEOUT
== result
) {
2302 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &ice_state
) != ERROR_OK
) {
2303 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2307 if ((ice_state
& 0x20) == 0) {
2308 LOG_ERROR("<-- TARGET ERROR! Target is disconnected with AICE. -->");
2313 } else if (ERROR_AICE_DISCONNECT
== result
) {
2314 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2318 if ((dbger_value
& NDS_DBGER_ILL_SEC_ACC
) == NDS_DBGER_ILL_SEC_ACC
) {
2319 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege. -->");
2321 /* Clear ILL_SEC_ACC */
2322 aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
, NDS_DBGER_ILL_SEC_ACC
);
2324 *state
= AICE_TARGET_RUNNING
;
2325 core_state
= AICE_TARGET_RUNNING
;
2326 } else if ((dbger_value
& NDS_DBGER_AT_MAX
) == NDS_DBGER_AT_MAX
) {
2327 /* Issue DBGI to exit cpu stall */
2330 /* Read OIPC to find out the trigger point */
2331 uint32_t ir11_value
;
2332 aice_read_reg(IR11
, &ir11_value
);
2334 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level; "
2335 "CPU is stalled at 0x%08x for debugging. -->", ir11_value
);
2337 *state
= AICE_TARGET_HALTED
;
2338 } else if ((dbger_value
& NDS_DBGER_CRST
) == NDS_DBGER_CRST
) {
2339 LOG_DEBUG("DBGER.CRST is on.");
2341 *state
= AICE_TARGET_RESET
;
2342 core_state
= AICE_TARGET_RUNNING
;
2345 aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
, NDS_DBGER_CRST
);
2346 } else if ((dbger_value
& NDS_DBGER_DEX
) == NDS_DBGER_DEX
) {
2347 if (AICE_TARGET_RUNNING
== core_state
) {
2348 /* enter debug mode, init EDM registers */
2349 /* backup EDM registers */
2350 aice_backup_edm_registers();
2351 /* init EDM for host debugging */
2352 aice_init_edm_registers(true);
2353 aice_backup_tmp_registers();
2354 core_state
= AICE_TARGET_HALTED
;
2355 } else if (AICE_TARGET_UNKNOWN
== core_state
) {
2356 /* debug 'debug mode', use force debug to halt core */
2359 *state
= AICE_TARGET_HALTED
;
2361 *state
= AICE_TARGET_RUNNING
;
2362 core_state
= AICE_TARGET_RUNNING
;
2368 static int aice_usb_reset(void)
2370 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
2373 if (custom_trst_script
== NULL
) {
2374 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2375 AICE_JTAG_PIN_CONTROL_TRST
) != ERROR_OK
)
2378 /* custom trst operations */
2379 if (aice_execute_custom_script(custom_trst_script
) != ERROR_OK
)
2383 if (aice_usb_set_clock(jtag_clock
) != ERROR_OK
)
2389 static int aice_issue_srst(void)
2391 LOG_DEBUG("aice_issue_srst");
2393 /* After issuing srst, target will be running. So we need to restore EDM_CTL. */
2394 aice_restore_edm_registers();
2396 if (custom_srst_script
== NULL
) {
2397 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2398 AICE_JTAG_PIN_CONTROL_SRST
) != ERROR_OK
)
2401 /* custom srst operations */
2402 if (aice_execute_custom_script(custom_srst_script
) != ERROR_OK
)
2406 /* wait CRST infinitely */
2407 uint32_t dbger_value
;
2410 if (aice_read_misc(current_target_id
,
2411 NDS_EDM_MISC_DBGER
, &dbger_value
) != ERROR_OK
)
2414 if (dbger_value
& NDS_DBGER_CRST
)
2422 host_dtr_valid
= false;
2423 target_dtr_valid
= false;
2425 core_state
= AICE_TARGET_RUNNING
;
2429 static int aice_issue_reset_hold(void)
2431 LOG_DEBUG("aice_issue_reset_hold");
2433 /* set no_dbgi_pin to 0 */
2434 uint32_t pin_status
;
2435 aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS
, &pin_status
);
2436 if (pin_status
| 0x4)
2437 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
& (~0x4));
2440 if (custom_restart_script
== NULL
) {
2441 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2442 AICE_JTAG_PIN_CONTROL_RESTART
) != ERROR_OK
)
2445 /* custom restart operations */
2446 if (aice_execute_custom_script(custom_restart_script
) != ERROR_OK
)
2450 if (aice_check_dbger(NDS_DBGER_CRST
| NDS_DBGER_DEX
) == ERROR_OK
) {
2451 aice_backup_tmp_registers();
2452 core_state
= AICE_TARGET_HALTED
;
2456 /* set no_dbgi_pin to 1 */
2457 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
| 0x4);
2459 /* issue restart again */
2460 if (custom_restart_script
== NULL
) {
2461 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2462 AICE_JTAG_PIN_CONTROL_RESTART
) != ERROR_OK
)
2465 /* custom restart operations */
2466 if (aice_execute_custom_script(custom_restart_script
) != ERROR_OK
)
2470 if (aice_check_dbger(NDS_DBGER_CRST
| NDS_DBGER_DEX
) == ERROR_OK
) {
2471 aice_backup_tmp_registers();
2472 core_state
= AICE_TARGET_HALTED
;
2477 /* do software reset-and-hold */
2482 aice_read_reg(IR3
, &value_ir3
);
2483 aice_write_reg(PC
, value_ir3
& 0xFFFF0000);
2489 static int aice_usb_assert_srst(enum aice_srst_type_s srst
)
2491 if ((AICE_SRST
!= srst
) && (AICE_RESET_HOLD
!= srst
))
2495 if (aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
,
2496 NDS_DBGER_CLEAR_ALL
) != ERROR_OK
)
2499 int result
= ERROR_OK
;
2500 if (AICE_SRST
== srst
)
2501 result
= aice_issue_srst();
2503 result
= aice_issue_reset_hold();
2505 /* Clear DBGER.CRST after reset to avoid 'core-reset checking' errors.
2506 * assert_srst is user-intentional reset behavior, so we could
2507 * clear DBGER.CRST safely.
2509 if (aice_write_misc(current_target_id
,
2510 NDS_EDM_MISC_DBGER
, NDS_DBGER_CRST
) != ERROR_OK
)
2516 static int aice_usb_run(void)
2518 LOG_DEBUG("aice_usb_run");
2520 uint32_t dbger_value
;
2521 if (aice_read_misc(current_target_id
,
2522 NDS_EDM_MISC_DBGER
, &dbger_value
) != ERROR_OK
)
2525 if ((dbger_value
& NDS_DBGER_DEX
) != NDS_DBGER_DEX
) {
2526 LOG_WARNING("<-- TARGET WARNING! The debug target exited "
2527 "the debug mode unexpectedly. -->");
2531 /* restore r0 & r1 before free run */
2532 aice_restore_tmp_registers();
2533 core_state
= AICE_TARGET_RUNNING
;
2536 aice_write_misc(current_target_id
, NDS_EDM_MISC_DBGER
,
2537 NDS_DBGER_CLEAR_ALL
);
2539 /** restore EDM registers */
2540 /** OpenOCD should restore EDM_CTL **before** to exit debug state.
2541 * Otherwise, following instruction will read wrong EDM_CTL value.
2543 * pc -> mfsr $p0, EDM_CTL (single step)
2547 aice_restore_edm_registers();
2549 /** execute instructions in DIM */
2550 uint32_t instructions
[4] = {
2556 int result
= aice_execute_dim(instructions
, 4);
2561 static int aice_usb_step(void)
2563 LOG_DEBUG("aice_usb_step");
2566 uint32_t ir0_reg_num
;
2568 if (is_v2_edm() == true)
2569 /* V2 EDM will push interrupt stack as debug exception */
2575 aice_read_reg(ir0_reg_num
, &ir0_value
);
2576 if ((ir0_value
& 0x800) == 0) {
2578 ir0_value
|= (0x01 << 11);
2579 aice_write_reg(ir0_reg_num
, ir0_value
);
2582 if (ERROR_FAIL
== aice_usb_run())
2586 enum aice_target_state_s state
;
2589 if (aice_usb_state(&state
) != ERROR_OK
)
2592 if (AICE_TARGET_HALTED
== state
)
2597 then
= timeval_ms();
2600 if ((timeval_ms() - then
) > 1000)
2601 LOG_WARNING("Timeout (1000ms) waiting for halt to complete");
2609 aice_read_reg(ir0_reg_num
, &ir0_value
);
2610 ir0_value
&= ~(0x01 << 11);
2611 aice_write_reg(ir0_reg_num
, ir0_value
);
2616 static int aice_usb_read_mem_b_bus(uint32_t address
, uint32_t *data
)
2618 return aice_read_mem_b(current_target_id
, address
, data
);
2621 static int aice_usb_read_mem_h_bus(uint32_t address
, uint32_t *data
)
2623 return aice_read_mem_h(current_target_id
, address
, data
);
2626 static int aice_usb_read_mem_w_bus(uint32_t address
, uint32_t *data
)
2628 return aice_read_mem(current_target_id
, address
, data
);
2631 static int aice_usb_read_mem_b_dim(uint32_t address
, uint32_t *data
)
2634 uint32_t instructions
[4] = {
2641 aice_execute_dim(instructions
, 4);
2643 aice_read_dtr(current_target_id
, &value
);
2644 *data
= value
& 0xFF;
2649 static int aice_usb_read_mem_h_dim(uint32_t address
, uint32_t *data
)
2652 uint32_t instructions
[4] = {
2659 aice_execute_dim(instructions
, 4);
2661 aice_read_dtr(current_target_id
, &value
);
2662 *data
= value
& 0xFFFF;
2667 static int aice_usb_read_mem_w_dim(uint32_t address
, uint32_t *data
)
2669 uint32_t instructions
[4] = {
2676 aice_execute_dim(instructions
, 4);
2678 aice_read_dtr(current_target_id
, data
);
2683 static int aice_usb_set_address_dim(uint32_t address
)
2685 uint32_t instructions
[4] = {
2686 SETHI(R0
, address
>> 12),
2687 ORI(R0
, R0
, address
& 0x00000FFF),
2692 return aice_execute_dim(instructions
, 4);
2695 static int aice_usb_read_memory_unit(uint32_t addr
, uint32_t size
,
2696 uint32_t count
, uint8_t *buffer
)
2698 LOG_DEBUG("aice_usb_read_memory_unit, addr: 0x%08x, size: %d, count: %d",
2701 if (NDS_MEMORY_ACC_CPU
== access_channel
)
2702 aice_usb_set_address_dim(addr
);
2706 read_mem_func_t read_mem_func
;
2710 if (NDS_MEMORY_ACC_BUS
== access_channel
)
2711 read_mem_func
= aice_usb_read_mem_b_bus
;
2713 read_mem_func
= aice_usb_read_mem_b_dim
;
2715 for (i
= 0; i
< count
; i
++) {
2716 read_mem_func(addr
, &value
);
2717 *buffer
++ = (uint8_t)value
;
2722 if (NDS_MEMORY_ACC_BUS
== access_channel
)
2723 read_mem_func
= aice_usb_read_mem_h_bus
;
2725 read_mem_func
= aice_usb_read_mem_h_dim
;
2727 for (i
= 0; i
< count
; i
++) {
2728 read_mem_func(addr
, &value
);
2729 uint16_t svalue
= value
;
2730 memcpy(buffer
, &svalue
, sizeof(uint16_t));
2736 if (NDS_MEMORY_ACC_BUS
== access_channel
)
2737 read_mem_func
= aice_usb_read_mem_w_bus
;
2739 read_mem_func
= aice_usb_read_mem_w_dim
;
2741 for (i
= 0; i
< count
; i
++) {
2742 read_mem_func(addr
, &value
);
2743 memcpy(buffer
, &value
, sizeof(uint32_t));
2753 static int aice_usb_write_mem_b_bus(uint32_t address
, uint32_t data
)
2755 return aice_write_mem_b(current_target_id
, address
, data
);
2758 static int aice_usb_write_mem_h_bus(uint32_t address
, uint32_t data
)
2760 return aice_write_mem_h(current_target_id
, address
, data
);
2763 static int aice_usb_write_mem_w_bus(uint32_t address
, uint32_t data
)
2765 return aice_write_mem(current_target_id
, address
, data
);
2768 static int aice_usb_write_mem_b_dim(uint32_t address
, uint32_t data
)
2770 uint32_t instructions
[4] = {
2777 aice_write_dtr(current_target_id
, data
& 0xFF);
2778 aice_execute_dim(instructions
, 4);
2783 static int aice_usb_write_mem_h_dim(uint32_t address
, uint32_t data
)
2785 uint32_t instructions
[4] = {
2792 aice_write_dtr(current_target_id
, data
& 0xFFFF);
2793 aice_execute_dim(instructions
, 4);
2798 static int aice_usb_write_mem_w_dim(uint32_t address
, uint32_t data
)
2800 uint32_t instructions
[4] = {
2807 aice_write_dtr(current_target_id
, data
);
2808 aice_execute_dim(instructions
, 4);
2813 static int aice_usb_write_memory_unit(uint32_t addr
, uint32_t size
,
2814 uint32_t count
, const uint8_t *buffer
)
2816 LOG_DEBUG("aice_usb_write_memory_unit, addr: 0x%08x, size: %d, count: %d",
2819 if (NDS_MEMORY_ACC_CPU
== access_channel
)
2820 aice_usb_set_address_dim(addr
);
2823 write_mem_func_t write_mem_func
;
2827 if (NDS_MEMORY_ACC_BUS
== access_channel
)
2828 write_mem_func
= aice_usb_write_mem_b_bus
;
2830 write_mem_func
= aice_usb_write_mem_b_dim
;
2832 for (i
= 0; i
< count
; i
++) {
2833 write_mem_func(addr
, *buffer
);
2839 if (NDS_MEMORY_ACC_BUS
== access_channel
)
2840 write_mem_func
= aice_usb_write_mem_h_bus
;
2842 write_mem_func
= aice_usb_write_mem_h_dim
;
2844 for (i
= 0; i
< count
; i
++) {
2846 memcpy(&value
, buffer
, sizeof(uint16_t));
2848 write_mem_func(addr
, value
);
2854 if (NDS_MEMORY_ACC_BUS
== access_channel
)
2855 write_mem_func
= aice_usb_write_mem_w_bus
;
2857 write_mem_func
= aice_usb_write_mem_w_dim
;
2859 for (i
= 0; i
< count
; i
++) {
2861 memcpy(&value
, buffer
, sizeof(uint32_t));
2863 write_mem_func(addr
, value
);
2873 static int aice_bulk_read_mem(uint32_t addr
, uint32_t count
, uint8_t *buffer
)
2875 uint32_t packet_size
;
2878 packet_size
= (count
>= 0x100) ? 0x100 : count
;
2882 if (aice_write_misc(current_target_id
, NDS_EDM_MISC_SBAR
, addr
) != ERROR_OK
)
2885 if (aice_fastread_mem(current_target_id
, buffer
,
2886 packet_size
) != ERROR_OK
)
2889 buffer
+= (packet_size
* 4);
2890 addr
+= (packet_size
* 4);
2891 count
-= packet_size
;
2897 static int aice_bulk_write_mem(uint32_t addr
, uint32_t count
, const uint8_t *buffer
)
2899 uint32_t packet_size
;
2902 packet_size
= (count
>= 0x100) ? 0x100 : count
;
2906 if (aice_write_misc(current_target_id
, NDS_EDM_MISC_SBAR
, addr
| 1) != ERROR_OK
)
2909 if (aice_fastwrite_mem(current_target_id
, buffer
,
2910 packet_size
) != ERROR_OK
)
2913 buffer
+= (packet_size
* 4);
2914 addr
+= (packet_size
* 4);
2915 count
-= packet_size
;
2921 static int aice_usb_bulk_read_mem(uint32_t addr
, uint32_t length
, uint8_t *buffer
)
2923 LOG_DEBUG("aice_usb_bulk_read_mem, addr: 0x%08x, length: 0x%08x", addr
, length
);
2927 if (NDS_MEMORY_ACC_CPU
== access_channel
)
2928 aice_usb_set_address_dim(addr
);
2930 if (NDS_MEMORY_ACC_CPU
== access_channel
)
2931 retval
= aice_usb_read_memory_unit(addr
, 4, length
/ 4, buffer
);
2933 retval
= aice_bulk_read_mem(addr
, length
/ 4, buffer
);
2938 static int aice_usb_bulk_write_mem(uint32_t addr
, uint32_t length
, const uint8_t *buffer
)
2940 LOG_DEBUG("aice_usb_bulk_write_mem, addr: 0x%08x, length: 0x%08x", addr
, length
);
2944 if (NDS_MEMORY_ACC_CPU
== access_channel
)
2945 aice_usb_set_address_dim(addr
);
2947 if (NDS_MEMORY_ACC_CPU
== access_channel
)
2948 retval
= aice_usb_write_memory_unit(addr
, 4, length
/ 4, buffer
);
2950 retval
= aice_bulk_write_mem(addr
, length
/ 4, buffer
);
2955 static int aice_usb_read_debug_reg(uint32_t addr
, uint32_t *val
)
2957 if (AICE_TARGET_HALTED
== core_state
) {
2958 if (NDS_EDM_SR_EDMSW
== addr
) {
2959 *val
= edmsw_backup
;
2960 } else if (NDS_EDM_SR_EDM_DTR
== addr
) {
2961 if (target_dtr_valid
) {
2962 /* if EDM_DTR has read out, clear it. */
2963 *val
= target_dtr_backup
;
2964 edmsw_backup
&= (~0x1);
2965 target_dtr_valid
= false;
2972 return aice_read_edmsr(current_target_id
, addr
, val
);
2975 static int aice_usb_write_debug_reg(uint32_t addr
, const uint32_t val
)
2977 if (AICE_TARGET_HALTED
== core_state
) {
2978 if (NDS_EDM_SR_EDM_DTR
== addr
) {
2979 host_dtr_backup
= val
;
2980 edmsw_backup
|= 0x2;
2981 host_dtr_valid
= true;
2985 return aice_write_edmsr(current_target_id
, addr
, val
);
2988 static int aice_usb_select_target(uint32_t target_id
)
2990 current_target_id
= target_id
;
2995 static int aice_usb_memory_access(enum nds_memory_access channel
)
2997 LOG_DEBUG("aice_usb_memory_access, access channel: %d", channel
);
2999 access_channel
= channel
;
3004 static int aice_usb_memory_mode(enum nds_memory_select mem_select
)
3006 if (memory_select
== mem_select
)
3009 LOG_DEBUG("aice_usb_memory_mode, memory select: %d", mem_select
);
3011 memory_select
= mem_select
;
3013 if (NDS_MEMORY_SELECT_AUTO
!= memory_select
)
3014 aice_write_misc(current_target_id
, NDS_EDM_MISC_ACC_CTL
,
3017 aice_write_misc(current_target_id
, NDS_EDM_MISC_ACC_CTL
,
3018 NDS_MEMORY_SELECT_MEM
- 1);
3023 static int aice_usb_read_tlb(uint32_t virtual_address
, uint32_t *physical_address
)
3025 LOG_DEBUG("aice_usb_read_tlb, virtual address: 0x%08x", virtual_address
);
3027 uint32_t instructions
[4];
3028 uint32_t probe_result
;
3031 uint32_t access_page_size
;
3032 uint32_t virtual_offset
;
3033 uint32_t physical_page_number
;
3035 aice_write_dtr(current_target_id
, virtual_address
);
3037 /* probe TLB first */
3038 instructions
[0] = MFSR_DTR(R0
);
3039 instructions
[1] = TLBOP_TARGET_PROBE(R1
, R0
);
3040 instructions
[2] = DSB
;
3041 instructions
[3] = BEQ_MINUS_12
;
3042 aice_execute_dim(instructions
, 4);
3044 aice_read_reg(R1
, &probe_result
);
3046 if (probe_result
& 0x80000000)
3049 /* read TLB entry */
3050 aice_write_dtr(current_target_id
, probe_result
& 0x7FF);
3052 /* probe TLB first */
3053 instructions
[0] = MFSR_DTR(R0
);
3054 instructions
[1] = TLBOP_TARGET_READ(R0
);
3055 instructions
[2] = DSB
;
3056 instructions
[3] = BEQ_MINUS_12
;
3057 aice_execute_dim(instructions
, 4);
3059 /* TODO: it should backup mr3, mr4 */
3060 aice_read_reg(MR3
, &value_mr3
);
3061 aice_read_reg(MR4
, &value_mr4
);
3063 access_page_size
= value_mr4
& 0xF;
3064 if (0 == access_page_size
) { /* 4K page */
3065 virtual_offset
= virtual_address
& 0x00000FFF;
3066 physical_page_number
= value_mr3
& 0xFFFFF000;
3067 } else if (1 == access_page_size
) { /* 8K page */
3068 virtual_offset
= virtual_address
& 0x00001FFF;
3069 physical_page_number
= value_mr3
& 0xFFFFE000;
3070 } else if (5 == access_page_size
) { /* 1M page */
3071 virtual_offset
= virtual_address
& 0x000FFFFF;
3072 physical_page_number
= value_mr3
& 0xFFF00000;
3077 *physical_address
= physical_page_number
| virtual_offset
;
3082 static int aice_usb_init_cache(void)
3084 LOG_DEBUG("aice_usb_init_cache");
3089 aice_read_reg(CR1
, &value_cr1
);
3090 aice_read_reg(CR2
, &value_cr2
);
3092 icache
.set
= value_cr1
& 0x7;
3093 icache
.log2_set
= icache
.set
+ 6;
3094 icache
.set
= 64 << icache
.set
;
3095 icache
.way
= ((value_cr1
>> 3) & 0x7) + 1;
3096 icache
.line_size
= (value_cr1
>> 6) & 0x7;
3097 if (icache
.line_size
!= 0) {
3098 icache
.log2_line_size
= icache
.line_size
+ 2;
3099 icache
.line_size
= 8 << (icache
.line_size
- 1);
3101 icache
.log2_line_size
= 0;
3104 LOG_DEBUG("\ticache set: %d, way: %d, line size: %d, "
3105 "log2(set): %d, log2(line_size): %d",
3106 icache
.set
, icache
.way
, icache
.line_size
,
3107 icache
.log2_set
, icache
.log2_line_size
);
3109 dcache
.set
= value_cr2
& 0x7;
3110 dcache
.log2_set
= dcache
.set
+ 6;
3111 dcache
.set
= 64 << dcache
.set
;
3112 dcache
.way
= ((value_cr2
>> 3) & 0x7) + 1;
3113 dcache
.line_size
= (value_cr2
>> 6) & 0x7;
3114 if (dcache
.line_size
!= 0) {
3115 dcache
.log2_line_size
= dcache
.line_size
+ 2;
3116 dcache
.line_size
= 8 << (dcache
.line_size
- 1);
3118 dcache
.log2_line_size
= 0;
3121 LOG_DEBUG("\tdcache set: %d, way: %d, line size: %d, "
3122 "log2(set): %d, log2(line_size): %d",
3123 dcache
.set
, dcache
.way
, dcache
.line_size
,
3124 dcache
.log2_set
, dcache
.log2_line_size
);
3131 static int aice_usb_dcache_inval_all(void)
3133 LOG_DEBUG("aice_usb_dcache_inval_all");
3137 uint32_t cache_index
;
3138 uint32_t instructions
[4];
3140 instructions
[0] = MFSR_DTR(R0
);
3141 instructions
[1] = L1D_IX_INVAL(R0
);
3142 instructions
[2] = DSB
;
3143 instructions
[3] = BEQ_MINUS_12
;
3145 for (set_index
= 0; set_index
< dcache
.set
; set_index
++) {
3146 for (way_index
= 0; way_index
< dcache
.way
; way_index
++) {
3147 cache_index
= (way_index
<< (dcache
.log2_set
+ dcache
.log2_line_size
)) |
3148 (set_index
<< dcache
.log2_line_size
);
3150 if (ERROR_OK
!= aice_write_dtr(current_target_id
, cache_index
))
3153 if (ERROR_OK
!= aice_execute_dim(instructions
, 4))
3161 static int aice_usb_dcache_va_inval(uint32_t address
)
3163 LOG_DEBUG("aice_usb_dcache_va_inval");
3165 uint32_t instructions
[4];
3167 aice_write_dtr(current_target_id
, address
);
3169 instructions
[0] = MFSR_DTR(R0
);
3170 instructions
[1] = L1D_VA_INVAL(R0
);
3171 instructions
[2] = DSB
;
3172 instructions
[3] = BEQ_MINUS_12
;
3174 return aice_execute_dim(instructions
, 4);
3177 static int aice_usb_dcache_wb_all(void)
3179 LOG_DEBUG("aice_usb_dcache_wb_all");
3183 uint32_t cache_index
;
3184 uint32_t instructions
[4];
3186 instructions
[0] = MFSR_DTR(R0
);
3187 instructions
[1] = L1D_IX_WB(R0
);
3188 instructions
[2] = DSB
;
3189 instructions
[3] = BEQ_MINUS_12
;
3191 for (set_index
= 0; set_index
< dcache
.set
; set_index
++) {
3192 for (way_index
= 0; way_index
< dcache
.way
; way_index
++) {
3193 cache_index
= (way_index
<< (dcache
.log2_set
+ dcache
.log2_line_size
)) |
3194 (set_index
<< dcache
.log2_line_size
);
3196 if (ERROR_OK
!= aice_write_dtr(current_target_id
, cache_index
))
3199 if (ERROR_OK
!= aice_execute_dim(instructions
, 4))
3207 static int aice_usb_dcache_va_wb(uint32_t address
)
3209 LOG_DEBUG("aice_usb_dcache_va_wb");
3211 uint32_t instructions
[4];
3213 aice_write_dtr(current_target_id
, address
);
3215 instructions
[0] = MFSR_DTR(R0
);
3216 instructions
[1] = L1D_VA_WB(R0
);
3217 instructions
[2] = DSB
;
3218 instructions
[3] = BEQ_MINUS_12
;
3220 return aice_execute_dim(instructions
, 4);
3223 static int aice_usb_icache_inval_all(void)
3225 LOG_DEBUG("aice_usb_icache_inval_all");
3229 uint32_t cache_index
;
3230 uint32_t instructions
[4];
3232 instructions
[0] = MFSR_DTR(R0
);
3233 instructions
[1] = L1I_IX_INVAL(R0
);
3234 instructions
[2] = ISB
;
3235 instructions
[3] = BEQ_MINUS_12
;
3237 for (set_index
= 0; set_index
< icache
.set
; set_index
++) {
3238 for (way_index
= 0; way_index
< icache
.way
; way_index
++) {
3239 cache_index
= (way_index
<< (icache
.log2_set
+ icache
.log2_line_size
)) |
3240 (set_index
<< icache
.log2_line_size
);
3242 if (ERROR_OK
!= aice_write_dtr(current_target_id
, cache_index
))
3245 if (ERROR_OK
!= aice_execute_dim(instructions
, 4))
3253 static int aice_usb_icache_va_inval(uint32_t address
)
3255 LOG_DEBUG("aice_usb_icache_va_inval");
3257 uint32_t instructions
[4];
3259 aice_write_dtr(current_target_id
, address
);
3261 instructions
[0] = MFSR_DTR(R0
);
3262 instructions
[1] = L1I_VA_INVAL(R0
);
3263 instructions
[2] = ISB
;
3264 instructions
[3] = BEQ_MINUS_12
;
3266 return aice_execute_dim(instructions
, 4);
3269 static int aice_usb_cache_ctl(uint32_t subtype
, uint32_t address
)
3271 LOG_DEBUG("aice_usb_cache_ctl");
3275 if (cache_init
== false)
3276 aice_usb_init_cache();
3279 case AICE_CACHE_CTL_L1D_INVALALL
:
3280 result
= aice_usb_dcache_inval_all();
3282 case AICE_CACHE_CTL_L1D_VA_INVAL
:
3283 result
= aice_usb_dcache_va_inval(address
);
3285 case AICE_CACHE_CTL_L1D_WBALL
:
3286 result
= aice_usb_dcache_wb_all();
3288 case AICE_CACHE_CTL_L1D_VA_WB
:
3289 result
= aice_usb_dcache_va_wb(address
);
3291 case AICE_CACHE_CTL_L1I_INVALALL
:
3292 result
= aice_usb_icache_inval_all();
3294 case AICE_CACHE_CTL_L1I_VA_INVAL
:
3295 result
= aice_usb_icache_va_inval(address
);
3298 result
= ERROR_FAIL
;
3305 static int aice_usb_set_retry_times(uint32_t a_retry_times
)
3307 aice_max_retry_times
= a_retry_times
;
3311 static int aice_usb_program_edm(char *command_sequence
)
3316 uint32_t data_value
;
3320 command_str
= strtok(command_sequence
, ";");
3321 if (command_str
== NULL
)
3326 /* process one command */
3327 while (command_str
[i
] == ' ' ||
3328 command_str
[i
] == '\n' ||
3329 command_str
[i
] == '\r' ||
3330 command_str
[i
] == '\t')
3333 /* skip ' ', '\r', '\n', '\t' */
3334 command_str
= command_str
+ i
;
3336 if (strncmp(command_str
, "write_misc", 10) == 0) {
3337 reg_name_0
= strstr(command_str
, "gen_port0");
3338 reg_name_1
= strstr(command_str
, "gen_port1");
3340 if (reg_name_0
!= NULL
) {
3341 data_value
= strtoul(reg_name_0
+ 9, NULL
, 0);
3343 if (aice_write_misc(current_target_id
,
3344 NDS_EDM_MISC_GEN_PORT0
, data_value
) != ERROR_OK
)
3347 } else if (reg_name_1
!= NULL
) {
3348 data_value
= strtoul(reg_name_1
+ 9, NULL
, 0);
3350 if (aice_write_misc(current_target_id
,
3351 NDS_EDM_MISC_GEN_PORT1
, data_value
) != ERROR_OK
)
3354 LOG_ERROR("program EDM, unsupported misc register: %s", command_str
);
3357 LOG_ERROR("program EDM, unsupported command: %s", command_str
);
3360 /* update command_str */
3361 command_str
= strtok(NULL
, ";");
3363 } while (command_str
!= NULL
);
3368 static int aice_usb_pack_command(bool enable_pack_command
)
3370 if (enable_pack_command
== false) {
3371 /* turn off usb_pack_command, flush usb_packets_buffer */
3372 aice_usb_packet_flush();
3375 usb_pack_command
= enable_pack_command
;
3380 static int aice_usb_execute(uint32_t *instructions
, uint32_t instruction_num
)
3383 uint8_t current_instruction_num
;
3384 uint32_t dim_instructions
[4] = {NOP
, NOP
, NOP
, BEQ_MINUS_12
};
3386 /* To execute 4 instructions as a special case */
3387 if (instruction_num
== 4)
3388 return aice_execute_dim(instructions
, 4);
3390 for (i
= 0 ; i
< instruction_num
; i
+= 3) {
3391 if (instruction_num
- i
< 3) {
3392 current_instruction_num
= instruction_num
- i
;
3393 for (j
= current_instruction_num
; j
< 3 ; j
++)
3394 dim_instructions
[j
] = NOP
;
3396 current_instruction_num
= 3;
3399 memcpy(dim_instructions
, instructions
+ i
,
3400 current_instruction_num
* sizeof(uint32_t));
3403 if (aice_write_dim(current_target_id
,
3408 /** clear DBGER.DPED */
3409 if (aice_write_misc(current_target_id
,
3410 NDS_EDM_MISC_DBGER
, NDS_DBGER_DPED
) != ERROR_OK
)
3414 if (aice_do_execute(current_target_id
) != ERROR_OK
)
3417 /** check DBGER.DPED */
3418 if (aice_check_dbger(NDS_DBGER_DPED
) != ERROR_OK
) {
3420 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly:"
3421 "0x%08x 0x%08x 0x%08x 0x%08x. -->",
3422 dim_instructions
[0],
3423 dim_instructions
[1],
3424 dim_instructions
[2],
3425 dim_instructions
[3]);
3433 static int aice_usb_set_custom_srst_script(const char *script
)
3435 custom_srst_script
= strdup(script
);
3440 static int aice_usb_set_custom_trst_script(const char *script
)
3442 custom_trst_script
= strdup(script
);
3447 static int aice_usb_set_custom_restart_script(const char *script
)
3449 custom_restart_script
= strdup(script
);
3454 static int aice_usb_set_count_to_check_dbger(uint32_t count_to_check
)
3456 aice_count_to_check_dbger
= count_to_check
;
3461 static int aice_usb_set_data_endian(enum aice_target_endian target_data_endian
)
3463 data_endian
= target_data_endian
;
3469 struct aice_port_api_s aice_usb_api
= {
3471 .open
= aice_open_device
,
3473 .close
= aice_usb_close
,
3475 .idcode
= aice_usb_idcode
,
3477 .state
= aice_usb_state
,
3479 .reset
= aice_usb_reset
,
3481 .assert_srst
= aice_usb_assert_srst
,
3483 .run
= aice_usb_run
,
3485 .halt
= aice_usb_halt
,
3487 .step
= aice_usb_step
,
3489 .read_reg
= aice_usb_read_reg
,
3491 .write_reg
= aice_usb_write_reg
,
3493 .read_reg_64
= aice_usb_read_reg_64
,
3495 .write_reg_64
= aice_usb_write_reg_64
,
3497 .read_mem_unit
= aice_usb_read_memory_unit
,
3499 .write_mem_unit
= aice_usb_write_memory_unit
,
3501 .read_mem_bulk
= aice_usb_bulk_read_mem
,
3503 .write_mem_bulk
= aice_usb_bulk_write_mem
,
3505 .read_debug_reg
= aice_usb_read_debug_reg
,
3507 .write_debug_reg
= aice_usb_write_debug_reg
,
3509 .set_jtag_clock
= aice_usb_set_jtag_clock
,
3511 .select_target
= aice_usb_select_target
,
3513 .memory_access
= aice_usb_memory_access
,
3515 .memory_mode
= aice_usb_memory_mode
,
3517 .read_tlb
= aice_usb_read_tlb
,
3519 .cache_ctl
= aice_usb_cache_ctl
,
3521 .set_retry_times
= aice_usb_set_retry_times
,
3523 .program_edm
= aice_usb_program_edm
,
3525 .pack_command
= aice_usb_pack_command
,
3527 .execute
= aice_usb_execute
,
3529 .set_custom_srst_script
= aice_usb_set_custom_srst_script
,
3531 .set_custom_trst_script
= aice_usb_set_custom_trst_script
,
3533 .set_custom_restart_script
= aice_usb_set_custom_restart_script
,
3535 .set_count_to_check_dbger
= aice_usb_set_count_to_check_dbger
,
3537 .set_data_endian
= aice_usb_set_data_endian
,