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[openocd.git] / src / jtag / aice / aice_usb.c
1 /***************************************************************************
2 * Copyright (C) 2013 by Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18 #ifdef HAVE_CONFIG_H
19 #include "config.h"
20 #endif
21
22 #include <jtag/drivers/libusb_common.h>
23 #include <helper/log.h>
24 #include <helper/time_support.h>
25 #include <target/target.h>
26 #include <jtag/jtag.h>
27 #include <target/nds32_insn.h>
28 #include <target/nds32_reg.h>
29 #include "aice_usb.h"
30
31
32 /* Global USB buffers */
33 static uint8_t usb_in_buffer[AICE_IN_BUFFER_SIZE];
34 static uint8_t usb_out_buffer[AICE_OUT_BUFFER_SIZE];
35 static uint32_t jtag_clock;
36 static struct aice_usb_handler_s aice_handler;
37 /* AICE max retry times. If AICE command timeout, retry it. */
38 static int aice_max_retry_times = 50;
39 /* Default endian is little endian. */
40 static enum aice_target_endian data_endian;
41
42 /* Constants for AICE command format length */
43 static const int32_t AICE_FORMAT_HTDA = 3;
44 static const int32_t AICE_FORMAT_HTDC = 7;
45 static const int32_t AICE_FORMAT_HTDMA = 4;
46 static const int32_t AICE_FORMAT_HTDMB = 8;
47 static const int32_t AICE_FORMAT_HTDMC = 8;
48 static const int32_t AICE_FORMAT_HTDMD = 12;
49 static const int32_t AICE_FORMAT_DTHA = 6;
50 static const int32_t AICE_FORMAT_DTHB = 2;
51 static const int32_t AICE_FORMAT_DTHMA = 8;
52 static const int32_t AICE_FORMAT_DTHMB = 4;
53
54 /* Constants for AICE command */
55 static const uint8_t AICE_CMD_SCAN_CHAIN = 0x00;
56 static const uint8_t AICE_CMD_T_READ_MISC = 0x20;
57 static const uint8_t AICE_CMD_T_READ_EDMSR = 0x21;
58 static const uint8_t AICE_CMD_T_READ_DTR = 0x22;
59 static const uint8_t AICE_CMD_T_READ_MEM_B = 0x24;
60 static const uint8_t AICE_CMD_T_READ_MEM_H = 0x25;
61 static const uint8_t AICE_CMD_T_READ_MEM = 0x26;
62 static const uint8_t AICE_CMD_T_FASTREAD_MEM = 0x27;
63 static const uint8_t AICE_CMD_T_WRITE_MISC = 0x28;
64 static const uint8_t AICE_CMD_T_WRITE_EDMSR = 0x29;
65 static const uint8_t AICE_CMD_T_WRITE_DTR = 0x2A;
66 static const uint8_t AICE_CMD_T_WRITE_DIM = 0x2B;
67 static const uint8_t AICE_CMD_T_WRITE_MEM_B = 0x2C;
68 static const uint8_t AICE_CMD_T_WRITE_MEM_H = 0x2D;
69 static const uint8_t AICE_CMD_T_WRITE_MEM = 0x2E;
70 static const uint8_t AICE_CMD_T_FASTWRITE_MEM = 0x2F;
71 static const uint8_t AICE_CMD_T_EXECUTE = 0x3E;
72 static const uint8_t AICE_CMD_READ_CTRL = 0x50;
73 static const uint8_t AICE_CMD_WRITE_CTRL = 0x51;
74 static const uint8_t AICE_CMD_BATCH_BUFFER_READ = 0x60;
75 static const uint8_t AICE_CMD_READ_DTR_TO_BUFFER = 0x61;
76 static const uint8_t AICE_CMD_BATCH_BUFFER_WRITE = 0x68;
77 static const uint8_t AICE_CMD_WRITE_DTR_FROM_BUFFER = 0x69;
78
79 /***************************************************************************/
80 /* AICE commands' pack/unpack functions */
81 static void aice_pack_htda(uint8_t cmd_code, uint8_t extra_word_length,
82 uint32_t address)
83 {
84 usb_out_buffer[0] = cmd_code;
85 usb_out_buffer[1] = extra_word_length;
86 usb_out_buffer[2] = (uint8_t)(address & 0xFF);
87 }
88
89 static void aice_pack_htdc(uint8_t cmd_code, uint8_t extra_word_length,
90 uint32_t address, uint32_t word, enum aice_target_endian access_endian)
91 {
92 usb_out_buffer[0] = cmd_code;
93 usb_out_buffer[1] = extra_word_length;
94 usb_out_buffer[2] = (uint8_t)(address & 0xFF);
95 if (access_endian == AICE_BIG_ENDIAN) {
96 usb_out_buffer[6] = (uint8_t)((word >> 24) & 0xFF);
97 usb_out_buffer[5] = (uint8_t)((word >> 16) & 0xFF);
98 usb_out_buffer[4] = (uint8_t)((word >> 8) & 0xFF);
99 usb_out_buffer[3] = (uint8_t)(word & 0xFF);
100 } else {
101 usb_out_buffer[3] = (uint8_t)((word >> 24) & 0xFF);
102 usb_out_buffer[4] = (uint8_t)((word >> 16) & 0xFF);
103 usb_out_buffer[5] = (uint8_t)((word >> 8) & 0xFF);
104 usb_out_buffer[6] = (uint8_t)(word & 0xFF);
105 }
106 }
107
108 static void aice_pack_htdma(uint8_t cmd_code, uint8_t target_id,
109 uint8_t extra_word_length, uint32_t address)
110 {
111 usb_out_buffer[0] = cmd_code;
112 usb_out_buffer[1] = target_id;
113 usb_out_buffer[2] = extra_word_length;
114 usb_out_buffer[3] = (uint8_t)(address & 0xFF);
115 }
116
117 static void aice_pack_htdmb(uint8_t cmd_code, uint8_t target_id,
118 uint8_t extra_word_length, uint32_t address)
119 {
120 usb_out_buffer[0] = cmd_code;
121 usb_out_buffer[1] = target_id;
122 usb_out_buffer[2] = extra_word_length;
123 usb_out_buffer[3] = 0;
124 usb_out_buffer[4] = (uint8_t)((address >> 24) & 0xFF);
125 usb_out_buffer[5] = (uint8_t)((address >> 16) & 0xFF);
126 usb_out_buffer[6] = (uint8_t)((address >> 8) & 0xFF);
127 usb_out_buffer[7] = (uint8_t)(address & 0xFF);
128 }
129
130 static void aice_pack_htdmc(uint8_t cmd_code, uint8_t target_id,
131 uint8_t extra_word_length, uint32_t address, uint32_t word,
132 enum aice_target_endian access_endian)
133 {
134 usb_out_buffer[0] = cmd_code;
135 usb_out_buffer[1] = target_id;
136 usb_out_buffer[2] = extra_word_length;
137 usb_out_buffer[3] = (uint8_t)(address & 0xFF);
138 if (access_endian == AICE_BIG_ENDIAN) {
139 usb_out_buffer[7] = (uint8_t)((word >> 24) & 0xFF);
140 usb_out_buffer[6] = (uint8_t)((word >> 16) & 0xFF);
141 usb_out_buffer[5] = (uint8_t)((word >> 8) & 0xFF);
142 usb_out_buffer[4] = (uint8_t)(word & 0xFF);
143 } else {
144 usb_out_buffer[4] = (uint8_t)((word >> 24) & 0xFF);
145 usb_out_buffer[5] = (uint8_t)((word >> 16) & 0xFF);
146 usb_out_buffer[6] = (uint8_t)((word >> 8) & 0xFF);
147 usb_out_buffer[7] = (uint8_t)(word & 0xFF);
148 }
149 }
150
151 static void aice_pack_htdmc_multiple_data(uint8_t cmd_code, uint8_t target_id,
152 uint8_t extra_word_length, uint32_t address, uint32_t *word,
153 uint8_t num_of_words, enum aice_target_endian access_endian)
154 {
155 usb_out_buffer[0] = cmd_code;
156 usb_out_buffer[1] = target_id;
157 usb_out_buffer[2] = extra_word_length;
158 usb_out_buffer[3] = (uint8_t)(address & 0xFF);
159
160 uint8_t i;
161 for (i = 0 ; i < num_of_words ; i++, word++) {
162 if (access_endian == AICE_BIG_ENDIAN) {
163 usb_out_buffer[7 + i * 4] = (uint8_t)((*word >> 24) & 0xFF);
164 usb_out_buffer[6 + i * 4] = (uint8_t)((*word >> 16) & 0xFF);
165 usb_out_buffer[5 + i * 4] = (uint8_t)((*word >> 8) & 0xFF);
166 usb_out_buffer[4 + i * 4] = (uint8_t)(*word & 0xFF);
167 } else {
168 usb_out_buffer[4 + i * 4] = (uint8_t)((*word >> 24) & 0xFF);
169 usb_out_buffer[5 + i * 4] = (uint8_t)((*word >> 16) & 0xFF);
170 usb_out_buffer[6 + i * 4] = (uint8_t)((*word >> 8) & 0xFF);
171 usb_out_buffer[7 + i * 4] = (uint8_t)(*word & 0xFF);
172 }
173 }
174 }
175
176 static void aice_pack_htdmd(uint8_t cmd_code, uint8_t target_id,
177 uint8_t extra_word_length, uint32_t address, uint32_t word,
178 enum aice_target_endian access_endian)
179 {
180 usb_out_buffer[0] = cmd_code;
181 usb_out_buffer[1] = target_id;
182 usb_out_buffer[2] = extra_word_length;
183 usb_out_buffer[3] = 0;
184 usb_out_buffer[4] = (uint8_t)((address >> 24) & 0xFF);
185 usb_out_buffer[5] = (uint8_t)((address >> 16) & 0xFF);
186 usb_out_buffer[6] = (uint8_t)((address >> 8) & 0xFF);
187 usb_out_buffer[7] = (uint8_t)(address & 0xFF);
188 if (access_endian == AICE_BIG_ENDIAN) {
189 usb_out_buffer[11] = (uint8_t)((word >> 24) & 0xFF);
190 usb_out_buffer[10] = (uint8_t)((word >> 16) & 0xFF);
191 usb_out_buffer[9] = (uint8_t)((word >> 8) & 0xFF);
192 usb_out_buffer[8] = (uint8_t)(word & 0xFF);
193 } else {
194 usb_out_buffer[8] = (uint8_t)((word >> 24) & 0xFF);
195 usb_out_buffer[9] = (uint8_t)((word >> 16) & 0xFF);
196 usb_out_buffer[10] = (uint8_t)((word >> 8) & 0xFF);
197 usb_out_buffer[11] = (uint8_t)(word & 0xFF);
198 }
199 }
200
201 static void aice_pack_htdmd_multiple_data(uint8_t cmd_code, uint8_t target_id,
202 uint8_t extra_word_length, uint32_t address, const uint8_t *word,
203 enum aice_target_endian access_endian)
204 {
205 usb_out_buffer[0] = cmd_code;
206 usb_out_buffer[1] = target_id;
207 usb_out_buffer[2] = extra_word_length;
208 usb_out_buffer[3] = 0;
209 usb_out_buffer[4] = (uint8_t)((address >> 24) & 0xFF);
210 usb_out_buffer[5] = (uint8_t)((address >> 16) & 0xFF);
211 usb_out_buffer[6] = (uint8_t)((address >> 8) & 0xFF);
212 usb_out_buffer[7] = (uint8_t)(address & 0xFF);
213
214 uint32_t i;
215 /* num_of_words may be over 0xFF, so use uint32_t */
216 uint32_t num_of_words = extra_word_length + 1;
217
218 for (i = 0 ; i < num_of_words ; i++, word += 4) {
219 if (access_endian == AICE_BIG_ENDIAN) {
220 usb_out_buffer[11 + i * 4] = word[3];
221 usb_out_buffer[10 + i * 4] = word[2];
222 usb_out_buffer[9 + i * 4] = word[1];
223 usb_out_buffer[8 + i * 4] = word[0];
224 } else {
225 usb_out_buffer[8 + i * 4] = word[3];
226 usb_out_buffer[9 + i * 4] = word[2];
227 usb_out_buffer[10 + i * 4] = word[1];
228 usb_out_buffer[11 + i * 4] = word[0];
229 }
230 }
231 }
232
233 static void aice_unpack_dtha(uint8_t *cmd_ack_code, uint8_t *extra_word_length,
234 uint32_t *word, enum aice_target_endian access_endian)
235 {
236 *cmd_ack_code = usb_in_buffer[0];
237 *extra_word_length = usb_in_buffer[1];
238
239 if (access_endian == AICE_BIG_ENDIAN) {
240 *word = (usb_in_buffer[5] << 24) |
241 (usb_in_buffer[4] << 16) |
242 (usb_in_buffer[3] << 8) |
243 (usb_in_buffer[2]);
244 } else {
245 *word = (usb_in_buffer[2] << 24) |
246 (usb_in_buffer[3] << 16) |
247 (usb_in_buffer[4] << 8) |
248 (usb_in_buffer[5]);
249 }
250 }
251
252 static void aice_unpack_dtha_multiple_data(uint8_t *cmd_ack_code,
253 uint8_t *extra_word_length, uint32_t *word, uint8_t num_of_words,
254 enum aice_target_endian access_endian)
255 {
256 *cmd_ack_code = usb_in_buffer[0];
257 *extra_word_length = usb_in_buffer[1];
258
259 uint8_t i;
260 for (i = 0 ; i < num_of_words ; i++, word++) {
261 if (access_endian == AICE_BIG_ENDIAN) {
262 *word = (usb_in_buffer[5 + i * 4] << 24) |
263 (usb_in_buffer[4 + i * 4] << 16) |
264 (usb_in_buffer[3 + i * 4] << 8) |
265 (usb_in_buffer[2 + i * 4]);
266 } else {
267 *word = (usb_in_buffer[2 + i * 4] << 24) |
268 (usb_in_buffer[3 + i * 4] << 16) |
269 (usb_in_buffer[4 + i * 4] << 8) |
270 (usb_in_buffer[5 + i * 4]);
271 }
272 }
273 }
274
275 static void aice_unpack_dthb(uint8_t *cmd_ack_code, uint8_t *extra_word_length)
276 {
277 *cmd_ack_code = usb_in_buffer[0];
278 *extra_word_length = usb_in_buffer[1];
279 }
280
281 static void aice_unpack_dthma(uint8_t *cmd_ack_code, uint8_t *target_id,
282 uint8_t *extra_word_length, uint32_t *word,
283 enum aice_target_endian access_endian)
284 {
285 *cmd_ack_code = usb_in_buffer[0];
286 *target_id = usb_in_buffer[1];
287 *extra_word_length = usb_in_buffer[2];
288 if (access_endian == AICE_BIG_ENDIAN) {
289 *word = (usb_in_buffer[7] << 24) |
290 (usb_in_buffer[6] << 16) |
291 (usb_in_buffer[5] << 8) |
292 (usb_in_buffer[4]);
293 } else {
294 *word = (usb_in_buffer[4] << 24) |
295 (usb_in_buffer[5] << 16) |
296 (usb_in_buffer[6] << 8) |
297 (usb_in_buffer[7]);
298 }
299 }
300
301 static void aice_unpack_dthma_multiple_data(uint8_t *cmd_ack_code,
302 uint8_t *target_id, uint8_t *extra_word_length, uint8_t *word,
303 enum aice_target_endian access_endian)
304 {
305 *cmd_ack_code = usb_in_buffer[0];
306 *target_id = usb_in_buffer[1];
307 *extra_word_length = usb_in_buffer[2];
308 if (access_endian == AICE_BIG_ENDIAN) {
309 word[0] = usb_in_buffer[4];
310 word[1] = usb_in_buffer[5];
311 word[2] = usb_in_buffer[6];
312 word[3] = usb_in_buffer[7];
313 } else {
314 word[0] = usb_in_buffer[7];
315 word[1] = usb_in_buffer[6];
316 word[2] = usb_in_buffer[5];
317 word[3] = usb_in_buffer[4];
318 }
319 word += 4;
320
321 uint8_t i;
322 for (i = 0; i < *extra_word_length; i++) {
323 if (access_endian == AICE_BIG_ENDIAN) {
324 word[0] = usb_in_buffer[8 + i * 4];
325 word[1] = usb_in_buffer[9 + i * 4];
326 word[2] = usb_in_buffer[10 + i * 4];
327 word[3] = usb_in_buffer[11 + i * 4];
328 } else {
329 word[0] = usb_in_buffer[11 + i * 4];
330 word[1] = usb_in_buffer[10 + i * 4];
331 word[2] = usb_in_buffer[9 + i * 4];
332 word[3] = usb_in_buffer[8 + i * 4];
333 }
334 word += 4;
335 }
336 }
337
338 static void aice_unpack_dthmb(uint8_t *cmd_ack_code, uint8_t *target_id,
339 uint8_t *extra_word_length)
340 {
341 *cmd_ack_code = usb_in_buffer[0];
342 *target_id = usb_in_buffer[1];
343 *extra_word_length = usb_in_buffer[2];
344 }
345
346 /***************************************************************************/
347 /* End of AICE commands' pack/unpack functions */
348
349 /* calls the given usb_bulk_* function, allowing for the data to
350 * trickle in with some timeouts */
351 static int usb_bulk_with_retries(
352 int (*f)(jtag_libusb_device_handle *, int, char *, int, int),
353 jtag_libusb_device_handle *dev, int ep,
354 char *bytes, int size, int timeout)
355 {
356 int tries = 3, count = 0;
357
358 while (tries && (count < size)) {
359 int result = f(dev, ep, bytes + count, size - count, timeout);
360 if (result > 0)
361 count += result;
362 else if ((-ETIMEDOUT != result) || !--tries)
363 return result;
364 }
365 return count;
366 }
367
368 static int wrap_usb_bulk_write(jtag_libusb_device_handle *dev, int ep,
369 char *buff, int size, int timeout)
370 {
371 /* usb_bulk_write() takes const char *buff */
372 return jtag_libusb_bulk_write(dev, ep, buff, size, timeout);
373 }
374
375 static inline int usb_bulk_write_ex(jtag_libusb_device_handle *dev, int ep,
376 char *bytes, int size, int timeout)
377 {
378 return usb_bulk_with_retries(&wrap_usb_bulk_write,
379 dev, ep, bytes, size, timeout);
380 }
381
382 static inline int usb_bulk_read_ex(jtag_libusb_device_handle *dev, int ep,
383 char *bytes, int size, int timeout)
384 {
385 return usb_bulk_with_retries(&jtag_libusb_bulk_read,
386 dev, ep, bytes, size, timeout);
387 }
388
389 /* Write data from out_buffer to USB. */
390 static int aice_usb_write(uint8_t *out_buffer, int out_length)
391 {
392 int result;
393
394 if (out_length > AICE_OUT_BUFFER_SIZE) {
395 LOG_ERROR("aice_write illegal out_length=%i (max=%i)",
396 out_length, AICE_OUT_BUFFER_SIZE);
397 return -1;
398 }
399
400 result = usb_bulk_write_ex(aice_handler.usb_handle, aice_handler.usb_write_ep,
401 (char *)out_buffer, out_length, AICE_USB_TIMEOUT);
402
403 LOG_DEBUG_IO("aice_usb_write, out_length = %i, result = %i",
404 out_length, result);
405
406 return result;
407 }
408
409 /* Read data from USB into in_buffer. */
410 static int aice_usb_read(uint8_t *in_buffer, int expected_size)
411 {
412 int32_t result = usb_bulk_read_ex(aice_handler.usb_handle, aice_handler.usb_read_ep,
413 (char *)in_buffer, expected_size, AICE_USB_TIMEOUT);
414
415 LOG_DEBUG_IO("aice_usb_read, result = %" PRId32, result);
416
417 return result;
418 }
419
420 static uint8_t usb_out_packets_buffer[AICE_OUT_PACKETS_BUFFER_SIZE];
421 static uint8_t usb_in_packets_buffer[AICE_IN_PACKETS_BUFFER_SIZE];
422 static uint32_t usb_out_packets_buffer_length;
423 static uint32_t usb_in_packets_buffer_length;
424 static enum aice_command_mode aice_command_mode;
425
426 static int aice_batch_buffer_write(uint8_t buf_index, const uint8_t *word,
427 uint32_t num_of_words);
428
429 static int aice_usb_packet_flush(void)
430 {
431 if (usb_out_packets_buffer_length == 0)
432 return 0;
433
434 if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
435 LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_PACK)");
436
437 if (aice_usb_write(usb_out_packets_buffer,
438 usb_out_packets_buffer_length) < 0)
439 return ERROR_FAIL;
440
441 if (aice_usb_read(usb_in_packets_buffer,
442 usb_in_packets_buffer_length) < 0)
443 return ERROR_FAIL;
444
445 usb_out_packets_buffer_length = 0;
446 usb_in_packets_buffer_length = 0;
447
448 } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
449 LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_BATCH)");
450
451 /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */
452 if (aice_batch_buffer_write(AICE_BATCH_COMMAND_BUFFER_0,
453 usb_out_packets_buffer,
454 (usb_out_packets_buffer_length + 3) / 4) != ERROR_OK)
455 return ERROR_FAIL;
456
457 usb_out_packets_buffer_length = 0;
458 usb_in_packets_buffer_length = 0;
459
460 /* enable BATCH command */
461 aice_command_mode = AICE_COMMAND_MODE_NORMAL;
462 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL, 0x80000000) != ERROR_OK)
463 return ERROR_FAIL;
464 aice_command_mode = AICE_COMMAND_MODE_BATCH;
465
466 /* wait 1 second (AICE bug, workaround) */
467 alive_sleep(1000);
468
469 /* check status */
470 uint32_t i;
471 uint32_t batch_status;
472
473 i = 0;
474 while (1) {
475 aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS, &batch_status);
476
477 if (batch_status & 0x1)
478 return ERROR_OK;
479 else if (batch_status & 0xE)
480 return ERROR_FAIL;
481
482 if ((i % 30) == 0)
483 keep_alive();
484
485 i++;
486 }
487 }
488
489 return ERROR_OK;
490 }
491
492 static int aice_usb_packet_append(uint8_t *out_buffer, int out_length, int in_length)
493 {
494 uint32_t max_packet_size = AICE_OUT_PACKETS_BUFFER_SIZE;
495
496 if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
497 max_packet_size = AICE_OUT_PACK_COMMAND_SIZE;
498 } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
499 max_packet_size = AICE_OUT_BATCH_COMMAND_SIZE;
500 } else {
501 /* AICE_COMMAND_MODE_NORMAL */
502 if (aice_usb_packet_flush() != ERROR_OK)
503 return ERROR_FAIL;
504 }
505
506 if (usb_out_packets_buffer_length + out_length > max_packet_size)
507 if (aice_usb_packet_flush() != ERROR_OK) {
508 LOG_DEBUG("Flush usb packets failed");
509 return ERROR_FAIL;
510 }
511
512 LOG_DEBUG("Append usb packets 0x%02x", out_buffer[0]);
513
514 memcpy(usb_out_packets_buffer + usb_out_packets_buffer_length, out_buffer, out_length);
515 usb_out_packets_buffer_length += out_length;
516 usb_in_packets_buffer_length += in_length;
517
518 return ERROR_OK;
519 }
520
521 /***************************************************************************/
522 /* AICE commands */
523 static int aice_reset_box(void)
524 {
525 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS, 0x1) != ERROR_OK)
526 return ERROR_FAIL;
527
528 /* turn off FASTMODE */
529 uint32_t pin_status;
530 if (aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS, &pin_status)
531 != ERROR_OK)
532 return ERROR_FAIL;
533
534 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS, pin_status & (~0x2))
535 != ERROR_OK)
536 return ERROR_FAIL;
537
538 return ERROR_OK;
539 }
540
541 static int aice_scan_chain(uint32_t *id_codes, uint8_t *num_of_ids)
542 {
543 int32_t result;
544 int retry_times = 0;
545
546 if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
547 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
548 aice_usb_packet_flush();
549
550 do {
551 aice_pack_htda(AICE_CMD_SCAN_CHAIN, 0x0F, 0x0);
552
553 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDA);
554
555 LOG_DEBUG("SCAN_CHAIN, length: 0x0F");
556
557 /** TODO: modify receive length */
558 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHA);
559 if (AICE_FORMAT_DTHA != result) {
560 LOG_ERROR("aice_usb_read failed (requested=%" PRIu32 ", result=%" PRId32 ")",
561 AICE_FORMAT_DTHA, result);
562 return ERROR_FAIL;
563 }
564
565 uint8_t cmd_ack_code;
566 aice_unpack_dtha_multiple_data(&cmd_ack_code, num_of_ids, id_codes,
567 0x10, AICE_LITTLE_ENDIAN);
568
569 if (cmd_ack_code != AICE_CMD_SCAN_CHAIN) {
570
571 if (retry_times > aice_max_retry_times) {
572 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
573 AICE_CMD_SCAN_CHAIN, cmd_ack_code);
574 return ERROR_FAIL;
575 }
576
577 /* clear timeout and retry */
578 if (aice_reset_box() != ERROR_OK)
579 return ERROR_FAIL;
580
581 retry_times++;
582 continue;
583 }
584
585 LOG_DEBUG("SCAN_CHAIN response, # of IDs: %" PRIu8, *num_of_ids);
586
587 if (*num_of_ids == 0xFF) {
588 LOG_ERROR("No target connected");
589 return ERROR_FAIL;
590 } else if (*num_of_ids == AICE_MAX_NUM_CORE) {
591 LOG_INFO("The ice chain over 16 targets");
592 } else {
593 (*num_of_ids)++;
594 }
595 break;
596 } while (1);
597
598 return ERROR_OK;
599 }
600
601 int aice_read_ctrl(uint32_t address, uint32_t *data)
602 {
603 int32_t result;
604
605 if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
606 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
607 aice_usb_packet_flush();
608
609 aice_pack_htda(AICE_CMD_READ_CTRL, 0, address);
610
611 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDA);
612
613 LOG_DEBUG("READ_CTRL, address: 0x%" PRIx32, address);
614
615 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHA);
616 if (AICE_FORMAT_DTHA != result) {
617 LOG_ERROR("aice_usb_read failed (requested=%" PRIu32 ", result=%" PRId32 ")",
618 AICE_FORMAT_DTHA, result);
619 return ERROR_FAIL;
620 }
621
622 uint8_t cmd_ack_code;
623 uint8_t extra_length;
624 aice_unpack_dtha(&cmd_ack_code, &extra_length, data, AICE_LITTLE_ENDIAN);
625
626 LOG_DEBUG("READ_CTRL response, data: 0x%" PRIx32, *data);
627
628 if (cmd_ack_code != AICE_CMD_READ_CTRL) {
629 LOG_ERROR("aice command error (command=0x%" PRIx32 ", response=0x%" PRIx8 ")",
630 (uint32_t)AICE_CMD_READ_CTRL, cmd_ack_code);
631 return ERROR_FAIL;
632 }
633
634 return ERROR_OK;
635 }
636
637 int aice_write_ctrl(uint32_t address, uint32_t data)
638 {
639 int32_t result;
640
641 if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
642 aice_usb_packet_flush();
643 } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
644 aice_pack_htdc(AICE_CMD_WRITE_CTRL, 0, address, data, AICE_LITTLE_ENDIAN);
645 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDC,
646 AICE_FORMAT_DTHB);
647 }
648
649 aice_pack_htdc(AICE_CMD_WRITE_CTRL, 0, address, data, AICE_LITTLE_ENDIAN);
650
651 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDC);
652
653 LOG_DEBUG("WRITE_CTRL, address: 0x%" PRIx32 ", data: 0x%" PRIx32, address, data);
654
655 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHB);
656 if (AICE_FORMAT_DTHB != result) {
657 LOG_ERROR("aice_usb_read failed (requested=%" PRIu32 ", result=%" PRId32 ")",
658 AICE_FORMAT_DTHB, result);
659 return ERROR_FAIL;
660 }
661
662 uint8_t cmd_ack_code;
663 uint8_t extra_length;
664 aice_unpack_dthb(&cmd_ack_code, &extra_length);
665
666 LOG_DEBUG("WRITE_CTRL response");
667
668 if (cmd_ack_code != AICE_CMD_WRITE_CTRL) {
669 LOG_ERROR("aice command error (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
670 AICE_CMD_WRITE_CTRL, cmd_ack_code);
671 return ERROR_FAIL;
672 }
673
674 return ERROR_OK;
675 }
676
677 int aice_read_dtr(uint8_t target_id, uint32_t *data)
678 {
679 int32_t result;
680 int retry_times = 0;
681
682 if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
683 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
684 aice_usb_packet_flush();
685
686 do {
687 aice_pack_htdma(AICE_CMD_T_READ_DTR, target_id, 0, 0);
688
689 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
690
691 LOG_DEBUG("READ_DTR, COREID: %" PRIu8, target_id);
692
693 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
694 if (AICE_FORMAT_DTHMA != result) {
695 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
696 AICE_FORMAT_DTHMA, result);
697 return ERROR_FAIL;
698 }
699
700 uint8_t cmd_ack_code;
701 uint8_t extra_length;
702 uint8_t res_target_id;
703 aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
704 data, AICE_LITTLE_ENDIAN);
705
706 if (cmd_ack_code == AICE_CMD_T_READ_DTR) {
707 LOG_DEBUG("READ_DTR response, data: 0x%" PRIx32, *data);
708 break;
709 } else {
710
711 if (retry_times > aice_max_retry_times) {
712 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
713 AICE_CMD_T_READ_DTR, cmd_ack_code);
714 return ERROR_FAIL;
715 }
716
717 /* clear timeout and retry */
718 if (aice_reset_box() != ERROR_OK)
719 return ERROR_FAIL;
720
721 retry_times++;
722 }
723 } while (1);
724
725 return ERROR_OK;
726 }
727
728 int aice_read_dtr_to_buffer(uint8_t target_id, uint32_t buffer_idx)
729 {
730 int32_t result;
731 int retry_times = 0;
732
733 if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
734 aice_usb_packet_flush();
735 } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
736 aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER, target_id, 0, buffer_idx);
737 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMA,
738 AICE_FORMAT_DTHMB);
739 }
740
741 do {
742 aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER, target_id, 0, buffer_idx);
743
744 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
745
746 LOG_DEBUG("READ_DTR_TO_BUFFER, COREID: %" PRIu8, target_id);
747
748 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
749 if (AICE_FORMAT_DTHMB != result) {
750 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")", AICE_FORMAT_DTHMB, result);
751 return ERROR_FAIL;
752 }
753
754 uint8_t cmd_ack_code;
755 uint8_t extra_length;
756 uint8_t res_target_id;
757 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
758
759 if (cmd_ack_code == AICE_CMD_READ_DTR_TO_BUFFER) {
760 break;
761 } else {
762 if (retry_times > aice_max_retry_times) {
763 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
764 AICE_CMD_READ_DTR_TO_BUFFER, cmd_ack_code);
765
766 return ERROR_FAIL;
767 }
768
769 /* clear timeout and retry */
770 if (aice_reset_box() != ERROR_OK)
771 return ERROR_FAIL;
772
773 retry_times++;
774 }
775 } while (1);
776
777 return ERROR_OK;
778 }
779
780 int aice_write_dtr(uint8_t target_id, uint32_t data)
781 {
782 int32_t result;
783 int retry_times = 0;
784
785 if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
786 aice_usb_packet_flush();
787 } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
788 aice_pack_htdmc(AICE_CMD_T_WRITE_DTR, target_id, 0, 0, data, AICE_LITTLE_ENDIAN);
789 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC,
790 AICE_FORMAT_DTHMB);
791 }
792
793 do {
794 aice_pack_htdmc(AICE_CMD_T_WRITE_DTR, target_id, 0, 0, data, AICE_LITTLE_ENDIAN);
795
796 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC);
797
798 LOG_DEBUG("WRITE_DTR, COREID: %" PRIu8 ", data: 0x%" PRIx32, target_id, data);
799
800 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
801 if (AICE_FORMAT_DTHMB != result) {
802 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")", AICE_FORMAT_DTHMB, result);
803 return ERROR_FAIL;
804 }
805
806 uint8_t cmd_ack_code;
807 uint8_t extra_length;
808 uint8_t res_target_id;
809 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
810
811 if (cmd_ack_code == AICE_CMD_T_WRITE_DTR) {
812 LOG_DEBUG("WRITE_DTR response");
813 break;
814 } else {
815 if (retry_times > aice_max_retry_times) {
816 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
817 AICE_CMD_T_WRITE_DTR, cmd_ack_code);
818
819 return ERROR_FAIL;
820 }
821
822 /* clear timeout and retry */
823 if (aice_reset_box() != ERROR_OK)
824 return ERROR_FAIL;
825
826 retry_times++;
827 }
828 } while (1);
829
830 return ERROR_OK;
831 }
832
833 int aice_write_dtr_from_buffer(uint8_t target_id, uint32_t buffer_idx)
834 {
835 int32_t result;
836 int retry_times = 0;
837
838 if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
839 aice_usb_packet_flush();
840 } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
841 aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER, target_id, 0, buffer_idx);
842 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMA,
843 AICE_FORMAT_DTHMB);
844 }
845
846 do {
847 aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER, target_id, 0, buffer_idx);
848
849 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
850
851 LOG_DEBUG("WRITE_DTR_FROM_BUFFER, COREID: %" PRIu8 "", target_id);
852
853 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
854 if (AICE_FORMAT_DTHMB != result) {
855 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")", AICE_FORMAT_DTHMB, result);
856 return ERROR_FAIL;
857 }
858
859 uint8_t cmd_ack_code;
860 uint8_t extra_length;
861 uint8_t res_target_id;
862 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
863
864 if (cmd_ack_code == AICE_CMD_WRITE_DTR_FROM_BUFFER) {
865 break;
866 } else {
867 if (retry_times > aice_max_retry_times) {
868 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
869 AICE_CMD_WRITE_DTR_FROM_BUFFER, cmd_ack_code);
870
871 return ERROR_FAIL;
872 }
873
874 /* clear timeout and retry */
875 if (aice_reset_box() != ERROR_OK)
876 return ERROR_FAIL;
877
878 retry_times++;
879 }
880 } while (1);
881
882 return ERROR_OK;
883 }
884
885 int aice_read_misc(uint8_t target_id, uint32_t address, uint32_t *data)
886 {
887 int32_t result;
888 int retry_times = 0;
889
890 if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
891 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
892 aice_usb_packet_flush();
893
894 do {
895 aice_pack_htdma(AICE_CMD_T_READ_MISC, target_id, 0, address);
896
897 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
898
899 LOG_DEBUG("READ_MISC, COREID: %" PRIu8 ", address: 0x%" PRIx32, target_id, address);
900
901 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
902 if (AICE_FORMAT_DTHMA != result) {
903 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
904 AICE_FORMAT_DTHMA, result);
905 return ERROR_AICE_DISCONNECT;
906 }
907
908 uint8_t cmd_ack_code;
909 uint8_t extra_length;
910 uint8_t res_target_id;
911 aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
912 data, AICE_LITTLE_ENDIAN);
913
914 if (cmd_ack_code == AICE_CMD_T_READ_MISC) {
915 LOG_DEBUG("READ_MISC response, data: 0x%" PRIx32, *data);
916 break;
917 } else {
918 if (retry_times > aice_max_retry_times) {
919 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
920 AICE_CMD_T_READ_MISC, cmd_ack_code);
921 return ERROR_FAIL;
922 }
923
924 /* clear timeout and retry */
925 if (aice_reset_box() != ERROR_OK)
926 return ERROR_FAIL;
927
928 retry_times++;
929 }
930 } while (1);
931
932 return ERROR_OK;
933 }
934
935 int aice_write_misc(uint8_t target_id, uint32_t address, uint32_t data)
936 {
937 int32_t result;
938 int retry_times = 0;
939
940 if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
941 aice_usb_packet_flush();
942 } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
943 aice_pack_htdmc(AICE_CMD_T_WRITE_MISC, target_id, 0, address, data,
944 AICE_LITTLE_ENDIAN);
945 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC,
946 AICE_FORMAT_DTHMB);
947 }
948
949 do {
950 aice_pack_htdmc(AICE_CMD_T_WRITE_MISC, target_id, 0, address,
951 data, AICE_LITTLE_ENDIAN);
952
953 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC);
954
955 LOG_DEBUG("WRITE_MISC, COREID: %" PRIu8 ", address: 0x%" PRIx32 ", data: 0x%" PRIx32,
956 target_id, address, data);
957
958 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
959 if (AICE_FORMAT_DTHMB != result) {
960 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
961 AICE_FORMAT_DTHMB, result);
962 return ERROR_FAIL;
963 }
964
965 uint8_t cmd_ack_code;
966 uint8_t extra_length;
967 uint8_t res_target_id;
968 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
969
970 if (cmd_ack_code == AICE_CMD_T_WRITE_MISC) {
971 LOG_DEBUG("WRITE_MISC response");
972 break;
973 } else {
974 if (retry_times > aice_max_retry_times) {
975 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
976 AICE_CMD_T_WRITE_MISC, cmd_ack_code);
977
978 return ERROR_FAIL;
979 }
980
981 /* clear timeout and retry */
982 if (aice_reset_box() != ERROR_OK)
983 return ERROR_FAIL;
984
985 retry_times++;
986 }
987 } while (1);
988
989 return ERROR_OK;
990 }
991
992 int aice_read_edmsr(uint8_t target_id, uint32_t address, uint32_t *data)
993 {
994 int32_t result;
995 int retry_times = 0;
996
997 if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
998 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
999 aice_usb_packet_flush();
1000
1001 do {
1002 aice_pack_htdma(AICE_CMD_T_READ_EDMSR, target_id, 0, address);
1003
1004 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
1005
1006 LOG_DEBUG("READ_EDMSR, COREID: %" PRIu8 ", address: 0x%" PRIx32, target_id, address);
1007
1008 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
1009 if (AICE_FORMAT_DTHMA != result) {
1010 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
1011 AICE_FORMAT_DTHMA, result);
1012 return ERROR_FAIL;
1013 }
1014
1015 uint8_t cmd_ack_code;
1016 uint8_t extra_length;
1017 uint8_t res_target_id;
1018 aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
1019 data, AICE_LITTLE_ENDIAN);
1020
1021 if (cmd_ack_code == AICE_CMD_T_READ_EDMSR) {
1022 LOG_DEBUG("READ_EDMSR response, data: 0x%" PRIx32, *data);
1023 break;
1024 } else {
1025 if (retry_times > aice_max_retry_times) {
1026 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1027 AICE_CMD_T_READ_EDMSR, cmd_ack_code);
1028
1029 return ERROR_FAIL;
1030 }
1031
1032 /* clear timeout and retry */
1033 if (aice_reset_box() != ERROR_OK)
1034 return ERROR_FAIL;
1035
1036 retry_times++;
1037 }
1038 } while (1);
1039
1040 return ERROR_OK;
1041 }
1042
1043 int aice_write_edmsr(uint8_t target_id, uint32_t address, uint32_t data)
1044 {
1045 int32_t result;
1046 int retry_times = 0;
1047
1048 if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
1049 aice_usb_packet_flush();
1050 } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
1051 aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR, target_id, 0, address, data,
1052 AICE_LITTLE_ENDIAN);
1053 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC,
1054 AICE_FORMAT_DTHMB);
1055 }
1056
1057 do {
1058 aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR, target_id, 0, address,
1059 data, AICE_LITTLE_ENDIAN);
1060
1061 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC);
1062
1063 LOG_DEBUG("WRITE_EDMSR, COREID: %" PRIu8 ", address: 0x%" PRIx32 ", data: 0x%" PRIx32,
1064 target_id, address, data);
1065
1066 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1067 if (AICE_FORMAT_DTHMB != result) {
1068 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
1069 AICE_FORMAT_DTHMB, result);
1070 return ERROR_FAIL;
1071 }
1072
1073 uint8_t cmd_ack_code;
1074 uint8_t extra_length;
1075 uint8_t res_target_id;
1076 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1077
1078 if (cmd_ack_code == AICE_CMD_T_WRITE_EDMSR) {
1079 LOG_DEBUG("WRITE_EDMSR response");
1080 break;
1081 } else {
1082 if (retry_times > aice_max_retry_times) {
1083 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1084 AICE_CMD_T_WRITE_EDMSR, cmd_ack_code);
1085
1086 return ERROR_FAIL;
1087 }
1088
1089 /* clear timeout and retry */
1090 if (aice_reset_box() != ERROR_OK)
1091 return ERROR_FAIL;
1092
1093 retry_times++;
1094 }
1095 } while (1);
1096
1097 return ERROR_OK;
1098 }
1099
1100 static int aice_switch_to_big_endian(uint32_t *word, uint8_t num_of_words)
1101 {
1102 uint32_t tmp;
1103
1104 for (uint8_t i = 0 ; i < num_of_words ; i++) {
1105 tmp = ((word[i] >> 24) & 0x000000FF) |
1106 ((word[i] >> 8) & 0x0000FF00) |
1107 ((word[i] << 8) & 0x00FF0000) |
1108 ((word[i] << 24) & 0xFF000000);
1109 word[i] = tmp;
1110 }
1111
1112 return ERROR_OK;
1113 }
1114
1115 static int aice_write_dim(uint8_t target_id, uint32_t *word, uint8_t num_of_words)
1116 {
1117 int32_t result;
1118 uint32_t big_endian_word[4];
1119 int retry_times = 0;
1120
1121 /** instruction is big-endian */
1122 memcpy(big_endian_word, word, sizeof(big_endian_word));
1123 aice_switch_to_big_endian(big_endian_word, num_of_words);
1124
1125 if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
1126 aice_usb_packet_flush();
1127 } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
1128 aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM, target_id,
1129 num_of_words - 1, 0, big_endian_word, num_of_words,
1130 AICE_LITTLE_ENDIAN);
1131 return aice_usb_packet_append(usb_out_buffer,
1132 AICE_FORMAT_HTDMC + (num_of_words - 1) * 4,
1133 AICE_FORMAT_DTHMB);
1134 }
1135
1136 do {
1137 aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM, target_id, num_of_words - 1, 0,
1138 big_endian_word, num_of_words, AICE_LITTLE_ENDIAN);
1139
1140 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC + (num_of_words - 1) * 4);
1141
1142 LOG_DEBUG("WRITE_DIM, COREID: %" PRIu8
1143 ", data: 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32,
1144 target_id,
1145 big_endian_word[0],
1146 big_endian_word[1],
1147 big_endian_word[2],
1148 big_endian_word[3]);
1149
1150 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1151 if (AICE_FORMAT_DTHMB != result) {
1152 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")", AICE_FORMAT_DTHMB, result);
1153 return ERROR_FAIL;
1154 }
1155
1156 uint8_t cmd_ack_code;
1157 uint8_t extra_length;
1158 uint8_t res_target_id;
1159 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1160
1161
1162 if (cmd_ack_code == AICE_CMD_T_WRITE_DIM) {
1163 LOG_DEBUG("WRITE_DIM response");
1164 break;
1165 } else {
1166 if (retry_times > aice_max_retry_times) {
1167 LOG_ERROR("aice command timeout (command=0x%" PRIx8
1168 ", response=0x%" PRIx8 ")",
1169 AICE_CMD_T_WRITE_DIM, cmd_ack_code);
1170
1171 return ERROR_FAIL;
1172 }
1173
1174 /* clear timeout and retry */
1175 if (aice_reset_box() != ERROR_OK)
1176 return ERROR_FAIL;
1177
1178 retry_times++;
1179 }
1180 } while (1);
1181
1182 return ERROR_OK;
1183 }
1184
1185 static int aice_do_execute(uint8_t target_id)
1186 {
1187 int32_t result;
1188 int retry_times = 0;
1189
1190 if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
1191 aice_usb_packet_flush();
1192 } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
1193 aice_pack_htdmc(AICE_CMD_T_EXECUTE, target_id, 0, 0, 0, AICE_LITTLE_ENDIAN);
1194 return aice_usb_packet_append(usb_out_buffer,
1195 AICE_FORMAT_HTDMC,
1196 AICE_FORMAT_DTHMB);
1197 }
1198
1199 do {
1200 aice_pack_htdmc(AICE_CMD_T_EXECUTE, target_id, 0, 0, 0, AICE_LITTLE_ENDIAN);
1201
1202 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC);
1203
1204 LOG_DEBUG("EXECUTE, COREID: %" PRIu8 "", target_id);
1205
1206 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1207 if (AICE_FORMAT_DTHMB != result) {
1208 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
1209 AICE_FORMAT_DTHMB, result);
1210 return ERROR_FAIL;
1211 }
1212
1213 uint8_t cmd_ack_code;
1214 uint8_t extra_length;
1215 uint8_t res_target_id;
1216 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1217
1218 if (cmd_ack_code == AICE_CMD_T_EXECUTE) {
1219 LOG_DEBUG("EXECUTE response");
1220 break;
1221 } else {
1222 if (retry_times > aice_max_retry_times) {
1223 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1224 AICE_CMD_T_EXECUTE, cmd_ack_code);
1225
1226 return ERROR_FAIL;
1227 }
1228
1229 /* clear timeout and retry */
1230 if (aice_reset_box() != ERROR_OK)
1231 return ERROR_FAIL;
1232
1233 retry_times++;
1234 }
1235 } while (1);
1236
1237 return ERROR_OK;
1238 }
1239
1240 int aice_write_mem_b(uint8_t target_id, uint32_t address, uint32_t data)
1241 {
1242 int32_t result;
1243 int retry_times = 0;
1244
1245 LOG_DEBUG("WRITE_MEM_B, COREID: %" PRIu8 ", ADDRESS %08" PRIx32 " VALUE %08" PRIx32,
1246 target_id,
1247 address,
1248 data);
1249
1250 if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1251 (AICE_COMMAND_MODE_BATCH == aice_command_mode)) {
1252 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B, target_id, 0, address,
1253 data & 0x000000FF, data_endian);
1254 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD,
1255 AICE_FORMAT_DTHMB);
1256 } else {
1257 do {
1258 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B, target_id, 0,
1259 address, data & 0x000000FF, data_endian);
1260 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD);
1261
1262 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1263 if (AICE_FORMAT_DTHMB != result) {
1264 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
1265 ", result=%" PRId32 ")", AICE_FORMAT_DTHMB, result);
1266 return ERROR_FAIL;
1267 }
1268
1269 uint8_t cmd_ack_code;
1270 uint8_t extra_length;
1271 uint8_t res_target_id;
1272 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1273
1274 if (cmd_ack_code == AICE_CMD_T_WRITE_MEM_B) {
1275 break;
1276 } else {
1277 if (retry_times > aice_max_retry_times) {
1278 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1279 AICE_CMD_T_WRITE_MEM_B, cmd_ack_code);
1280
1281 return ERROR_FAIL;
1282 }
1283
1284 /* clear timeout and retry */
1285 if (aice_reset_box() != ERROR_OK)
1286 return ERROR_FAIL;
1287
1288 retry_times++;
1289 }
1290 } while (1);
1291 }
1292
1293 return ERROR_OK;
1294 }
1295
1296 int aice_write_mem_h(uint8_t target_id, uint32_t address, uint32_t data)
1297 {
1298 int32_t result;
1299 int retry_times = 0;
1300
1301 LOG_DEBUG("WRITE_MEM_H, COREID: %" PRIu8 ", ADDRESS %08" PRIx32 " VALUE %08" PRIx32,
1302 target_id,
1303 address,
1304 data);
1305
1306 if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1307 (AICE_COMMAND_MODE_BATCH == aice_command_mode)) {
1308 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H, target_id, 0,
1309 (address >> 1) & 0x7FFFFFFF, data & 0x0000FFFF, data_endian);
1310 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD,
1311 AICE_FORMAT_DTHMB);
1312 } else {
1313 do {
1314 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H, target_id, 0,
1315 (address >> 1) & 0x7FFFFFFF, data & 0x0000FFFF, data_endian);
1316 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD);
1317
1318 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1319 if (AICE_FORMAT_DTHMB != result) {
1320 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
1321 AICE_FORMAT_DTHMB, result);
1322 return ERROR_FAIL;
1323 }
1324
1325 uint8_t cmd_ack_code;
1326 uint8_t extra_length;
1327 uint8_t res_target_id;
1328 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1329
1330 if (cmd_ack_code == AICE_CMD_T_WRITE_MEM_H) {
1331 break;
1332 } else {
1333 if (retry_times > aice_max_retry_times) {
1334 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1335 AICE_CMD_T_WRITE_MEM_H, cmd_ack_code);
1336
1337 return ERROR_FAIL;
1338 }
1339
1340 /* clear timeout and retry */
1341 if (aice_reset_box() != ERROR_OK)
1342 return ERROR_FAIL;
1343
1344 retry_times++;
1345 }
1346 } while (1);
1347 }
1348
1349 return ERROR_OK;
1350 }
1351
1352 int aice_write_mem(uint8_t target_id, uint32_t address, uint32_t data)
1353 {
1354 int32_t result;
1355 int retry_times = 0;
1356
1357 LOG_DEBUG("WRITE_MEM, COREID: %" PRIu8 ", ADDRESS %08" PRIx32 " VALUE %08" PRIx32,
1358 target_id,
1359 address,
1360 data);
1361
1362 if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1363 (AICE_COMMAND_MODE_BATCH == aice_command_mode)) {
1364 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM, target_id, 0,
1365 (address >> 2) & 0x3FFFFFFF, data, data_endian);
1366 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD,
1367 AICE_FORMAT_DTHMB);
1368 } else {
1369 do {
1370 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM, target_id, 0,
1371 (address >> 2) & 0x3FFFFFFF, data, data_endian);
1372 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD);
1373
1374 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1375 if (AICE_FORMAT_DTHMB != result) {
1376 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
1377 AICE_FORMAT_DTHMB, result);
1378 return ERROR_FAIL;
1379 }
1380
1381 uint8_t cmd_ack_code;
1382 uint8_t extra_length;
1383 uint8_t res_target_id;
1384 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1385
1386 if (cmd_ack_code == AICE_CMD_T_WRITE_MEM) {
1387 break;
1388 } else {
1389 if (retry_times > aice_max_retry_times) {
1390 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1391 AICE_CMD_T_WRITE_MEM, cmd_ack_code);
1392
1393 return ERROR_FAIL;
1394 }
1395
1396 /* clear timeout and retry */
1397 if (aice_reset_box() != ERROR_OK)
1398 return ERROR_FAIL;
1399
1400 retry_times++;
1401 }
1402 } while (1);
1403 }
1404
1405 return ERROR_OK;
1406 }
1407
1408 int aice_fastread_mem(uint8_t target_id, uint8_t *word, uint32_t num_of_words)
1409 {
1410 int32_t result;
1411 int retry_times = 0;
1412
1413 if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1414 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
1415 aice_usb_packet_flush();
1416
1417 do {
1418 aice_pack_htdmb(AICE_CMD_T_FASTREAD_MEM, target_id, num_of_words - 1, 0);
1419
1420 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB);
1421
1422 LOG_DEBUG("FASTREAD_MEM, COREID: %" PRIu8 ", # of DATA %08" PRIx32,
1423 target_id, num_of_words);
1424
1425 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA + (num_of_words - 1) * 4);
1426 if (result < 0) {
1427 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
1428 AICE_FORMAT_DTHMA + (num_of_words - 1) * 4, result);
1429 return ERROR_FAIL;
1430 }
1431
1432 uint8_t cmd_ack_code;
1433 uint8_t extra_length;
1434 uint8_t res_target_id;
1435 aice_unpack_dthma_multiple_data(&cmd_ack_code, &res_target_id,
1436 &extra_length, word, data_endian);
1437
1438 if (cmd_ack_code == AICE_CMD_T_FASTREAD_MEM) {
1439 break;
1440 } else {
1441 if (retry_times > aice_max_retry_times) {
1442 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1443 AICE_CMD_T_FASTREAD_MEM, cmd_ack_code);
1444
1445 return ERROR_FAIL;
1446 }
1447
1448 /* clear timeout and retry */
1449 if (aice_reset_box() != ERROR_OK)
1450 return ERROR_FAIL;
1451
1452 retry_times++;
1453 }
1454 } while (1);
1455
1456 return ERROR_OK;
1457 }
1458
1459 int aice_fastwrite_mem(uint8_t target_id, const uint8_t *word, uint32_t num_of_words)
1460 {
1461 int32_t result;
1462 int retry_times = 0;
1463
1464 if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
1465 aice_usb_packet_flush();
1466 } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
1467 aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM, target_id,
1468 num_of_words - 1, 0, word, data_endian);
1469 return aice_usb_packet_append(usb_out_buffer,
1470 AICE_FORMAT_HTDMD + (num_of_words - 1) * 4,
1471 AICE_FORMAT_DTHMB);
1472 }
1473
1474 do {
1475 aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM, target_id,
1476 num_of_words - 1, 0, word, data_endian);
1477
1478 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD + (num_of_words - 1) * 4);
1479
1480 LOG_DEBUG("FASTWRITE_MEM, COREID: %" PRIu8 ", # of DATA %08" PRIx32,
1481 target_id, num_of_words);
1482
1483 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1484 if (AICE_FORMAT_DTHMB != result) {
1485 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
1486 AICE_FORMAT_DTHMB, result);
1487 return ERROR_FAIL;
1488 }
1489
1490 uint8_t cmd_ack_code;
1491 uint8_t extra_length;
1492 uint8_t res_target_id;
1493 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1494
1495 if (cmd_ack_code == AICE_CMD_T_FASTWRITE_MEM) {
1496 break;
1497 } else {
1498 if (retry_times > aice_max_retry_times) {
1499 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1500 AICE_CMD_T_FASTWRITE_MEM, cmd_ack_code);
1501
1502 return ERROR_FAIL;
1503 }
1504
1505 /* clear timeout and retry */
1506 if (aice_reset_box() != ERROR_OK)
1507 return ERROR_FAIL;
1508
1509 retry_times++;
1510 }
1511 } while (1);
1512
1513 return ERROR_OK;
1514 }
1515
1516 int aice_read_mem_b(uint8_t target_id, uint32_t address, uint32_t *data)
1517 {
1518 int32_t result;
1519 int retry_times = 0;
1520
1521 if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1522 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
1523 aice_usb_packet_flush();
1524
1525 do {
1526 aice_pack_htdmb(AICE_CMD_T_READ_MEM_B, target_id, 0, address);
1527
1528 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB);
1529
1530 LOG_DEBUG("READ_MEM_B, COREID: %" PRIu8 "", target_id);
1531
1532 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
1533 if (AICE_FORMAT_DTHMA != result) {
1534 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
1535 AICE_FORMAT_DTHMA, result);
1536 return ERROR_FAIL;
1537 }
1538
1539 uint8_t cmd_ack_code;
1540 uint8_t extra_length;
1541 uint8_t res_target_id;
1542 aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
1543 data, data_endian);
1544
1545 if (cmd_ack_code == AICE_CMD_T_READ_MEM_B) {
1546 LOG_DEBUG("READ_MEM_B response, data: 0x%02" PRIx32, *data);
1547 break;
1548 } else {
1549 if (retry_times > aice_max_retry_times) {
1550 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1551 AICE_CMD_T_READ_MEM_B, cmd_ack_code);
1552
1553 return ERROR_FAIL;
1554 }
1555
1556 /* clear timeout and retry */
1557 if (aice_reset_box() != ERROR_OK)
1558 return ERROR_FAIL;
1559
1560 retry_times++;
1561 }
1562 } while (1);
1563
1564 return ERROR_OK;
1565 }
1566
1567 int aice_read_mem_h(uint8_t target_id, uint32_t address, uint32_t *data)
1568 {
1569 int32_t result;
1570 int retry_times = 0;
1571
1572 if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1573 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
1574 aice_usb_packet_flush();
1575
1576 do {
1577 aice_pack_htdmb(AICE_CMD_T_READ_MEM_H, target_id, 0, (address >> 1) & 0x7FFFFFFF);
1578
1579 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB);
1580
1581 LOG_DEBUG("READ_MEM_H, CORE_ID: %" PRIu8 "", target_id);
1582
1583 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
1584 if (AICE_FORMAT_DTHMA != result) {
1585 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
1586 AICE_FORMAT_DTHMA, result);
1587 return ERROR_FAIL;
1588 }
1589
1590 uint8_t cmd_ack_code;
1591 uint8_t extra_length;
1592 uint8_t res_target_id;
1593 aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
1594 data, data_endian);
1595
1596 if (cmd_ack_code == AICE_CMD_T_READ_MEM_H) {
1597 LOG_DEBUG("READ_MEM_H response, data: 0x%" PRIx32, *data);
1598 break;
1599 } else {
1600 if (retry_times > aice_max_retry_times) {
1601 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1602 AICE_CMD_T_READ_MEM_H, cmd_ack_code);
1603
1604 return ERROR_FAIL;
1605 }
1606
1607 /* clear timeout and retry */
1608 if (aice_reset_box() != ERROR_OK)
1609 return ERROR_FAIL;
1610
1611 retry_times++;
1612 }
1613 } while (1);
1614
1615 return ERROR_OK;
1616 }
1617
1618 int aice_read_mem(uint8_t target_id, uint32_t address, uint32_t *data)
1619 {
1620 int32_t result;
1621 int retry_times = 0;
1622
1623 if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1624 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
1625 aice_usb_packet_flush();
1626
1627 do {
1628 aice_pack_htdmb(AICE_CMD_T_READ_MEM, target_id, 0,
1629 (address >> 2) & 0x3FFFFFFF);
1630
1631 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB);
1632
1633 LOG_DEBUG("READ_MEM, COREID: %" PRIu8 "", target_id);
1634
1635 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
1636 if (AICE_FORMAT_DTHMA != result) {
1637 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
1638 AICE_FORMAT_DTHMA, result);
1639 return ERROR_FAIL;
1640 }
1641
1642 uint8_t cmd_ack_code;
1643 uint8_t extra_length;
1644 uint8_t res_target_id;
1645 aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
1646 data, data_endian);
1647
1648 if (cmd_ack_code == AICE_CMD_T_READ_MEM) {
1649 LOG_DEBUG("READ_MEM response, data: 0x%" PRIx32, *data);
1650 break;
1651 } else {
1652 if (retry_times > aice_max_retry_times) {
1653 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1654 AICE_CMD_T_READ_MEM, cmd_ack_code);
1655
1656 return ERROR_FAIL;
1657 }
1658
1659 /* clear timeout and retry */
1660 if (aice_reset_box() != ERROR_OK)
1661 return ERROR_FAIL;
1662
1663 retry_times++;
1664 }
1665 } while (1);
1666
1667 return ERROR_OK;
1668 }
1669
1670 int aice_batch_buffer_read(uint8_t buf_index, uint32_t *word, uint32_t num_of_words)
1671 {
1672 int32_t result;
1673 int retry_times = 0;
1674
1675 do {
1676 aice_pack_htdma(AICE_CMD_BATCH_BUFFER_READ, 0, num_of_words - 1, buf_index);
1677
1678 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
1679
1680 LOG_DEBUG("BATCH_BUFFER_READ, # of DATA %08" PRIx32, num_of_words);
1681
1682 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA + (num_of_words - 1) * 4);
1683 if (result < 0) {
1684 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
1685 AICE_FORMAT_DTHMA + (num_of_words - 1) * 4, result);
1686 return ERROR_FAIL;
1687 }
1688
1689 uint8_t cmd_ack_code;
1690 uint8_t extra_length;
1691 uint8_t res_target_id;
1692 aice_unpack_dthma_multiple_data(&cmd_ack_code, &res_target_id,
1693 &extra_length, (uint8_t *)word, data_endian);
1694
1695 if (cmd_ack_code == AICE_CMD_BATCH_BUFFER_READ) {
1696 break;
1697 } else {
1698 if (retry_times > aice_max_retry_times) {
1699 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1700 AICE_CMD_BATCH_BUFFER_READ, cmd_ack_code);
1701
1702 return ERROR_FAIL;
1703 }
1704
1705 /* clear timeout and retry */
1706 if (aice_reset_box() != ERROR_OK)
1707 return ERROR_FAIL;
1708
1709 retry_times++;
1710 }
1711 } while (1);
1712
1713 return ERROR_OK;
1714 }
1715
1716 int aice_batch_buffer_write(uint8_t buf_index, const uint8_t *word, uint32_t num_of_words)
1717 {
1718 int32_t result;
1719 int retry_times = 0;
1720
1721 if (num_of_words == 0)
1722 return ERROR_OK;
1723
1724 do {
1725 /* only pack AICE_CMD_BATCH_BUFFER_WRITE command header */
1726 aice_pack_htdmc(AICE_CMD_BATCH_BUFFER_WRITE, 0, num_of_words - 1, buf_index,
1727 0, data_endian);
1728
1729 /* use append instead of pack */
1730 memcpy(usb_out_buffer + 4, word, num_of_words * 4);
1731
1732 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC + (num_of_words - 1) * 4);
1733
1734 LOG_DEBUG("BATCH_BUFFER_WRITE, # of DATA %08" PRIx32, num_of_words);
1735
1736 result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1737 if (AICE_FORMAT_DTHMB != result) {
1738 LOG_ERROR("aice_usb_read failed (requested=%" PRId32 ", result=%" PRId32 ")",
1739 AICE_FORMAT_DTHMB, result);
1740 return ERROR_FAIL;
1741 }
1742
1743 uint8_t cmd_ack_code;
1744 uint8_t extra_length;
1745 uint8_t res_target_id;
1746 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1747
1748 if (cmd_ack_code == AICE_CMD_BATCH_BUFFER_WRITE) {
1749 break;
1750 } else {
1751 if (retry_times > aice_max_retry_times) {
1752 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1753 AICE_CMD_BATCH_BUFFER_WRITE, cmd_ack_code);
1754
1755 return ERROR_FAIL;
1756 }
1757
1758 /* clear timeout and retry */
1759 if (aice_reset_box() != ERROR_OK)
1760 return ERROR_FAIL;
1761
1762 retry_times++;
1763 }
1764 } while (1);
1765
1766 return ERROR_OK;
1767 }
1768
1769 /***************************************************************************/
1770 /* End of AICE commands */
1771
1772 typedef int (*read_mem_func_t)(uint32_t coreid, uint32_t address, uint32_t *data);
1773 typedef int (*write_mem_func_t)(uint32_t coreid, uint32_t address, uint32_t data);
1774
1775 struct aice_nds32_info core_info[AICE_MAX_NUM_CORE];
1776 static uint8_t total_num_of_core;
1777
1778 static char *custom_srst_script;
1779 static char *custom_trst_script;
1780 static char *custom_restart_script;
1781 static uint32_t aice_count_to_check_dbger = 30;
1782
1783 static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val);
1784 static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val);
1785
1786 static int check_suppressed_exception(uint32_t coreid, uint32_t dbger_value)
1787 {
1788 uint32_t ir4_value;
1789 uint32_t ir6_value;
1790 /* the default value of handling_suppressed_exception is false */
1791 static bool handling_suppressed_exception;
1792
1793 if (handling_suppressed_exception)
1794 return ERROR_OK;
1795
1796 if ((dbger_value & NDS_DBGER_ALL_SUPRS_EX) == NDS_DBGER_ALL_SUPRS_EX) {
1797 LOG_ERROR("<-- TARGET WARNING! Exception is detected and suppressed. -->");
1798 handling_suppressed_exception = true;
1799
1800 aice_read_reg(coreid, IR4, &ir4_value);
1801 /* Clear IR6.SUPRS_EXC, IR6.IMP_EXC */
1802 aice_read_reg(coreid, IR6, &ir6_value);
1803 /*
1804 * For MCU version(MSC_CFG.MCU == 1) like V3m
1805 * | SWID[30:16] | Reserved[15:10] | SUPRS_EXC[9] | IMP_EXC[8]
1806 * |VECTOR[7:5] | INST[4] | Exc Type[3:0] |
1807 *
1808 * For non-MCU version(MSC_CFG.MCU == 0) like V3
1809 * | SWID[30:16] | Reserved[15:14] | SUPRS_EXC[13] | IMP_EXC[12]
1810 * | VECTOR[11:5] | INST[4] | Exc Type[3:0] |
1811 */
1812 LOG_INFO("EVA: 0x%08" PRIx32, ir4_value);
1813 LOG_INFO("ITYPE: 0x%08" PRIx32, ir6_value);
1814
1815 ir6_value = ir6_value & (~0x300); /* for MCU */
1816 ir6_value = ir6_value & (~0x3000); /* for non-MCU */
1817 aice_write_reg(coreid, IR6, ir6_value);
1818
1819 handling_suppressed_exception = false;
1820 }
1821
1822 return ERROR_OK;
1823 }
1824
1825 static int check_privilege(uint32_t coreid, uint32_t dbger_value)
1826 {
1827 if ((dbger_value & NDS_DBGER_ILL_SEC_ACC) == NDS_DBGER_ILL_SEC_ACC) {
1828 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege "
1829 "to execute the debug operations. -->");
1830
1831 /* Clear DBGER.ILL_SEC_ACC */
1832 if (aice_write_misc(coreid, NDS_EDM_MISC_DBGER,
1833 NDS_DBGER_ILL_SEC_ACC) != ERROR_OK)
1834 return ERROR_FAIL;
1835 }
1836
1837 return ERROR_OK;
1838 }
1839
1840 static int aice_check_dbger(uint32_t coreid, uint32_t expect_status)
1841 {
1842 uint32_t i = 0;
1843 uint32_t value_dbger;
1844
1845 while (1) {
1846 aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &value_dbger);
1847
1848 if ((value_dbger & expect_status) == expect_status) {
1849 if (ERROR_OK != check_suppressed_exception(coreid, value_dbger))
1850 return ERROR_FAIL;
1851 if (ERROR_OK != check_privilege(coreid, value_dbger))
1852 return ERROR_FAIL;
1853 return ERROR_OK;
1854 }
1855
1856 if ((i % 30) == 0)
1857 keep_alive();
1858
1859 int64_t then = 0;
1860 if (i == aice_count_to_check_dbger)
1861 then = timeval_ms();
1862 if (i >= aice_count_to_check_dbger) {
1863 if ((timeval_ms() - then) > 1000) {
1864 LOG_ERROR("Timeout (1000ms) waiting for $DBGER status "
1865 "being 0x%08" PRIx32, expect_status);
1866 return ERROR_FAIL;
1867 }
1868 }
1869 i++;
1870 }
1871
1872 return ERROR_FAIL;
1873 }
1874
1875 static int aice_execute_dim(uint32_t coreid, uint32_t *insts, uint8_t n_inst)
1876 {
1877 /** fill DIM */
1878 if (aice_write_dim(coreid, insts, n_inst) != ERROR_OK)
1879 return ERROR_FAIL;
1880
1881 /** clear DBGER.DPED */
1882 if (aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_DPED) != ERROR_OK)
1883 return ERROR_FAIL;
1884
1885 /** execute DIM */
1886 if (aice_do_execute(coreid) != ERROR_OK)
1887 return ERROR_FAIL;
1888
1889 /** read DBGER.DPED */
1890 if (aice_check_dbger(coreid, NDS_DBGER_DPED) != ERROR_OK) {
1891 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly: "
1892 "0x%08" PRIx32 "0x%08" PRIx32 "0x%08" PRIx32 "0x%08" PRIx32 ". -->",
1893 insts[0],
1894 insts[1],
1895 insts[2],
1896 insts[3]);
1897 return ERROR_FAIL;
1898 }
1899
1900 return ERROR_OK;
1901 }
1902
1903 static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val)
1904 {
1905 LOG_DEBUG("aice_read_reg, reg_no: 0x%08" PRIx32, num);
1906
1907 uint32_t instructions[4]; /** execute instructions in DIM */
1908
1909 if (NDS32_REG_TYPE_GPR == nds32_reg_type(num)) { /* general registers */
1910 instructions[0] = MTSR_DTR(num);
1911 instructions[1] = DSB;
1912 instructions[2] = NOP;
1913 instructions[3] = BEQ_MINUS_12;
1914 } else if (NDS32_REG_TYPE_SPR == nds32_reg_type(num)) { /* user special registers */
1915 instructions[0] = MFUSR_G0(0, nds32_reg_sr_index(num));
1916 instructions[1] = MTSR_DTR(0);
1917 instructions[2] = DSB;
1918 instructions[3] = BEQ_MINUS_12;
1919 } else if (NDS32_REG_TYPE_AUMR == nds32_reg_type(num)) { /* audio registers */
1920 if ((CB_CTL <= num) && (num <= CBE3)) {
1921 instructions[0] = AMFAR2(0, nds32_reg_sr_index(num));
1922 instructions[1] = MTSR_DTR(0);
1923 instructions[2] = DSB;
1924 instructions[3] = BEQ_MINUS_12;
1925 } else {
1926 instructions[0] = AMFAR(0, nds32_reg_sr_index(num));
1927 instructions[1] = MTSR_DTR(0);
1928 instructions[2] = DSB;
1929 instructions[3] = BEQ_MINUS_12;
1930 }
1931 } else if (NDS32_REG_TYPE_FPU == nds32_reg_type(num)) { /* fpu registers */
1932 if (FPCSR == num) {
1933 instructions[0] = FMFCSR;
1934 instructions[1] = MTSR_DTR(0);
1935 instructions[2] = DSB;
1936 instructions[3] = BEQ_MINUS_12;
1937 } else if (FPCFG == num) {
1938 instructions[0] = FMFCFG;
1939 instructions[1] = MTSR_DTR(0);
1940 instructions[2] = DSB;
1941 instructions[3] = BEQ_MINUS_12;
1942 } else {
1943 if (FS0 <= num && num <= FS31) { /* single precision */
1944 instructions[0] = FMFSR(0, nds32_reg_sr_index(num));
1945 instructions[1] = MTSR_DTR(0);
1946 instructions[2] = DSB;
1947 instructions[3] = BEQ_MINUS_12;
1948 } else if (FD0 <= num && num <= FD31) { /* double precision */
1949 instructions[0] = FMFDR(0, nds32_reg_sr_index(num));
1950 instructions[1] = MTSR_DTR(0);
1951 instructions[2] = DSB;
1952 instructions[3] = BEQ_MINUS_12;
1953 }
1954 }
1955 } else { /* system registers */
1956 instructions[0] = MFSR(0, nds32_reg_sr_index(num));
1957 instructions[1] = MTSR_DTR(0);
1958 instructions[2] = DSB;
1959 instructions[3] = BEQ_MINUS_12;
1960 }
1961
1962 aice_execute_dim(coreid, instructions, 4);
1963
1964 uint32_t value_edmsw;
1965 aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw);
1966 if (value_edmsw & NDS_EDMSW_WDV)
1967 aice_read_dtr(coreid, val);
1968 else {
1969 LOG_ERROR("<-- TARGET ERROR! The debug target failed to update "
1970 "the DTR register. -->");
1971 return ERROR_FAIL;
1972 }
1973
1974 return ERROR_OK;
1975 }
1976
1977 static int aice_usb_read_reg(uint32_t coreid, uint32_t num, uint32_t *val)
1978 {
1979 LOG_DEBUG("aice_usb_read_reg");
1980
1981 if (num == R0) {
1982 *val = core_info[coreid].r0_backup;
1983 } else if (num == R1) {
1984 *val = core_info[coreid].r1_backup;
1985 } else if (num == DR41) {
1986 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
1987 * As user wants to read these registers, OpenOCD should return
1988 * the backup values, instead of reading the real values.
1989 * As user wants to write these registers, OpenOCD should write
1990 * to the backup values, instead of writing to real registers. */
1991 *val = core_info[coreid].edmsw_backup;
1992 } else if (num == DR42) {
1993 *val = core_info[coreid].edm_ctl_backup;
1994 } else if ((core_info[coreid].target_dtr_valid == true) && (num == DR43)) {
1995 *val = core_info[coreid].target_dtr_backup;
1996 } else {
1997 if (ERROR_OK != aice_read_reg(coreid, num, val))
1998 *val = 0xBBADBEEF;
1999 }
2000
2001 return ERROR_OK;
2002 }
2003
2004 static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val)
2005 {
2006 LOG_DEBUG("aice_write_reg, reg_no: 0x%08" PRIx32 ", value: 0x%08" PRIx32, num, val);
2007
2008 uint32_t instructions[4]; /** execute instructions in DIM */
2009 uint32_t value_edmsw;
2010
2011 aice_write_dtr(coreid, val);
2012 aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw);
2013 if (0 == (value_edmsw & NDS_EDMSW_RDV)) {
2014 LOG_ERROR("<-- TARGET ERROR! AICE failed to write to the DTR register. -->");
2015 return ERROR_FAIL;
2016 }
2017
2018 if (NDS32_REG_TYPE_GPR == nds32_reg_type(num)) { /* general registers */
2019 instructions[0] = MFSR_DTR(num);
2020 instructions[1] = DSB;
2021 instructions[2] = NOP;
2022 instructions[3] = BEQ_MINUS_12;
2023 } else if (NDS32_REG_TYPE_SPR == nds32_reg_type(num)) { /* user special registers */
2024 instructions[0] = MFSR_DTR(0);
2025 instructions[1] = MTUSR_G0(0, nds32_reg_sr_index(num));
2026 instructions[2] = DSB;
2027 instructions[3] = BEQ_MINUS_12;
2028 } else if (NDS32_REG_TYPE_AUMR == nds32_reg_type(num)) { /* audio registers */
2029 if ((CB_CTL <= num) && (num <= CBE3)) {
2030 instructions[0] = MFSR_DTR(0);
2031 instructions[1] = AMTAR2(0, nds32_reg_sr_index(num));
2032 instructions[2] = DSB;
2033 instructions[3] = BEQ_MINUS_12;
2034 } else {
2035 instructions[0] = MFSR_DTR(0);
2036 instructions[1] = AMTAR(0, nds32_reg_sr_index(num));
2037 instructions[2] = DSB;
2038 instructions[3] = BEQ_MINUS_12;
2039 }
2040 } else if (NDS32_REG_TYPE_FPU == nds32_reg_type(num)) { /* fpu registers */
2041 if (FPCSR == num) {
2042 instructions[0] = MFSR_DTR(0);
2043 instructions[1] = FMTCSR;
2044 instructions[2] = DSB;
2045 instructions[3] = BEQ_MINUS_12;
2046 } else if (FPCFG == num) {
2047 /* FPCFG is readonly */
2048 } else {
2049 if (FS0 <= num && num <= FS31) { /* single precision */
2050 instructions[0] = MFSR_DTR(0);
2051 instructions[1] = FMTSR(0, nds32_reg_sr_index(num));
2052 instructions[2] = DSB;
2053 instructions[3] = BEQ_MINUS_12;
2054 } else if (FD0 <= num && num <= FD31) { /* double precision */
2055 instructions[0] = MFSR_DTR(0);
2056 instructions[1] = FMTDR(0, nds32_reg_sr_index(num));
2057 instructions[2] = DSB;
2058 instructions[3] = BEQ_MINUS_12;
2059 }
2060 }
2061 } else {
2062 instructions[0] = MFSR_DTR(0);
2063 instructions[1] = MTSR(0, nds32_reg_sr_index(num));
2064 instructions[2] = DSB;
2065 instructions[3] = BEQ_MINUS_12;
2066 }
2067
2068 return aice_execute_dim(coreid, instructions, 4);
2069 }
2070
2071 static int aice_usb_write_reg(uint32_t coreid, uint32_t num, uint32_t val)
2072 {
2073 LOG_DEBUG("aice_usb_write_reg");
2074
2075 if (num == R0)
2076 core_info[coreid].r0_backup = val;
2077 else if (num == R1)
2078 core_info[coreid].r1_backup = val;
2079 else if (num == DR42)
2080 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
2081 * As user wants to read these registers, OpenOCD should return
2082 * the backup values, instead of reading the real values.
2083 * As user wants to write these registers, OpenOCD should write
2084 * to the backup values, instead of writing to real registers. */
2085 core_info[coreid].edm_ctl_backup = val;
2086 else if ((core_info[coreid].target_dtr_valid == true) && (num == DR43))
2087 core_info[coreid].target_dtr_backup = val;
2088 else
2089 return aice_write_reg(coreid, num, val);
2090
2091 return ERROR_OK;
2092 }
2093
2094 static int aice_usb_open(struct aice_port_param_s *param)
2095 {
2096 const uint16_t vids[] = { param->vid, 0 };
2097 const uint16_t pids[] = { param->pid, 0 };
2098 struct jtag_libusb_device_handle *devh;
2099
2100 if (jtag_libusb_open(vids, pids, NULL, &devh) != ERROR_OK)
2101 return ERROR_FAIL;
2102
2103 /* BE ***VERY CAREFUL*** ABOUT MAKING CHANGES IN THIS
2104 * AREA!!!!!!!!!!! The behavior of libusb is not completely
2105 * consistent across Windows, Linux, and Mac OS X platforms.
2106 * The actions taken in the following compiler conditionals may
2107 * not agree with published documentation for libusb, but were
2108 * found to be necessary through trials and tribulations. Even
2109 * little tweaks can break one or more platforms, so if you do
2110 * make changes test them carefully on all platforms before
2111 * committing them!
2112 */
2113
2114 #if IS_WIN32 == 0
2115
2116 jtag_libusb_reset_device(devh);
2117
2118 #if IS_DARWIN == 0
2119
2120 int timeout = 5;
2121 /* reopen jlink after usb_reset
2122 * on win32 this may take a second or two to re-enumerate */
2123 int retval;
2124 while ((retval = jtag_libusb_open(vids, pids, NULL, &devh)) != ERROR_OK) {
2125 usleep(1000);
2126 timeout--;
2127 if (!timeout)
2128 break;
2129 }
2130 if (ERROR_OK != retval)
2131 return ERROR_FAIL;
2132 #endif
2133
2134 #endif
2135
2136 /* usb_set_configuration required under win32 */
2137 jtag_libusb_set_configuration(devh, 0);
2138 jtag_libusb_claim_interface(devh, 0);
2139
2140 unsigned int aice_read_ep;
2141 unsigned int aice_write_ep;
2142
2143 jtag_libusb_choose_interface(devh, &aice_read_ep, &aice_write_ep, -1, -1, -1, LIBUSB_TRANSFER_TYPE_BULK);
2144 LOG_DEBUG("aice_read_ep=0x%x, aice_write_ep=0x%x", aice_read_ep, aice_write_ep);
2145
2146 aice_handler.usb_read_ep = aice_read_ep;
2147 aice_handler.usb_write_ep = aice_write_ep;
2148 aice_handler.usb_handle = devh;
2149
2150 return ERROR_OK;
2151 }
2152
2153 static int aice_usb_read_reg_64(uint32_t coreid, uint32_t num, uint64_t *val)
2154 {
2155 LOG_DEBUG("aice_usb_read_reg_64, %s", nds32_reg_simple_name(num));
2156
2157 uint32_t value;
2158 uint32_t high_value;
2159
2160 if (ERROR_OK != aice_read_reg(coreid, num, &value))
2161 value = 0xBBADBEEF;
2162
2163 aice_read_reg(coreid, R1, &high_value);
2164
2165 LOG_DEBUG("low: 0x%08" PRIx32 ", high: 0x%08" PRIx32 "\n", value, high_value);
2166
2167 if (data_endian == AICE_BIG_ENDIAN)
2168 *val = (((uint64_t)high_value) << 32) | value;
2169 else
2170 *val = (((uint64_t)value) << 32) | high_value;
2171
2172 return ERROR_OK;
2173 }
2174
2175 static int aice_usb_write_reg_64(uint32_t coreid, uint32_t num, uint64_t val)
2176 {
2177 uint32_t value;
2178 uint32_t high_value;
2179
2180 if (data_endian == AICE_BIG_ENDIAN) {
2181 value = val & 0xFFFFFFFF;
2182 high_value = (val >> 32) & 0xFFFFFFFF;
2183 } else {
2184 high_value = val & 0xFFFFFFFF;
2185 value = (val >> 32) & 0xFFFFFFFF;
2186 }
2187
2188 LOG_DEBUG("aice_usb_write_reg_64, %s, low: 0x%08" PRIx32 ", high: 0x%08" PRIx32 "\n",
2189 nds32_reg_simple_name(num), value, high_value);
2190
2191 aice_write_reg(coreid, R1, high_value);
2192 return aice_write_reg(coreid, num, value);
2193 }
2194
2195 static int aice_get_version_info(void)
2196 {
2197 uint32_t hardware_version;
2198 uint32_t firmware_version;
2199 uint32_t fpga_version;
2200
2201 if (aice_read_ctrl(AICE_READ_CTRL_GET_HARDWARE_VERSION, &hardware_version) != ERROR_OK)
2202 return ERROR_FAIL;
2203
2204 if (aice_read_ctrl(AICE_READ_CTRL_GET_FIRMWARE_VERSION, &firmware_version) != ERROR_OK)
2205 return ERROR_FAIL;
2206
2207 if (aice_read_ctrl(AICE_READ_CTRL_GET_FPGA_VERSION, &fpga_version) != ERROR_OK)
2208 return ERROR_FAIL;
2209
2210 LOG_INFO("AICE version: hw_ver = 0x%" PRIx32 ", fw_ver = 0x%" PRIx32 ", fpga_ver = 0x%" PRIx32,
2211 hardware_version, firmware_version, fpga_version);
2212
2213 return ERROR_OK;
2214 }
2215
2216 #define LINE_BUFFER_SIZE 1024
2217
2218 static int aice_execute_custom_script(const char *script)
2219 {
2220 FILE *script_fd;
2221 char line_buffer[LINE_BUFFER_SIZE];
2222 char *op_str;
2223 char *reset_str;
2224 uint32_t delay;
2225 uint32_t write_ctrl_value;
2226 bool set_op;
2227
2228 script_fd = fopen(script, "r");
2229 if (script_fd == NULL) {
2230 return ERROR_FAIL;
2231 } else {
2232 while (fgets(line_buffer, LINE_BUFFER_SIZE, script_fd) != NULL) {
2233 /* execute operations */
2234 set_op = false;
2235 op_str = strstr(line_buffer, "set");
2236 if (op_str != NULL) {
2237 set_op = true;
2238 goto get_reset_type;
2239 }
2240
2241 op_str = strstr(line_buffer, "clear");
2242 if (op_str == NULL)
2243 continue;
2244 get_reset_type:
2245 reset_str = strstr(op_str, "srst");
2246 if (reset_str != NULL) {
2247 if (set_op)
2248 write_ctrl_value = AICE_CUSTOM_DELAY_SET_SRST;
2249 else
2250 write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_SRST;
2251 goto get_delay;
2252 }
2253 reset_str = strstr(op_str, "dbgi");
2254 if (reset_str != NULL) {
2255 if (set_op)
2256 write_ctrl_value = AICE_CUSTOM_DELAY_SET_DBGI;
2257 else
2258 write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_DBGI;
2259 goto get_delay;
2260 }
2261 reset_str = strstr(op_str, "trst");
2262 if (reset_str != NULL) {
2263 if (set_op)
2264 write_ctrl_value = AICE_CUSTOM_DELAY_SET_TRST;
2265 else
2266 write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_TRST;
2267 goto get_delay;
2268 }
2269 continue;
2270 get_delay:
2271 /* get delay */
2272 delay = strtoul(reset_str + 4, NULL, 0);
2273 write_ctrl_value |= (delay << 16);
2274
2275 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY,
2276 write_ctrl_value) != ERROR_OK) {
2277 fclose(script_fd);
2278 return ERROR_FAIL;
2279 }
2280 }
2281 fclose(script_fd);
2282 }
2283
2284 return ERROR_OK;
2285 }
2286
2287 static int aice_usb_set_clock(int set_clock)
2288 {
2289 if (set_clock & AICE_TCK_CONTROL_TCK_SCAN) {
2290 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL,
2291 AICE_TCK_CONTROL_TCK_SCAN) != ERROR_OK)
2292 return ERROR_FAIL;
2293
2294 /* Read out TCK_SCAN clock value */
2295 uint32_t scan_clock;
2296 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE, &scan_clock) != ERROR_OK)
2297 return ERROR_FAIL;
2298
2299 scan_clock &= 0x0F;
2300
2301 uint32_t scan_base_freq;
2302 if (scan_clock & 0x8)
2303 scan_base_freq = 48000; /* 48 MHz */
2304 else
2305 scan_base_freq = 30000; /* 30 MHz */
2306
2307 uint32_t set_base_freq;
2308 if (set_clock & 0x8)
2309 set_base_freq = 48000;
2310 else
2311 set_base_freq = 30000;
2312
2313 uint32_t set_freq;
2314 uint32_t scan_freq;
2315 set_freq = set_base_freq >> (set_clock & 0x7);
2316 scan_freq = scan_base_freq >> (scan_clock & 0x7);
2317
2318 if (scan_freq < set_freq) {
2319 LOG_ERROR("User specifies higher jtag clock than TCK_SCAN clock");
2320 return ERROR_FAIL;
2321 }
2322 }
2323
2324 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL, set_clock) != ERROR_OK)
2325 return ERROR_FAIL;
2326
2327 uint32_t check_speed;
2328 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE, &check_speed) != ERROR_OK)
2329 return ERROR_FAIL;
2330
2331 if (((int)check_speed & 0x0F) != set_clock) {
2332 LOG_ERROR("Set jtag clock failed");
2333 return ERROR_FAIL;
2334 }
2335
2336 return ERROR_OK;
2337 }
2338
2339 static int aice_edm_init(uint32_t coreid)
2340 {
2341 aice_write_edmsr(coreid, NDS_EDM_SR_DIMBR, 0xFFFF0000);
2342 aice_write_misc(coreid, NDS_EDM_MISC_DIMIR, 0);
2343
2344 /* unconditionally try to turn on V3_EDM_MODE */
2345 uint32_t edm_ctl_value;
2346 aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL, &edm_ctl_value);
2347 aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value | 0x00000040);
2348
2349 /* clear DBGER */
2350 aice_write_misc(coreid, NDS_EDM_MISC_DBGER,
2351 NDS_DBGER_DPED | NDS_DBGER_CRST | NDS_DBGER_AT_MAX);
2352
2353 /* get EDM version */
2354 uint32_t value_edmcfg;
2355 aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CFG, &value_edmcfg);
2356 core_info[coreid].edm_version = (value_edmcfg >> 16) & 0xFFFF;
2357
2358 return ERROR_OK;
2359 }
2360
2361 static bool is_v2_edm(uint32_t coreid)
2362 {
2363 if ((core_info[coreid].edm_version & 0x1000) == 0)
2364 return true;
2365 else
2366 return false;
2367 }
2368
2369 static int aice_init_edm_registers(uint32_t coreid, bool clear_dex_use_psw)
2370 {
2371 /* enable DEH_SEL & MAX_STOP & V3_EDM_MODE & DBGI_MASK */
2372 uint32_t host_edm_ctl = core_info[coreid].edm_ctl_backup | 0xA000004F;
2373 if (clear_dex_use_psw)
2374 /* After entering debug mode, OpenOCD may set
2375 * DEX_USE_PSW accidentally through backup value
2376 * of target EDM_CTL.
2377 * So, clear DEX_USE_PSW by force. */
2378 host_edm_ctl &= ~(0x40000000);
2379
2380 LOG_DEBUG("aice_init_edm_registers - EDM_CTL: 0x%08" PRIx32, host_edm_ctl);
2381
2382 int result = aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, host_edm_ctl);
2383
2384 return result;
2385 }
2386
2387 /**
2388 * EDM_CTL will be modified by OpenOCD as debugging. OpenOCD has the
2389 * responsibility to keep EDM_CTL untouched after debugging.
2390 *
2391 * There are two scenarios to consider:
2392 * 1. single step/running as debugging (running under debug session)
2393 * 2. detached from gdb (exit debug session)
2394 *
2395 * So, we need to bakcup EDM_CTL before halted and restore it after
2396 * running. The difference of these two scenarios is EDM_CTL.DEH_SEL
2397 * is on for scenario 1, and off for scenario 2.
2398 */
2399 static int aice_backup_edm_registers(uint32_t coreid)
2400 {
2401 int result = aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL,
2402 &core_info[coreid].edm_ctl_backup);
2403
2404 /* To call aice_backup_edm_registers() after DEX on, DEX_USE_PSW
2405 * may be not correct. (For example, hit breakpoint, then backup
2406 * EDM_CTL. EDM_CTL.DEX_USE_PSW will be cleared.) Because debug
2407 * interrupt will clear DEX_USE_PSW, DEX_USE_PSW is always off after
2408 * DEX is on. It only backups correct value before OpenOCD issues DBGI.
2409 * (Backup EDM_CTL, then issue DBGI actively (refer aice_usb_halt())) */
2410 if (core_info[coreid].edm_ctl_backup & 0x40000000)
2411 core_info[coreid].dex_use_psw_on = true;
2412 else
2413 core_info[coreid].dex_use_psw_on = false;
2414
2415 LOG_DEBUG("aice_backup_edm_registers - EDM_CTL: 0x%08" PRIx32 ", DEX_USE_PSW: %s",
2416 core_info[coreid].edm_ctl_backup,
2417 core_info[coreid].dex_use_psw_on ? "on" : "off");
2418
2419 return result;
2420 }
2421
2422 static int aice_restore_edm_registers(uint32_t coreid)
2423 {
2424 LOG_DEBUG("aice_restore_edm_registers -");
2425
2426 /* set DEH_SEL, because target still under EDM control */
2427 int result = aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL,
2428 core_info[coreid].edm_ctl_backup | 0x80000000);
2429
2430 return result;
2431 }
2432
2433 static int aice_backup_tmp_registers(uint32_t coreid)
2434 {
2435 LOG_DEBUG("backup_tmp_registers -");
2436
2437 /* backup target DTR first(if the target DTR is valid) */
2438 uint32_t value_edmsw;
2439 aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw);
2440 core_info[coreid].edmsw_backup = value_edmsw;
2441 if (value_edmsw & 0x1) { /* EDMSW.WDV == 1 */
2442 aice_read_dtr(coreid, &core_info[coreid].target_dtr_backup);
2443 core_info[coreid].target_dtr_valid = true;
2444
2445 LOG_DEBUG("Backup target DTR: 0x%08" PRIx32, core_info[coreid].target_dtr_backup);
2446 } else {
2447 core_info[coreid].target_dtr_valid = false;
2448 }
2449
2450 /* Target DTR has been backup, then backup $R0 and $R1 */
2451 aice_read_reg(coreid, R0, &core_info[coreid].r0_backup);
2452 aice_read_reg(coreid, R1, &core_info[coreid].r1_backup);
2453
2454 /* backup host DTR(if the host DTR is valid) */
2455 if (value_edmsw & 0x2) { /* EDMSW.RDV == 1*/
2456 /* read out host DTR and write into target DTR, then use aice_read_edmsr to
2457 * read out */
2458 uint32_t instructions[4] = {
2459 MFSR_DTR(R0), /* R0 has already been backup */
2460 DSB,
2461 MTSR_DTR(R0),
2462 BEQ_MINUS_12
2463 };
2464 aice_execute_dim(coreid, instructions, 4);
2465
2466 aice_read_dtr(coreid, &core_info[coreid].host_dtr_backup);
2467 core_info[coreid].host_dtr_valid = true;
2468
2469 LOG_DEBUG("Backup host DTR: 0x%08" PRIx32, core_info[coreid].host_dtr_backup);
2470 } else {
2471 core_info[coreid].host_dtr_valid = false;
2472 }
2473
2474 LOG_DEBUG("r0: 0x%08" PRIx32 ", r1: 0x%08" PRIx32,
2475 core_info[coreid].r0_backup, core_info[coreid].r1_backup);
2476
2477 return ERROR_OK;
2478 }
2479
2480 static int aice_restore_tmp_registers(uint32_t coreid)
2481 {
2482 LOG_DEBUG("restore_tmp_registers - r0: 0x%08" PRIx32 ", r1: 0x%08" PRIx32,
2483 core_info[coreid].r0_backup, core_info[coreid].r1_backup);
2484
2485 if (core_info[coreid].target_dtr_valid) {
2486 uint32_t instructions[4] = {
2487 SETHI(R0, core_info[coreid].target_dtr_backup >> 12),
2488 ORI(R0, R0, core_info[coreid].target_dtr_backup & 0x00000FFF),
2489 NOP,
2490 BEQ_MINUS_12
2491 };
2492 aice_execute_dim(coreid, instructions, 4);
2493
2494 instructions[0] = MTSR_DTR(R0);
2495 instructions[1] = DSB;
2496 instructions[2] = NOP;
2497 instructions[3] = BEQ_MINUS_12;
2498 aice_execute_dim(coreid, instructions, 4);
2499
2500 LOG_DEBUG("Restore target DTR: 0x%08" PRIx32, core_info[coreid].target_dtr_backup);
2501 }
2502
2503 aice_write_reg(coreid, R0, core_info[coreid].r0_backup);
2504 aice_write_reg(coreid, R1, core_info[coreid].r1_backup);
2505
2506 if (core_info[coreid].host_dtr_valid) {
2507 aice_write_dtr(coreid, core_info[coreid].host_dtr_backup);
2508
2509 LOG_DEBUG("Restore host DTR: 0x%08" PRIx32, core_info[coreid].host_dtr_backup);
2510 }
2511
2512 return ERROR_OK;
2513 }
2514
2515 static int aice_open_device(struct aice_port_param_s *param)
2516 {
2517 if (ERROR_OK != aice_usb_open(param))
2518 return ERROR_FAIL;
2519
2520 if (ERROR_FAIL == aice_get_version_info()) {
2521 LOG_ERROR("Cannot get AICE version!");
2522 return ERROR_FAIL;
2523 }
2524
2525 LOG_INFO("AICE initialization started");
2526
2527 /* attempt to reset Andes EDM */
2528 if (ERROR_FAIL == aice_reset_box()) {
2529 LOG_ERROR("Cannot initial AICE box!");
2530 return ERROR_FAIL;
2531 }
2532
2533 return ERROR_OK;
2534 }
2535
2536 static int aice_usb_set_jtag_clock(uint32_t a_clock)
2537 {
2538 jtag_clock = a_clock;
2539
2540 if (ERROR_OK != aice_usb_set_clock(a_clock)) {
2541 LOG_ERROR("Cannot set AICE JTAG clock!");
2542 return ERROR_FAIL;
2543 }
2544
2545 return ERROR_OK;
2546 }
2547
2548 static int aice_usb_close(void)
2549 {
2550 jtag_libusb_close(aice_handler.usb_handle);
2551
2552 if (custom_srst_script)
2553 free(custom_srst_script);
2554
2555 if (custom_trst_script)
2556 free(custom_trst_script);
2557
2558 if (custom_restart_script)
2559 free(custom_restart_script);
2560
2561 return ERROR_OK;
2562 }
2563
2564 static int aice_core_init(uint32_t coreid)
2565 {
2566 core_info[coreid].access_channel = NDS_MEMORY_ACC_CPU;
2567 core_info[coreid].memory_select = NDS_MEMORY_SELECT_AUTO;
2568 core_info[coreid].core_state = AICE_TARGET_UNKNOWN;
2569
2570 return ERROR_OK;
2571 }
2572
2573 static int aice_usb_idcode(uint32_t *idcode, uint8_t *num_of_idcode)
2574 {
2575 int retval;
2576
2577 retval = aice_scan_chain(idcode, num_of_idcode);
2578 if (ERROR_OK == retval) {
2579 for (int i = 0; i < *num_of_idcode; i++) {
2580 aice_core_init(i);
2581 aice_edm_init(i);
2582 }
2583 total_num_of_core = *num_of_idcode;
2584 }
2585
2586 return retval;
2587 }
2588
2589 static int aice_usb_halt(uint32_t coreid)
2590 {
2591 if (core_info[coreid].core_state == AICE_TARGET_HALTED) {
2592 LOG_DEBUG("aice_usb_halt check halted");
2593 return ERROR_OK;
2594 }
2595
2596 LOG_DEBUG("aice_usb_halt");
2597
2598 /** backup EDM registers */
2599 aice_backup_edm_registers(coreid);
2600 /** init EDM for host debugging */
2601 /** no need to clear dex_use_psw, because dbgi will clear it */
2602 aice_init_edm_registers(coreid, false);
2603
2604 /** Clear EDM_CTL.DBGIM & EDM_CTL.DBGACKM */
2605 uint32_t edm_ctl_value;
2606 aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL, &edm_ctl_value);
2607 if (edm_ctl_value & 0x3)
2608 aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value & ~(0x3));
2609
2610 uint32_t dbger;
2611 uint32_t acc_ctl_value;
2612
2613 core_info[coreid].debug_under_dex_on = false;
2614 aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &dbger);
2615
2616 if (dbger & NDS_DBGER_AT_MAX)
2617 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level. -->");
2618
2619 if (dbger & NDS_DBGER_DEX) {
2620 if (is_v2_edm(coreid) == false) {
2621 /** debug 'debug mode'. use force_debug to issue dbgi */
2622 aice_read_misc(coreid, NDS_EDM_MISC_ACC_CTL, &acc_ctl_value);
2623 acc_ctl_value |= 0x8;
2624 aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL, acc_ctl_value);
2625 core_info[coreid].debug_under_dex_on = true;
2626
2627 aice_write_misc(coreid, NDS_EDM_MISC_EDM_CMDR, 0);
2628 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2629 if (dbger & NDS_DBGER_AT_MAX)
2630 aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_AT_MAX);
2631 }
2632 } else {
2633 /** Issue DBGI normally */
2634 aice_write_misc(coreid, NDS_EDM_MISC_EDM_CMDR, 0);
2635 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2636 if (dbger & NDS_DBGER_AT_MAX)
2637 aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_AT_MAX);
2638 }
2639
2640 if (aice_check_dbger(coreid, NDS_DBGER_DEX) != ERROR_OK) {
2641 LOG_ERROR("<-- TARGET ERROR! Unable to stop the debug target through DBGI. -->");
2642 return ERROR_FAIL;
2643 }
2644
2645 if (core_info[coreid].debug_under_dex_on) {
2646 if (core_info[coreid].dex_use_psw_on == false) {
2647 /* under debug 'debug mode', force $psw to 'debug mode' bahavior */
2648 /* !!!NOTICE!!! this is workaround for debug 'debug mode'.
2649 * it is only for debugging 'debug exception handler' purpose.
2650 * after openocd detaches from target, target behavior is
2651 * undefined. */
2652 uint32_t ir0_value;
2653 uint32_t debug_mode_ir0_value;
2654 aice_read_reg(coreid, IR0, &ir0_value);
2655 debug_mode_ir0_value = ir0_value | 0x408; /* turn on DEX, set POM = 1 */
2656 debug_mode_ir0_value &= ~(0x000000C1); /* turn off DT/IT/GIE */
2657 aice_write_reg(coreid, IR0, debug_mode_ir0_value);
2658 }
2659 }
2660
2661 /** set EDM_CTL.DBGIM & EDM_CTL.DBGACKM after halt */
2662 if (edm_ctl_value & 0x3)
2663 aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value);
2664
2665 /* backup r0 & r1 */
2666 aice_backup_tmp_registers(coreid);
2667 core_info[coreid].core_state = AICE_TARGET_HALTED;
2668
2669 return ERROR_OK;
2670 }
2671
2672 static int aice_usb_state(uint32_t coreid, enum aice_target_state_s *state)
2673 {
2674 uint32_t dbger_value;
2675 uint32_t ice_state;
2676
2677 int result = aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &dbger_value);
2678
2679 if (ERROR_AICE_TIMEOUT == result) {
2680 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE, &ice_state) != ERROR_OK) {
2681 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2682 return ERROR_FAIL;
2683 }
2684
2685 if ((ice_state & 0x20) == 0) {
2686 LOG_ERROR("<-- TARGET ERROR! Target is disconnected with AICE. -->");
2687 return ERROR_FAIL;
2688 } else {
2689 return ERROR_FAIL;
2690 }
2691 } else if (ERROR_AICE_DISCONNECT == result) {
2692 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2693 return ERROR_FAIL;
2694 }
2695
2696 if ((dbger_value & NDS_DBGER_ILL_SEC_ACC) == NDS_DBGER_ILL_SEC_ACC) {
2697 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege. -->");
2698
2699 /* Clear ILL_SEC_ACC */
2700 aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_ILL_SEC_ACC);
2701
2702 *state = AICE_TARGET_RUNNING;
2703 core_info[coreid].core_state = AICE_TARGET_RUNNING;
2704 } else if ((dbger_value & NDS_DBGER_AT_MAX) == NDS_DBGER_AT_MAX) {
2705 /* Issue DBGI to exit cpu stall */
2706 aice_usb_halt(coreid);
2707
2708 /* Read OIPC to find out the trigger point */
2709 uint32_t ir11_value;
2710 aice_read_reg(coreid, IR11, &ir11_value);
2711
2712 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level; "
2713 "CPU is stalled at 0x%08" PRIx32 " for debugging. -->", ir11_value);
2714
2715 *state = AICE_TARGET_HALTED;
2716 } else if ((dbger_value & NDS_DBGER_CRST) == NDS_DBGER_CRST) {
2717 LOG_DEBUG("DBGER.CRST is on.");
2718
2719 *state = AICE_TARGET_RESET;
2720 core_info[coreid].core_state = AICE_TARGET_RUNNING;
2721
2722 /* Clear CRST */
2723 aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_CRST);
2724 } else if ((dbger_value & NDS_DBGER_DEX) == NDS_DBGER_DEX) {
2725 if (AICE_TARGET_RUNNING == core_info[coreid].core_state) {
2726 /* enter debug mode, init EDM registers */
2727 /* backup EDM registers */
2728 aice_backup_edm_registers(coreid);
2729 /* init EDM for host debugging */
2730 aice_init_edm_registers(coreid, true);
2731 aice_backup_tmp_registers(coreid);
2732 core_info[coreid].core_state = AICE_TARGET_HALTED;
2733 } else if (AICE_TARGET_UNKNOWN == core_info[coreid].core_state) {
2734 /* debug 'debug mode', use force debug to halt core */
2735 aice_usb_halt(coreid);
2736 }
2737 *state = AICE_TARGET_HALTED;
2738 } else {
2739 *state = AICE_TARGET_RUNNING;
2740 core_info[coreid].core_state = AICE_TARGET_RUNNING;
2741 }
2742
2743 return ERROR_OK;
2744 }
2745
2746 static int aice_usb_reset(void)
2747 {
2748 if (aice_reset_box() != ERROR_OK)
2749 return ERROR_FAIL;
2750
2751 /* issue TRST */
2752 if (custom_trst_script == NULL) {
2753 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL,
2754 AICE_JTAG_PIN_CONTROL_TRST) != ERROR_OK)
2755 return ERROR_FAIL;
2756 } else {
2757 /* custom trst operations */
2758 if (aice_execute_custom_script(custom_trst_script) != ERROR_OK)
2759 return ERROR_FAIL;
2760 }
2761
2762 if (aice_usb_set_clock(jtag_clock) != ERROR_OK)
2763 return ERROR_FAIL;
2764
2765 return ERROR_OK;
2766 }
2767
2768 static int aice_issue_srst(uint32_t coreid)
2769 {
2770 LOG_DEBUG("aice_issue_srst");
2771
2772 /* After issuing srst, target will be running. So we need to restore EDM_CTL. */
2773 aice_restore_edm_registers(coreid);
2774
2775 if (custom_srst_script == NULL) {
2776 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL,
2777 AICE_JTAG_PIN_CONTROL_SRST) != ERROR_OK)
2778 return ERROR_FAIL;
2779 } else {
2780 /* custom srst operations */
2781 if (aice_execute_custom_script(custom_srst_script) != ERROR_OK)
2782 return ERROR_FAIL;
2783 }
2784
2785 /* wait CRST infinitely */
2786 uint32_t dbger_value;
2787 int i = 0;
2788 while (1) {
2789 if (aice_read_misc(coreid,
2790 NDS_EDM_MISC_DBGER, &dbger_value) != ERROR_OK)
2791 return ERROR_FAIL;
2792
2793 if (dbger_value & NDS_DBGER_CRST)
2794 break;
2795
2796 if ((i % 30) == 0)
2797 keep_alive();
2798 i++;
2799 }
2800
2801 core_info[coreid].host_dtr_valid = false;
2802 core_info[coreid].target_dtr_valid = false;
2803
2804 core_info[coreid].core_state = AICE_TARGET_RUNNING;
2805 return ERROR_OK;
2806 }
2807
2808 static int aice_issue_reset_hold(uint32_t coreid)
2809 {
2810 LOG_DEBUG("aice_issue_reset_hold");
2811
2812 /* set no_dbgi_pin to 0 */
2813 uint32_t pin_status;
2814 aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS, &pin_status);
2815 if (pin_status & 0x4)
2816 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS, pin_status & (~0x4));
2817
2818 /* issue restart */
2819 if (custom_restart_script == NULL) {
2820 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL,
2821 AICE_JTAG_PIN_CONTROL_RESTART) != ERROR_OK)
2822 return ERROR_FAIL;
2823 } else {
2824 /* custom restart operations */
2825 if (aice_execute_custom_script(custom_restart_script) != ERROR_OK)
2826 return ERROR_FAIL;
2827 }
2828
2829 if (aice_check_dbger(coreid, NDS_DBGER_CRST | NDS_DBGER_DEX) == ERROR_OK) {
2830 aice_backup_tmp_registers(coreid);
2831 core_info[coreid].core_state = AICE_TARGET_HALTED;
2832
2833 return ERROR_OK;
2834 } else {
2835 /* set no_dbgi_pin to 1 */
2836 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS, pin_status | 0x4);
2837
2838 /* issue restart again */
2839 if (custom_restart_script == NULL) {
2840 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL,
2841 AICE_JTAG_PIN_CONTROL_RESTART) != ERROR_OK)
2842 return ERROR_FAIL;
2843 } else {
2844 /* custom restart operations */
2845 if (aice_execute_custom_script(custom_restart_script) != ERROR_OK)
2846 return ERROR_FAIL;
2847 }
2848
2849 if (aice_check_dbger(coreid, NDS_DBGER_CRST | NDS_DBGER_DEX) == ERROR_OK) {
2850 aice_backup_tmp_registers(coreid);
2851 core_info[coreid].core_state = AICE_TARGET_HALTED;
2852
2853 return ERROR_OK;
2854 }
2855
2856 /* do software reset-and-hold */
2857 aice_issue_srst(coreid);
2858 aice_usb_halt(coreid);
2859
2860 uint32_t value_ir3;
2861 aice_read_reg(coreid, IR3, &value_ir3);
2862 aice_write_reg(coreid, PC, value_ir3 & 0xFFFF0000);
2863 }
2864
2865 return ERROR_FAIL;
2866 }
2867
2868 static int aice_issue_reset_hold_multi(void)
2869 {
2870 uint32_t write_ctrl_value = 0;
2871
2872 /* set SRST */
2873 write_ctrl_value = AICE_CUSTOM_DELAY_SET_SRST;
2874 write_ctrl_value |= (0x200 << 16);
2875 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY,
2876 write_ctrl_value) != ERROR_OK)
2877 return ERROR_FAIL;
2878
2879 for (uint8_t i = 0 ; i < total_num_of_core ; i++)
2880 aice_write_misc(i, NDS_EDM_MISC_EDM_CMDR, 0);
2881
2882 /* clear SRST */
2883 write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_SRST;
2884 write_ctrl_value |= (0x200 << 16);
2885 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY,
2886 write_ctrl_value) != ERROR_OK)
2887 return ERROR_FAIL;
2888
2889 for (uint8_t i = 0; i < total_num_of_core; i++)
2890 aice_edm_init(i);
2891
2892 return ERROR_FAIL;
2893 }
2894
2895 static int aice_usb_assert_srst(uint32_t coreid, enum aice_srst_type_s srst)
2896 {
2897 if ((AICE_SRST != srst) && (AICE_RESET_HOLD != srst))
2898 return ERROR_FAIL;
2899
2900 /* clear DBGER */
2901 if (aice_write_misc(coreid, NDS_EDM_MISC_DBGER,
2902 NDS_DBGER_CLEAR_ALL) != ERROR_OK)
2903 return ERROR_FAIL;
2904
2905 int result = ERROR_OK;
2906 if (AICE_SRST == srst)
2907 result = aice_issue_srst(coreid);
2908 else {
2909 if (1 == total_num_of_core)
2910 result = aice_issue_reset_hold(coreid);
2911 else
2912 result = aice_issue_reset_hold_multi();
2913 }
2914
2915 /* Clear DBGER.CRST after reset to avoid 'core-reset checking' errors.
2916 * assert_srst is user-intentional reset behavior, so we could
2917 * clear DBGER.CRST safely.
2918 */
2919 if (aice_write_misc(coreid,
2920 NDS_EDM_MISC_DBGER, NDS_DBGER_CRST) != ERROR_OK)
2921 return ERROR_FAIL;
2922
2923 return result;
2924 }
2925
2926 static int aice_usb_run(uint32_t coreid)
2927 {
2928 LOG_DEBUG("aice_usb_run");
2929
2930 uint32_t dbger_value;
2931 if (aice_read_misc(coreid,
2932 NDS_EDM_MISC_DBGER, &dbger_value) != ERROR_OK)
2933 return ERROR_FAIL;
2934
2935 if ((dbger_value & NDS_DBGER_DEX) != NDS_DBGER_DEX) {
2936 LOG_WARNING("<-- TARGET WARNING! The debug target exited "
2937 "the debug mode unexpectedly. -->");
2938 return ERROR_FAIL;
2939 }
2940
2941 /* restore r0 & r1 before free run */
2942 aice_restore_tmp_registers(coreid);
2943 core_info[coreid].core_state = AICE_TARGET_RUNNING;
2944
2945 /* clear DBGER */
2946 aice_write_misc(coreid, NDS_EDM_MISC_DBGER,
2947 NDS_DBGER_CLEAR_ALL);
2948
2949 /** restore EDM registers */
2950 /** OpenOCD should restore EDM_CTL **before** to exit debug state.
2951 * Otherwise, following instruction will read wrong EDM_CTL value.
2952 *
2953 * pc -> mfsr $p0, EDM_CTL (single step)
2954 * slli $p0, $p0, 1
2955 * slri $p0, $p0, 31
2956 */
2957 aice_restore_edm_registers(coreid);
2958
2959 /** execute instructions in DIM */
2960 uint32_t instructions[4] = {
2961 NOP,
2962 NOP,
2963 NOP,
2964 IRET
2965 };
2966 int result = aice_execute_dim(coreid, instructions, 4);
2967
2968 return result;
2969 }
2970
2971 static int aice_usb_step(uint32_t coreid)
2972 {
2973 LOG_DEBUG("aice_usb_step");
2974
2975 uint32_t ir0_value;
2976 uint32_t ir0_reg_num;
2977
2978 if (is_v2_edm(coreid) == true)
2979 /* V2 EDM will push interrupt stack as debug exception */
2980 ir0_reg_num = IR1;
2981 else
2982 ir0_reg_num = IR0;
2983
2984 /** enable HSS */
2985 aice_read_reg(coreid, ir0_reg_num, &ir0_value);
2986 if ((ir0_value & 0x800) == 0) {
2987 /** set PSW.HSS */
2988 ir0_value |= (0x01 << 11);
2989 aice_write_reg(coreid, ir0_reg_num, ir0_value);
2990 }
2991
2992 if (ERROR_FAIL == aice_usb_run(coreid))
2993 return ERROR_FAIL;
2994
2995 int i = 0;
2996 enum aice_target_state_s state;
2997 while (1) {
2998 /* read DBGER */
2999 if (aice_usb_state(coreid, &state) != ERROR_OK)
3000 return ERROR_FAIL;
3001
3002 if (AICE_TARGET_HALTED == state)
3003 break;
3004
3005 int64_t then = 0;
3006 if (i == 30)
3007 then = timeval_ms();
3008
3009 if (i >= 30) {
3010 if ((timeval_ms() - then) > 1000)
3011 LOG_WARNING("Timeout (1000ms) waiting for halt to complete");
3012
3013 return ERROR_FAIL;
3014 }
3015 i++;
3016 }
3017
3018 /** disable HSS */
3019 aice_read_reg(coreid, ir0_reg_num, &ir0_value);
3020 ir0_value &= ~(0x01 << 11);
3021 aice_write_reg(coreid, ir0_reg_num, ir0_value);
3022
3023 return ERROR_OK;
3024 }
3025
3026 static int aice_usb_read_mem_b_bus(uint32_t coreid, uint32_t address, uint32_t *data)
3027 {
3028 return aice_read_mem_b(coreid, address, data);
3029 }
3030
3031 static int aice_usb_read_mem_h_bus(uint32_t coreid, uint32_t address, uint32_t *data)
3032 {
3033 return aice_read_mem_h(coreid, address, data);
3034 }
3035
3036 static int aice_usb_read_mem_w_bus(uint32_t coreid, uint32_t address, uint32_t *data)
3037 {
3038 return aice_read_mem(coreid, address, data);
3039 }
3040
3041 static int aice_usb_read_mem_b_dim(uint32_t coreid, uint32_t address, uint32_t *data)
3042 {
3043 uint32_t value;
3044 uint32_t instructions[4] = {
3045 LBI_BI(R1, R0),
3046 MTSR_DTR(R1),
3047 DSB,
3048 BEQ_MINUS_12
3049 };
3050
3051 aice_execute_dim(coreid, instructions, 4);
3052
3053 aice_read_dtr(coreid, &value);
3054 *data = value & 0xFF;
3055
3056 return ERROR_OK;
3057 }
3058
3059 static int aice_usb_read_mem_h_dim(uint32_t coreid, uint32_t address, uint32_t *data)
3060 {
3061 uint32_t value;
3062 uint32_t instructions[4] = {
3063 LHI_BI(R1, R0),
3064 MTSR_DTR(R1),
3065 DSB,
3066 BEQ_MINUS_12
3067 };
3068
3069 aice_execute_dim(coreid, instructions, 4);
3070
3071 aice_read_dtr(coreid, &value);
3072 *data = value & 0xFFFF;
3073
3074 return ERROR_OK;
3075 }
3076
3077 static int aice_usb_read_mem_w_dim(uint32_t coreid, uint32_t address, uint32_t *data)
3078 {
3079 uint32_t instructions[4] = {
3080 LWI_BI(R1, R0),
3081 MTSR_DTR(R1),
3082 DSB,
3083 BEQ_MINUS_12
3084 };
3085
3086 aice_execute_dim(coreid, instructions, 4);
3087
3088 aice_read_dtr(coreid, data);
3089
3090 return ERROR_OK;
3091 }
3092
3093 static int aice_usb_set_address_dim(uint32_t coreid, uint32_t address)
3094 {
3095 uint32_t instructions[4] = {
3096 SETHI(R0, address >> 12),
3097 ORI(R0, R0, address & 0x00000FFF),
3098 NOP,
3099 BEQ_MINUS_12
3100 };
3101
3102 return aice_execute_dim(coreid, instructions, 4);
3103 }
3104
3105 static int aice_usb_read_memory_unit(uint32_t coreid, uint32_t addr, uint32_t size,
3106 uint32_t count, uint8_t *buffer)
3107 {
3108 LOG_DEBUG("aice_usb_read_memory_unit, addr: 0x%08" PRIx32
3109 ", size: %" PRIu32 ", count: %" PRIu32 "",
3110 addr, size, count);
3111
3112 if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
3113 aice_usb_set_address_dim(coreid, addr);
3114
3115 uint32_t value;
3116 size_t i;
3117 read_mem_func_t read_mem_func;
3118
3119 switch (size) {
3120 case 1:
3121 if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
3122 read_mem_func = aice_usb_read_mem_b_bus;
3123 else
3124 read_mem_func = aice_usb_read_mem_b_dim;
3125
3126 for (i = 0; i < count; i++) {
3127 read_mem_func(coreid, addr, &value);
3128 *buffer++ = (uint8_t)value;
3129 addr++;
3130 }
3131 break;
3132 case 2:
3133 if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
3134 read_mem_func = aice_usb_read_mem_h_bus;
3135 else
3136 read_mem_func = aice_usb_read_mem_h_dim;
3137
3138 for (i = 0; i < count; i++) {
3139 read_mem_func(coreid, addr, &value);
3140 uint16_t svalue = value;
3141 memcpy(buffer, &svalue, sizeof(uint16_t));
3142 buffer += 2;
3143 addr += 2;
3144 }
3145 break;
3146 case 4:
3147 if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
3148 read_mem_func = aice_usb_read_mem_w_bus;
3149 else
3150 read_mem_func = aice_usb_read_mem_w_dim;
3151
3152 for (i = 0; i < count; i++) {
3153 read_mem_func(coreid, addr, &value);
3154 memcpy(buffer, &value, sizeof(uint32_t));
3155 buffer += 4;
3156 addr += 4;
3157 }
3158 break;
3159 }
3160
3161 return ERROR_OK;
3162 }
3163
3164 static int aice_usb_write_mem_b_bus(uint32_t coreid, uint32_t address, uint32_t data)
3165 {
3166 return aice_write_mem_b(coreid, address, data);
3167 }
3168
3169 static int aice_usb_write_mem_h_bus(uint32_t coreid, uint32_t address, uint32_t data)
3170 {
3171 return aice_write_mem_h(coreid, address, data);
3172 }
3173
3174 static int aice_usb_write_mem_w_bus(uint32_t coreid, uint32_t address, uint32_t data)
3175 {
3176 return aice_write_mem(coreid, address, data);
3177 }
3178
3179 static int aice_usb_write_mem_b_dim(uint32_t coreid, uint32_t address, uint32_t data)
3180 {
3181 uint32_t instructions[4] = {
3182 MFSR_DTR(R1),
3183 SBI_BI(R1, R0),
3184 DSB,
3185 BEQ_MINUS_12
3186 };
3187
3188 aice_write_dtr(coreid, data & 0xFF);
3189 aice_execute_dim(coreid, instructions, 4);
3190
3191 return ERROR_OK;
3192 }
3193
3194 static int aice_usb_write_mem_h_dim(uint32_t coreid, uint32_t address, uint32_t data)
3195 {
3196 uint32_t instructions[4] = {
3197 MFSR_DTR(R1),
3198 SHI_BI(R1, R0),
3199 DSB,
3200 BEQ_MINUS_12
3201 };
3202
3203 aice_write_dtr(coreid, data & 0xFFFF);
3204 aice_execute_dim(coreid, instructions, 4);
3205
3206 return ERROR_OK;
3207 }
3208
3209 static int aice_usb_write_mem_w_dim(uint32_t coreid, uint32_t address, uint32_t data)
3210 {
3211 uint32_t instructions[4] = {
3212 MFSR_DTR(R1),
3213 SWI_BI(R1, R0),
3214 DSB,
3215 BEQ_MINUS_12
3216 };
3217
3218 aice_write_dtr(coreid, data);
3219 aice_execute_dim(coreid, instructions, 4);
3220
3221 return ERROR_OK;
3222 }
3223
3224 static int aice_usb_write_memory_unit(uint32_t coreid, uint32_t addr, uint32_t size,
3225 uint32_t count, const uint8_t *buffer)
3226 {
3227 LOG_DEBUG("aice_usb_write_memory_unit, addr: 0x%08" PRIx32
3228 ", size: %" PRIu32 ", count: %" PRIu32 "",
3229 addr, size, count);
3230
3231 if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
3232 aice_usb_set_address_dim(coreid, addr);
3233
3234 size_t i;
3235 write_mem_func_t write_mem_func;
3236
3237 switch (size) {
3238 case 1:
3239 if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
3240 write_mem_func = aice_usb_write_mem_b_bus;
3241 else
3242 write_mem_func = aice_usb_write_mem_b_dim;
3243
3244 for (i = 0; i < count; i++) {
3245 write_mem_func(coreid, addr, *buffer);
3246 buffer++;
3247 addr++;
3248 }
3249 break;
3250 case 2:
3251 if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
3252 write_mem_func = aice_usb_write_mem_h_bus;
3253 else
3254 write_mem_func = aice_usb_write_mem_h_dim;
3255
3256 for (i = 0; i < count; i++) {
3257 uint16_t value;
3258 memcpy(&value, buffer, sizeof(uint16_t));
3259
3260 write_mem_func(coreid, addr, value);
3261 buffer += 2;
3262 addr += 2;
3263 }
3264 break;
3265 case 4:
3266 if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
3267 write_mem_func = aice_usb_write_mem_w_bus;
3268 else
3269 write_mem_func = aice_usb_write_mem_w_dim;
3270
3271 for (i = 0; i < count; i++) {
3272 uint32_t value;
3273 memcpy(&value, buffer, sizeof(uint32_t));
3274
3275 write_mem_func(coreid, addr, value);
3276 buffer += 4;
3277 addr += 4;
3278 }
3279 break;
3280 }
3281
3282 return ERROR_OK;
3283 }
3284
3285 static int aice_bulk_read_mem(uint32_t coreid, uint32_t addr, uint32_t count,
3286 uint8_t *buffer)
3287 {
3288 uint32_t packet_size;
3289
3290 while (count > 0) {
3291 packet_size = (count >= 0x100) ? 0x100 : count;
3292
3293 /** set address */
3294 addr &= 0xFFFFFFFC;
3295 if (aice_write_misc(coreid, NDS_EDM_MISC_SBAR, addr) != ERROR_OK)
3296 return ERROR_FAIL;
3297
3298 if (aice_fastread_mem(coreid, buffer,
3299 packet_size) != ERROR_OK)
3300 return ERROR_FAIL;
3301
3302 buffer += (packet_size * 4);
3303 addr += (packet_size * 4);
3304 count -= packet_size;
3305 }
3306
3307 return ERROR_OK;
3308 }
3309
3310 static int aice_bulk_write_mem(uint32_t coreid, uint32_t addr, uint32_t count,
3311 const uint8_t *buffer)
3312 {
3313 uint32_t packet_size;
3314
3315 while (count > 0) {
3316 packet_size = (count >= 0x100) ? 0x100 : count;
3317
3318 /** set address */
3319 addr &= 0xFFFFFFFC;
3320 if (aice_write_misc(coreid, NDS_EDM_MISC_SBAR, addr | 1) != ERROR_OK)
3321 return ERROR_FAIL;
3322
3323 if (aice_fastwrite_mem(coreid, buffer,
3324 packet_size) != ERROR_OK)
3325 return ERROR_FAIL;
3326
3327 buffer += (packet_size * 4);
3328 addr += (packet_size * 4);
3329 count -= packet_size;
3330 }
3331
3332 return ERROR_OK;
3333 }
3334
3335 static int aice_usb_bulk_read_mem(uint32_t coreid, uint32_t addr,
3336 uint32_t length, uint8_t *buffer)
3337 {
3338 LOG_DEBUG("aice_usb_bulk_read_mem, addr: 0x%08" PRIx32 ", length: 0x%08" PRIx32, addr, length);
3339
3340 int retval;
3341
3342 if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
3343 aice_usb_set_address_dim(coreid, addr);
3344
3345 if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
3346 retval = aice_usb_read_memory_unit(coreid, addr, 4, length / 4, buffer);
3347 else
3348 retval = aice_bulk_read_mem(coreid, addr, length / 4, buffer);
3349
3350 return retval;
3351 }
3352
3353 static int aice_usb_bulk_write_mem(uint32_t coreid, uint32_t addr,
3354 uint32_t length, const uint8_t *buffer)
3355 {
3356 LOG_DEBUG("aice_usb_bulk_write_mem, addr: 0x%08" PRIx32 ", length: 0x%08" PRIx32, addr, length);
3357
3358 int retval;
3359
3360 if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
3361 aice_usb_set_address_dim(coreid, addr);
3362
3363 if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
3364 retval = aice_usb_write_memory_unit(coreid, addr, 4, length / 4, buffer);
3365 else
3366 retval = aice_bulk_write_mem(coreid, addr, length / 4, buffer);
3367
3368 return retval;
3369 }
3370
3371 static int aice_usb_read_debug_reg(uint32_t coreid, uint32_t addr, uint32_t *val)
3372 {
3373 if (AICE_TARGET_HALTED == core_info[coreid].core_state) {
3374 if (NDS_EDM_SR_EDMSW == addr) {
3375 *val = core_info[coreid].edmsw_backup;
3376 } else if (NDS_EDM_SR_EDM_DTR == addr) {
3377 if (core_info[coreid].target_dtr_valid) {
3378 /* if EDM_DTR has read out, clear it. */
3379 *val = core_info[coreid].target_dtr_backup;
3380 core_info[coreid].edmsw_backup &= (~0x1);
3381 core_info[coreid].target_dtr_valid = false;
3382 } else {
3383 *val = 0;
3384 }
3385 }
3386 }
3387
3388 return aice_read_edmsr(coreid, addr, val);
3389 }
3390
3391 static int aice_usb_write_debug_reg(uint32_t coreid, uint32_t addr, const uint32_t val)
3392 {
3393 if (AICE_TARGET_HALTED == core_info[coreid].core_state) {
3394 if (NDS_EDM_SR_EDM_DTR == addr) {
3395 core_info[coreid].host_dtr_backup = val;
3396 core_info[coreid].edmsw_backup |= 0x2;
3397 core_info[coreid].host_dtr_valid = true;
3398 }
3399 }
3400
3401 return aice_write_edmsr(coreid, addr, val);
3402 }
3403
3404 static int aice_usb_memory_access(uint32_t coreid, enum nds_memory_access channel)
3405 {
3406 LOG_DEBUG("aice_usb_memory_access, access channel: %u", channel);
3407
3408 core_info[coreid].access_channel = channel;
3409
3410 return ERROR_OK;
3411 }
3412
3413 static int aice_usb_memory_mode(uint32_t coreid, enum nds_memory_select mem_select)
3414 {
3415 if (core_info[coreid].memory_select == mem_select)
3416 return ERROR_OK;
3417
3418 LOG_DEBUG("aice_usb_memory_mode, memory select: %u", mem_select);
3419
3420 core_info[coreid].memory_select = mem_select;
3421
3422 if (NDS_MEMORY_SELECT_AUTO != core_info[coreid].memory_select)
3423 aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL,
3424 core_info[coreid].memory_select - 1);
3425 else
3426 aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL,
3427 NDS_MEMORY_SELECT_MEM - 1);
3428
3429 return ERROR_OK;
3430 }
3431
3432 static int aice_usb_read_tlb(uint32_t coreid, target_addr_t virtual_address,
3433 target_addr_t *physical_address)
3434 {
3435 LOG_DEBUG("aice_usb_read_tlb, virtual address: 0x%08" TARGET_PRIxADDR, virtual_address);
3436
3437 uint32_t instructions[4];
3438 uint32_t probe_result;
3439 uint32_t value_mr3;
3440 uint32_t value_mr4;
3441 uint32_t access_page_size;
3442 uint32_t virtual_offset;
3443 uint32_t physical_page_number;
3444
3445 aice_write_dtr(coreid, virtual_address);
3446
3447 /* probe TLB first */
3448 instructions[0] = MFSR_DTR(R0);
3449 instructions[1] = TLBOP_TARGET_PROBE(R1, R0);
3450 instructions[2] = DSB;
3451 instructions[3] = BEQ_MINUS_12;
3452 aice_execute_dim(coreid, instructions, 4);
3453
3454 aice_read_reg(coreid, R1, &probe_result);
3455
3456 if (probe_result & 0x80000000)
3457 return ERROR_FAIL;
3458
3459 /* read TLB entry */
3460 aice_write_dtr(coreid, probe_result & 0x7FF);
3461
3462 /* probe TLB first */
3463 instructions[0] = MFSR_DTR(R0);
3464 instructions[1] = TLBOP_TARGET_READ(R0);
3465 instructions[2] = DSB;
3466 instructions[3] = BEQ_MINUS_12;
3467 aice_execute_dim(coreid, instructions, 4);
3468
3469 /* TODO: it should backup mr3, mr4 */
3470 aice_read_reg(coreid, MR3, &value_mr3);
3471 aice_read_reg(coreid, MR4, &value_mr4);
3472
3473 access_page_size = value_mr4 & 0xF;
3474 if (0 == access_page_size) { /* 4K page */
3475 virtual_offset = virtual_address & 0x00000FFF;
3476 physical_page_number = value_mr3 & 0xFFFFF000;
3477 } else if (1 == access_page_size) { /* 8K page */
3478 virtual_offset = virtual_address & 0x00001FFF;
3479 physical_page_number = value_mr3 & 0xFFFFE000;
3480 } else if (5 == access_page_size) { /* 1M page */
3481 virtual_offset = virtual_address & 0x000FFFFF;
3482 physical_page_number = value_mr3 & 0xFFF00000;
3483 } else {
3484 return ERROR_FAIL;
3485 }
3486
3487 *physical_address = physical_page_number | virtual_offset;
3488
3489 return ERROR_OK;
3490 }
3491
3492 static int aice_usb_init_cache(uint32_t coreid)
3493 {
3494 LOG_DEBUG("aice_usb_init_cache");
3495
3496 uint32_t value_cr1;
3497 uint32_t value_cr2;
3498
3499 aice_read_reg(coreid, CR1, &value_cr1);
3500 aice_read_reg(coreid, CR2, &value_cr2);
3501
3502 struct cache_info *icache = &core_info[coreid].icache;
3503
3504 icache->set = value_cr1 & 0x7;
3505 icache->log2_set = icache->set + 6;
3506 icache->set = 64 << icache->set;
3507 icache->way = ((value_cr1 >> 3) & 0x7) + 1;
3508 icache->line_size = (value_cr1 >> 6) & 0x7;
3509 if (icache->line_size != 0) {
3510 icache->log2_line_size = icache->line_size + 2;
3511 icache->line_size = 8 << (icache->line_size - 1);
3512 } else {
3513 icache->log2_line_size = 0;
3514 }
3515
3516 LOG_DEBUG("\ticache set: %" PRIu32 ", way: %" PRIu32 ", line size: %" PRIu32 ", "
3517 "log2(set): %" PRIu32 ", log2(line_size): %" PRIu32 "",
3518 icache->set, icache->way, icache->line_size,
3519 icache->log2_set, icache->log2_line_size);
3520
3521 struct cache_info *dcache = &core_info[coreid].dcache;
3522
3523 dcache->set = value_cr2 & 0x7;
3524 dcache->log2_set = dcache->set + 6;
3525 dcache->set = 64 << dcache->set;
3526 dcache->way = ((value_cr2 >> 3) & 0x7) + 1;
3527 dcache->line_size = (value_cr2 >> 6) & 0x7;
3528 if (dcache->line_size != 0) {
3529 dcache->log2_line_size = dcache->line_size + 2;
3530 dcache->line_size = 8 << (dcache->line_size - 1);
3531 } else {
3532 dcache->log2_line_size = 0;
3533 }
3534
3535 LOG_DEBUG("\tdcache set: %" PRIu32 ", way: %" PRIu32 ", line size: %" PRIu32 ", "
3536 "log2(set): %" PRIu32 ", log2(line_size): %" PRIu32 "",
3537 dcache->set, dcache->way, dcache->line_size,
3538 dcache->log2_set, dcache->log2_line_size);
3539
3540 core_info[coreid].cache_init = true;
3541
3542 return ERROR_OK;
3543 }
3544
3545 static int aice_usb_dcache_inval_all(uint32_t coreid)
3546 {
3547 LOG_DEBUG("aice_usb_dcache_inval_all");
3548
3549 uint32_t set_index;
3550 uint32_t way_index;
3551 uint32_t cache_index;
3552 uint32_t instructions[4];
3553
3554 instructions[0] = MFSR_DTR(R0);
3555 instructions[1] = L1D_IX_INVAL(R0);
3556 instructions[2] = DSB;
3557 instructions[3] = BEQ_MINUS_12;
3558
3559 struct cache_info *dcache = &core_info[coreid].dcache;
3560
3561 for (set_index = 0; set_index < dcache->set; set_index++) {
3562 for (way_index = 0; way_index < dcache->way; way_index++) {
3563 cache_index = (way_index << (dcache->log2_set + dcache->log2_line_size)) |
3564 (set_index << dcache->log2_line_size);
3565
3566 if (ERROR_OK != aice_write_dtr(coreid, cache_index))
3567 return ERROR_FAIL;
3568
3569 if (ERROR_OK != aice_execute_dim(coreid, instructions, 4))
3570 return ERROR_FAIL;
3571 }
3572 }
3573
3574 return ERROR_OK;
3575 }
3576
3577 static int aice_usb_dcache_va_inval(uint32_t coreid, uint32_t address)
3578 {
3579 LOG_DEBUG("aice_usb_dcache_va_inval");
3580
3581 uint32_t instructions[4];
3582
3583 aice_write_dtr(coreid, address);
3584
3585 instructions[0] = MFSR_DTR(R0);
3586 instructions[1] = L1D_VA_INVAL(R0);
3587 instructions[2] = DSB;
3588 instructions[3] = BEQ_MINUS_12;
3589
3590 return aice_execute_dim(coreid, instructions, 4);
3591 }
3592
3593 static int aice_usb_dcache_wb_all(uint32_t coreid)
3594 {
3595 LOG_DEBUG("aice_usb_dcache_wb_all");
3596
3597 uint32_t set_index;
3598 uint32_t way_index;
3599 uint32_t cache_index;
3600 uint32_t instructions[4];
3601
3602 instructions[0] = MFSR_DTR(R0);
3603 instructions[1] = L1D_IX_WB(R0);
3604 instructions[2] = DSB;
3605 instructions[3] = BEQ_MINUS_12;
3606
3607 struct cache_info *dcache = &core_info[coreid].dcache;
3608
3609 for (set_index = 0; set_index < dcache->set; set_index++) {
3610 for (way_index = 0; way_index < dcache->way; way_index++) {
3611 cache_index = (way_index << (dcache->log2_set + dcache->log2_line_size)) |
3612 (set_index << dcache->log2_line_size);
3613
3614 if (ERROR_OK != aice_write_dtr(coreid, cache_index))
3615 return ERROR_FAIL;
3616
3617 if (ERROR_OK != aice_execute_dim(coreid, instructions, 4))
3618 return ERROR_FAIL;
3619 }
3620 }
3621
3622 return ERROR_OK;
3623 }
3624
3625 static int aice_usb_dcache_va_wb(uint32_t coreid, uint32_t address)
3626 {
3627 LOG_DEBUG("aice_usb_dcache_va_wb");
3628
3629 uint32_t instructions[4];
3630
3631 aice_write_dtr(coreid, address);
3632
3633 instructions[0] = MFSR_DTR(R0);
3634 instructions[1] = L1D_VA_WB(R0);
3635 instructions[2] = DSB;
3636 instructions[3] = BEQ_MINUS_12;
3637
3638 return aice_execute_dim(coreid, instructions, 4);
3639 }
3640
3641 static int aice_usb_icache_inval_all(uint32_t coreid)
3642 {
3643 LOG_DEBUG("aice_usb_icache_inval_all");
3644
3645 uint32_t set_index;
3646 uint32_t way_index;
3647 uint32_t cache_index;
3648 uint32_t instructions[4];
3649
3650 instructions[0] = MFSR_DTR(R0);
3651 instructions[1] = L1I_IX_INVAL(R0);
3652 instructions[2] = ISB;
3653 instructions[3] = BEQ_MINUS_12;
3654
3655 struct cache_info *icache = &core_info[coreid].icache;
3656
3657 for (set_index = 0; set_index < icache->set; set_index++) {
3658 for (way_index = 0; way_index < icache->way; way_index++) {
3659 cache_index = (way_index << (icache->log2_set + icache->log2_line_size)) |
3660 (set_index << icache->log2_line_size);
3661
3662 if (ERROR_OK != aice_write_dtr(coreid, cache_index))
3663 return ERROR_FAIL;
3664
3665 if (ERROR_OK != aice_execute_dim(coreid, instructions, 4))
3666 return ERROR_FAIL;
3667 }
3668 }
3669
3670 return ERROR_OK;
3671 }
3672
3673 static int aice_usb_icache_va_inval(uint32_t coreid, uint32_t address)
3674 {
3675 LOG_DEBUG("aice_usb_icache_va_inval");
3676
3677 uint32_t instructions[4];
3678
3679 aice_write_dtr(coreid, address);
3680
3681 instructions[0] = MFSR_DTR(R0);
3682 instructions[1] = L1I_VA_INVAL(R0);
3683 instructions[2] = ISB;
3684 instructions[3] = BEQ_MINUS_12;
3685
3686 return aice_execute_dim(coreid, instructions, 4);
3687 }
3688
3689 static int aice_usb_cache_ctl(uint32_t coreid, uint32_t subtype, uint32_t address)
3690 {
3691 LOG_DEBUG("aice_usb_cache_ctl");
3692
3693 int result;
3694
3695 if (core_info[coreid].cache_init == false)
3696 aice_usb_init_cache(coreid);
3697
3698 switch (subtype) {
3699 case AICE_CACHE_CTL_L1D_INVALALL:
3700 result = aice_usb_dcache_inval_all(coreid);
3701 break;
3702 case AICE_CACHE_CTL_L1D_VA_INVAL:
3703 result = aice_usb_dcache_va_inval(coreid, address);
3704 break;
3705 case AICE_CACHE_CTL_L1D_WBALL:
3706 result = aice_usb_dcache_wb_all(coreid);
3707 break;
3708 case AICE_CACHE_CTL_L1D_VA_WB:
3709 result = aice_usb_dcache_va_wb(coreid, address);
3710 break;
3711 case AICE_CACHE_CTL_L1I_INVALALL:
3712 result = aice_usb_icache_inval_all(coreid);
3713 break;
3714 case AICE_CACHE_CTL_L1I_VA_INVAL:
3715 result = aice_usb_icache_va_inval(coreid, address);
3716 break;
3717 default:
3718 result = ERROR_FAIL;
3719 break;
3720 }
3721
3722 return result;
3723 }
3724
3725 static int aice_usb_set_retry_times(uint32_t a_retry_times)
3726 {
3727 aice_max_retry_times = a_retry_times;
3728 return ERROR_OK;
3729 }
3730
3731 static int aice_usb_program_edm(uint32_t coreid, char *command_sequence)
3732 {
3733 char *command_str;
3734 char *reg_name_0;
3735 char *reg_name_1;
3736 uint32_t data_value;
3737 int i;
3738
3739 /* init strtok() */
3740 command_str = strtok(command_sequence, ";");
3741 if (command_str == NULL)
3742 return ERROR_OK;
3743
3744 do {
3745 i = 0;
3746 /* process one command */
3747 while (command_str[i] == ' ' ||
3748 command_str[i] == '\n' ||
3749 command_str[i] == '\r' ||
3750 command_str[i] == '\t')
3751 i++;
3752
3753 /* skip ' ', '\r', '\n', '\t' */
3754 command_str = command_str + i;
3755
3756 if (strncmp(command_str, "write_misc", 10) == 0) {
3757 reg_name_0 = strstr(command_str, "gen_port0");
3758 reg_name_1 = strstr(command_str, "gen_port1");
3759
3760 if (reg_name_0 != NULL) {
3761 data_value = strtoul(reg_name_0 + 9, NULL, 0);
3762
3763 if (aice_write_misc(coreid,
3764 NDS_EDM_MISC_GEN_PORT0, data_value) != ERROR_OK)
3765 return ERROR_FAIL;
3766
3767 } else if (reg_name_1 != NULL) {
3768 data_value = strtoul(reg_name_1 + 9, NULL, 0);
3769
3770 if (aice_write_misc(coreid,
3771 NDS_EDM_MISC_GEN_PORT1, data_value) != ERROR_OK)
3772 return ERROR_FAIL;
3773 } else {
3774 LOG_ERROR("program EDM, unsupported misc register: %s", command_str);
3775 }
3776 } else {
3777 LOG_ERROR("program EDM, unsupported command: %s", command_str);
3778 }
3779
3780 /* update command_str */
3781 command_str = strtok(NULL, ";");
3782
3783 } while (command_str != NULL);
3784
3785 return ERROR_OK;
3786 }
3787
3788 static int aice_usb_set_command_mode(enum aice_command_mode command_mode)
3789 {
3790 int retval = ERROR_OK;
3791
3792 /* flush usb_packets_buffer as users change mode */
3793 retval = aice_usb_packet_flush();
3794
3795 if (AICE_COMMAND_MODE_BATCH == command_mode) {
3796 /* reset batch buffer */
3797 aice_command_mode = AICE_COMMAND_MODE_NORMAL;
3798 retval = aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL, 0x40000);
3799 }
3800
3801 aice_command_mode = command_mode;
3802
3803 return retval;
3804 }
3805
3806 static int aice_usb_execute(uint32_t coreid, uint32_t *instructions,
3807 uint32_t instruction_num)
3808 {
3809 uint32_t i, j;
3810 uint8_t current_instruction_num;
3811 uint32_t dim_instructions[4] = {NOP, NOP, NOP, BEQ_MINUS_12};
3812
3813 /* To execute 4 instructions as a special case */
3814 if (instruction_num == 4)
3815 return aice_execute_dim(coreid, instructions, 4);
3816
3817 for (i = 0 ; i < instruction_num ; i += 3) {
3818 if (instruction_num - i < 3) {
3819 current_instruction_num = instruction_num - i;
3820 for (j = current_instruction_num ; j < 3 ; j++)
3821 dim_instructions[j] = NOP;
3822 } else {
3823 current_instruction_num = 3;
3824 }
3825
3826 memcpy(dim_instructions, instructions + i,
3827 current_instruction_num * sizeof(uint32_t));
3828
3829 /** fill DIM */
3830 if (aice_write_dim(coreid,
3831 dim_instructions,
3832 4) != ERROR_OK)
3833 return ERROR_FAIL;
3834
3835 /** clear DBGER.DPED */
3836 if (aice_write_misc(coreid,
3837 NDS_EDM_MISC_DBGER, NDS_DBGER_DPED) != ERROR_OK)
3838 return ERROR_FAIL;
3839
3840 /** execute DIM */
3841 if (aice_do_execute(coreid) != ERROR_OK)
3842 return ERROR_FAIL;
3843
3844 /** check DBGER.DPED */
3845 if (aice_check_dbger(coreid, NDS_DBGER_DPED) != ERROR_OK) {
3846
3847 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly:"
3848 "0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 ". -->",
3849 dim_instructions[0],
3850 dim_instructions[1],
3851 dim_instructions[2],
3852 dim_instructions[3]);
3853 return ERROR_FAIL;
3854 }
3855 }
3856
3857 return ERROR_OK;
3858 }
3859
3860 static int aice_usb_set_custom_srst_script(const char *script)
3861 {
3862 custom_srst_script = strdup(script);
3863
3864 return ERROR_OK;
3865 }
3866
3867 static int aice_usb_set_custom_trst_script(const char *script)
3868 {
3869 custom_trst_script = strdup(script);
3870
3871 return ERROR_OK;
3872 }
3873
3874 static int aice_usb_set_custom_restart_script(const char *script)
3875 {
3876 custom_restart_script = strdup(script);
3877
3878 return ERROR_OK;
3879 }
3880
3881 static int aice_usb_set_count_to_check_dbger(uint32_t count_to_check)
3882 {
3883 aice_count_to_check_dbger = count_to_check;
3884
3885 return ERROR_OK;
3886 }
3887
3888 static int aice_usb_set_data_endian(uint32_t coreid,
3889 enum aice_target_endian target_data_endian)
3890 {
3891 data_endian = target_data_endian;
3892
3893 return ERROR_OK;
3894 }
3895
3896 static int fill_profiling_batch_commands(uint32_t coreid, uint32_t reg_no)
3897 {
3898 uint32_t dim_instructions[4];
3899
3900 aice_usb_set_command_mode(AICE_COMMAND_MODE_BATCH);
3901
3902 /* halt */
3903 if (aice_write_misc(coreid, NDS_EDM_MISC_EDM_CMDR, 0) != ERROR_OK)
3904 return ERROR_FAIL;
3905
3906 /* backup $r0 */
3907 dim_instructions[0] = MTSR_DTR(0);
3908 dim_instructions[1] = DSB;
3909 dim_instructions[2] = NOP;
3910 dim_instructions[3] = BEQ_MINUS_12;
3911 if (aice_write_dim(coreid, dim_instructions, 4) != ERROR_OK)
3912 return ERROR_FAIL;
3913 aice_read_dtr_to_buffer(coreid, AICE_BATCH_DATA_BUFFER_0);
3914
3915 /* get samples */
3916 if (NDS32_REG_TYPE_GPR == nds32_reg_type(reg_no)) {
3917 /* general registers */
3918 dim_instructions[0] = MTSR_DTR(reg_no);
3919 dim_instructions[1] = DSB;
3920 dim_instructions[2] = NOP;
3921 dim_instructions[3] = BEQ_MINUS_12;
3922 } else if (NDS32_REG_TYPE_SPR == nds32_reg_type(reg_no)) {
3923 /* user special registers */
3924 dim_instructions[0] = MFUSR_G0(0, nds32_reg_sr_index(reg_no));
3925 dim_instructions[1] = MTSR_DTR(0);
3926 dim_instructions[2] = DSB;
3927 dim_instructions[3] = BEQ_MINUS_12;
3928 } else { /* system registers */
3929 dim_instructions[0] = MFSR(0, nds32_reg_sr_index(reg_no));
3930 dim_instructions[1] = MTSR_DTR(0);
3931 dim_instructions[2] = DSB;
3932 dim_instructions[3] = BEQ_MINUS_12;
3933 }
3934 if (aice_write_dim(coreid, dim_instructions, 4) != ERROR_OK)
3935 return ERROR_FAIL;
3936 aice_read_dtr_to_buffer(coreid, AICE_BATCH_DATA_BUFFER_1);
3937
3938 /* restore $r0 */
3939 aice_write_dtr_from_buffer(coreid, AICE_BATCH_DATA_BUFFER_0);
3940 dim_instructions[0] = MFSR_DTR(0);
3941 dim_instructions[1] = DSB;
3942 dim_instructions[2] = NOP;
3943 dim_instructions[3] = IRET; /* free run */
3944 if (aice_write_dim(coreid, dim_instructions, 4) != ERROR_OK)
3945 return ERROR_FAIL;
3946
3947 aice_command_mode = AICE_COMMAND_MODE_NORMAL;
3948
3949 /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */
3950 if (aice_batch_buffer_write(AICE_BATCH_COMMAND_BUFFER_0,
3951 usb_out_packets_buffer,
3952 (usb_out_packets_buffer_length + 3) / 4) != ERROR_OK)
3953 return ERROR_FAIL;
3954
3955 usb_out_packets_buffer_length = 0;
3956 usb_in_packets_buffer_length = 0;
3957
3958 return ERROR_OK;
3959 }
3960
3961 static int aice_usb_profiling(uint32_t coreid, uint32_t interval, uint32_t iteration,
3962 uint32_t reg_no, uint32_t *samples, uint32_t *num_samples)
3963 {
3964 uint32_t iteration_count;
3965 uint32_t this_iteration;
3966 int retval = ERROR_OK;
3967 const uint32_t MAX_ITERATION = 250;
3968
3969 *num_samples = 0;
3970
3971 /* init DIM size */
3972 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DIM_SIZE, 4) != ERROR_OK)
3973 return ERROR_FAIL;
3974
3975 /* Use AICE_BATCH_DATA_BUFFER_0 to read/write $DTR.
3976 * Set it to circular buffer */
3977 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF0_CTRL, 0xC0000) != ERROR_OK)
3978 return ERROR_FAIL;
3979
3980 fill_profiling_batch_commands(coreid, reg_no);
3981
3982 iteration_count = 0;
3983 while (iteration_count < iteration) {
3984 if (iteration - iteration_count < MAX_ITERATION)
3985 this_iteration = iteration - iteration_count;
3986 else
3987 this_iteration = MAX_ITERATION;
3988
3989 /* set number of iterations */
3990 uint32_t val_iteration;
3991 val_iteration = interval << 16 | this_iteration;
3992 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_ITERATION,
3993 val_iteration) != ERROR_OK) {
3994 retval = ERROR_FAIL;
3995 goto end_profiling;
3996 }
3997
3998 /* init AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL to store $PC */
3999 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL,
4000 0x40000) != ERROR_OK) {
4001 retval = ERROR_FAIL;
4002 goto end_profiling;
4003 }
4004
4005 aice_usb_run(coreid);
4006
4007 /* enable BATCH command */
4008 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL,
4009 0x80000000) != ERROR_OK) {
4010 aice_usb_halt(coreid);
4011 retval = ERROR_FAIL;
4012 goto end_profiling;
4013 }
4014
4015 /* wait a while (AICE bug, workaround) */
4016 alive_sleep(this_iteration);
4017
4018 /* check status */
4019 uint32_t i;
4020 uint32_t batch_status;
4021
4022 i = 0;
4023 while (1) {
4024 aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS, &batch_status);
4025
4026 if (batch_status & 0x1) {
4027 break;
4028 } else if (batch_status & 0xE) {
4029 aice_usb_halt(coreid);
4030 retval = ERROR_FAIL;
4031 goto end_profiling;
4032 }
4033
4034 if ((i % 30) == 0)
4035 keep_alive();
4036
4037 i++;
4038 }
4039
4040 aice_usb_halt(coreid);
4041
4042 /* get samples from batch data buffer */
4043 if (aice_batch_buffer_read(AICE_BATCH_DATA_BUFFER_1,
4044 samples + iteration_count, this_iteration) != ERROR_OK) {
4045 retval = ERROR_FAIL;
4046 goto end_profiling;
4047 }
4048
4049 iteration_count += this_iteration;
4050 }
4051
4052 end_profiling:
4053 *num_samples = iteration_count;
4054
4055 return retval;
4056 }
4057
4058 /** */
4059 struct aice_port_api_s aice_usb_api = {
4060 /** */
4061 .open = aice_open_device,
4062 /** */
4063 .close = aice_usb_close,
4064 /** */
4065 .idcode = aice_usb_idcode,
4066 /** */
4067 .state = aice_usb_state,
4068 /** */
4069 .reset = aice_usb_reset,
4070 /** */
4071 .assert_srst = aice_usb_assert_srst,
4072 /** */
4073 .run = aice_usb_run,
4074 /** */
4075 .halt = aice_usb_halt,
4076 /** */
4077 .step = aice_usb_step,
4078 /** */
4079 .read_reg = aice_usb_read_reg,
4080 /** */
4081 .write_reg = aice_usb_write_reg,
4082 /** */
4083 .read_reg_64 = aice_usb_read_reg_64,
4084 /** */
4085 .write_reg_64 = aice_usb_write_reg_64,
4086 /** */
4087 .read_mem_unit = aice_usb_read_memory_unit,
4088 /** */
4089 .write_mem_unit = aice_usb_write_memory_unit,
4090 /** */
4091 .read_mem_bulk = aice_usb_bulk_read_mem,
4092 /** */
4093 .write_mem_bulk = aice_usb_bulk_write_mem,
4094 /** */
4095 .read_debug_reg = aice_usb_read_debug_reg,
4096 /** */
4097 .write_debug_reg = aice_usb_write_debug_reg,
4098 /** */
4099 .set_jtag_clock = aice_usb_set_jtag_clock,
4100 /** */
4101 .memory_access = aice_usb_memory_access,
4102 /** */
4103 .memory_mode = aice_usb_memory_mode,
4104 /** */
4105 .read_tlb = aice_usb_read_tlb,
4106 /** */
4107 .cache_ctl = aice_usb_cache_ctl,
4108 /** */
4109 .set_retry_times = aice_usb_set_retry_times,
4110 /** */
4111 .program_edm = aice_usb_program_edm,
4112 /** */
4113 .set_command_mode = aice_usb_set_command_mode,
4114 /** */
4115 .execute = aice_usb_execute,
4116 /** */
4117 .set_custom_srst_script = aice_usb_set_custom_srst_script,
4118 /** */
4119 .set_custom_trst_script = aice_usb_set_custom_trst_script,
4120 /** */
4121 .set_custom_restart_script = aice_usb_set_custom_restart_script,
4122 /** */
4123 .set_count_to_check_dbger = aice_usb_set_count_to_check_dbger,
4124 /** */
4125 .set_data_endian = aice_usb_set_data_endian,
4126 /** */
4127 .profiling = aice_usb_profiling,
4128 };
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SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)