src/jtag/aice/aice_port.h

   1 /***************************************************************************
   2  *   Copyright (C) 2013 by Andes Technology                                *
   3  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20 #ifndef _AICE_PORT_H_
  21 #define _AICE_PORT_H_
  22
  23 #include <target/nds32_edm.h>
  24
  25 #define ERROR_AICE_DISCONNECT  (-200)
  26 #define ERROR_AICE_TIMEOUT     (-201)
  27
  28 enum aice_target_state_s {
  29         AICE_DISCONNECT = 0,
  30         AICE_TARGET_DETACH,
  31         AICE_TARGET_UNKNOWN,
  32         AICE_TARGET_RUNNING,
  33         AICE_TARGET_HALTED,
  34         AICE_TARGET_RESET,
  35         AICE_TARGET_DEBUG_RUNNING,
  36 };
  37
  38 enum aice_srst_type_s {
  39         AICE_SRST = 0x1,
  40         AICE_RESET_HOLD = 0x8,
  41 };
  42
  43 enum aice_target_endian {
  44         AICE_LITTLE_ENDIAN = 0,
  45         AICE_BIG_ENDIAN,
  46 };
  47
  48 enum aice_api_s {
  49         AICE_OPEN = 0x0,
  50         AICE_CLOSE,
  51         AICE_RESET,
  52         AICE_ASSERT_SRST,
  53         AICE_RUN,
  54         AICE_HALT,
  55         AICE_STEP,
  56         AICE_READ_REG,
  57         AICE_WRITE_REG,
  58         AICE_READ_REG_64,
  59         AICE_WRITE_REG_64,
  60         AICE_READ_MEM_UNIT,
  61         AICE_WRITE_MEM_UNIT,
  62         AICE_READ_MEM_BULK,
  63         AICE_WRITE_MEM_BULK,
  64         AICE_READ_DEBUG_REG,
  65         AICE_WRITE_DEBUG_REG,
  66         AICE_IDCODE,
  67         AICE_STATE,
  68         AICE_SET_JTAG_CLOCK,
  69         AICE_SELECT_TARGET,
  70         AICE_MEMORY_ACCESS,
  71         AICE_MEMORY_MODE,
  72         AICE_READ_TLB,
  73         AICE_CACHE_CTL,
  74         AICE_SET_RETRY_TIMES,
  75         AICE_PROGRAM_EDM,
  76         AICE_PACK_COMMAND,
  77         AICE_EXECUTE,
  78         AICE_SET_CUSTOM_SRST_SCRIPT,
  79         AICE_SET_CUSTOM_TRST_SCRIPT,
  80         AICE_SET_CUSTOM_RESTART_SCRIPT,
  81         AICE_SET_COUNT_TO_CHECK_DBGER,
  82         AICE_SET_DATA_ENDIAN,
  83 };
  84
  85 enum aice_error_s {
  86         AICE_OK,
  87         AICE_ACK,
  88         AICE_ERROR,
  89 };
  90
  91 enum aice_cache_ctl_type {
  92         AICE_CACHE_CTL_L1D_INVALALL = 0,
  93         AICE_CACHE_CTL_L1D_VA_INVAL,
  94         AICE_CACHE_CTL_L1D_WBALL,
  95         AICE_CACHE_CTL_L1D_VA_WB,
  96         AICE_CACHE_CTL_L1I_INVALALL,
  97         AICE_CACHE_CTL_L1I_VA_INVAL,
  98 };
  99
 100 struct aice_port_param_s {
 101         /** */
 102         char *device_desc;
 103         /** */
 104         char *serial;
 105         /** */
 106         uint16_t vid;
 107         /** */
 108         uint16_t pid;
 109         /** */
 110         char *adapter_name;
 111 };
 112
 113 struct aice_port_s {
 114         /** */
 115         struct aice_port_param_s param;
 116         /** */
 117         const struct aice_port *port;
 118         /** */
 119         uint32_t retry_times;
 120         /** */
 121         uint32_t count_to_check_dbger;
 122 };
 123
 124 /** */
 125 extern struct aice_port_api_s aice_usb_layout_api;
 126
 127 /** */
 128 struct aice_port_api_s {
 129         /** */
 130         int (*open)(struct aice_port_param_s *param);
 131         /** */
 132         int (*close)(void);
 133         /** */
 134         int (*reset)(void);
 135         /** */
 136         int (*assert_srst)(enum aice_srst_type_s srst);
 137         /** */
 138         int (*run)(void);
 139         /** */
 140         int (*halt)(void);
 141         /** */
 142         int (*step)(void);
 143         /** */
 144         int (*read_reg)(uint32_t num, uint32_t *val);
 145         /** */
 146         int (*write_reg)(uint32_t num, uint32_t val);
 147         /** */
 148         int (*read_reg_64)(uint32_t num, uint64_t *val);
 149         /** */
 150         int (*write_reg_64)(uint32_t num, uint64_t val);
 151         /** */
 152         int (*read_mem_unit)(uint32_t addr, uint32_t size, uint32_t count,
 153                         uint8_t *buffer);
 154         /** */
 155         int (*write_mem_unit)(uint32_t addr, uint32_t size, uint32_t count,
 156                         const uint8_t *buffer);
 157         /** */
 158         int (*read_mem_bulk)(uint32_t addr, uint32_t length,
 159                         uint8_t *buffer);
 160         /** */
 161         int (*write_mem_bulk)(uint32_t addr, uint32_t length,
 162                         const uint8_t *buffer);
 163         /** */
 164         int (*read_debug_reg)(uint32_t addr, uint32_t *val);
 165         /** */
 166         int (*write_debug_reg)(uint32_t addr, const uint32_t val);
 167
 168         /** */
 169         int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
 170         /** */
 171         int (*state)(enum aice_target_state_s *state);
 172
 173         /** */
 174         int (*set_jtag_clock)(uint32_t a_clock);
 175         /** */
 176         int (*select_target)(uint32_t target_id);
 177
 178         /** */
 179         int (*memory_access)(enum nds_memory_access a_access);
 180         /** */
 181         int (*memory_mode)(enum nds_memory_select mem_select);
 182
 183         /** */
 184         int (*read_tlb)(uint32_t virtual_address, uint32_t *physical_address);
 185
 186         /** */
 187         int (*cache_ctl)(uint32_t subtype, uint32_t address);
 188
 189         /** */
 190         int (*set_retry_times)(uint32_t a_retry_times);
 191
 192         /** */
 193         int (*program_edm)(char *command_sequence);
 194
 195         /** */
 196         int (*pack_command)(bool enable_pack_command);
 197
 198         /** */
 199         int (*execute)(uint32_t *instructions, uint32_t instruction_num);
 200
 201         /** */
 202         int (*set_custom_srst_script)(const char *script);
 203
 204         /** */
 205         int (*set_custom_trst_script)(const char *script);
 206
 207         /** */
 208         int (*set_custom_restart_script)(const char *script);
 209
 210         /** */
 211         int (*set_count_to_check_dbger)(uint32_t count_to_check);
 212
 213         /** */
 214         int (*set_data_endian)(enum aice_target_endian target_data_endian);
 215 };
 216
 217 #define AICE_PORT_UNKNOWN       0
 218 #define AICE_PORT_AICE_USB      1
 219 #define AICE_PORT_AICE_PIPE     2
 220
 221 /** */
 222 struct aice_port {
 223         /** */
 224         char *name;
 225         /** */
 226         int type;
 227         /** */
 228         struct aice_port_api_s *api;
 229 };
 230
 231 /** */
 232 const struct aice_port *aice_port_get_list(void);
 233
 234 #endif