008961139f1c2d40196c2470fdbed13f57eeb8fb
[openocd.git] / src / flash / tms470.c
1 /***************************************************************************
2 * Copyright (C) 2007,2008 by Christopher Kilgour *
3 * techie |_at_| whiterocker |_dot_| com *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "log.h"
25 #include "tms470.h"
26 #include <string.h>
27 #include <unistd.h>
28
29 int tms470_register_commands(struct command_context_s *cmd_ctx);
30 int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
31 int tms470_erase(struct flash_bank_s *bank, int first, int last);
32 int tms470_protect(struct flash_bank_s *bank, int set, int first, int last);
33 int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count);
34 int tms470_probe(struct flash_bank_s *bank);
35 int tms470_auto_probe(struct flash_bank_s *bank);
36 int tms470_erase_check(struct flash_bank_s *bank);
37 int tms470_protect_check(struct flash_bank_s *bank);
38 int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size);
39
40 flash_driver_t tms470_flash = {
41 .name = "tms470",
42 .register_commands = tms470_register_commands,
43 .flash_bank_command = tms470_flash_bank_command,
44 .erase = tms470_erase,
45 .protect = tms470_protect,
46 .write = tms470_write,
47 .probe = tms470_probe,
48 .auto_probe = tms470_auto_probe,
49 .erase_check = tms470_erase_check,
50 .protect_check = tms470_protect_check,
51 .info = tms470_info
52 };
53
54 /* ----------------------------------------------------------------------
55 Internal Support, Helpers
56 ---------------------------------------------------------------------- */
57
58 const flash_sector_t TMS470R1A256_SECTORS[] = {
59 {0x00000000, 0x00002000, -1, -1},
60 {0x00002000, 0x00002000, -1, -1},
61 {0x00004000, 0x00002000, -1, -1},
62 {0x00006000, 0x00002000, -1, -1},
63 {0x00008000, 0x00008000, -1, -1},
64 {0x00010000, 0x00008000, -1, -1},
65 {0x00018000, 0x00008000, -1, -1},
66 {0x00020000, 0x00008000, -1, -1},
67 {0x00028000, 0x00008000, -1, -1},
68 {0x00030000, 0x00008000, -1, -1},
69 {0x00038000, 0x00002000, -1, -1},
70 {0x0003A000, 0x00002000, -1, -1},
71 {0x0003C000, 0x00002000, -1, -1},
72 {0x0003E000, 0x00002000, -1, -1},
73 };
74
75 #define TMS470R1A256_NUM_SECTORS \
76 (sizeof(TMS470R1A256_SECTORS)/sizeof(TMS470R1A256_SECTORS[0]))
77
78 const flash_sector_t TMS470R1A288_BANK0_SECTORS[] = {
79 {0x00000000, 0x00002000, -1, -1},
80 {0x00002000, 0x00002000, -1, -1},
81 {0x00004000, 0x00002000, -1, -1},
82 {0x00006000, 0x00002000, -1, -1},
83 };
84
85 #define TMS470R1A288_BANK0_NUM_SECTORS \
86 (sizeof(TMS470R1A288_BANK0_SECTORS)/sizeof(TMS470R1A288_BANK0_SECTORS[0]))
87
88 const flash_sector_t TMS470R1A288_BANK1_SECTORS[] = {
89 {0x00040000, 0x00010000, -1, -1},
90 {0x00050000, 0x00010000, -1, -1},
91 {0x00060000, 0x00010000, -1, -1},
92 {0x00070000, 0x00010000, -1, -1},
93 };
94
95 #define TMS470R1A288_BANK1_NUM_SECTORS \
96 (sizeof(TMS470R1A288_BANK1_SECTORS)/sizeof(TMS470R1A288_BANK1_SECTORS[0]))
97
98 /* ---------------------------------------------------------------------- */
99
100 int tms470_read_part_info(struct flash_bank_s *bank)
101 {
102 tms470_flash_bank_t *tms470_info = bank->driver_priv;
103 target_t *target = bank->target;
104 u32 device_ident_reg;
105 u32 silicon_version;
106 u32 technology_family;
107 u32 rom_flash;
108 u32 part_number;
109 char *part_name;
110
111 /* we shall not rely on the caller in this test, this function allocates memory,
112 thus and executing the code more than once may cause memory leak */
113 if (tms470_info->device_ident_reg)
114 return ERROR_OK;
115
116 /* read and parse the device identification register */
117 target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
118
119 INFO("device_ident_reg=0x%08x", device_ident_reg);
120
121 if ((device_ident_reg & 7) == 0)
122 {
123 WARNING("Cannot identify target as a TMS470 family.");
124 return ERROR_FLASH_OPERATION_FAILED;
125 }
126
127 silicon_version = (device_ident_reg >> 12) & 0xF;
128 technology_family = (device_ident_reg >> 11) & 1;
129 rom_flash = (device_ident_reg >> 10) & 1;
130 part_number = (device_ident_reg >> 3) & 0x7f;
131
132 /*
133 * If the part number is known, determine if the flash bank is valid
134 * based on the base address being within the known flash bank
135 * ranges. Then fixup/complete the remaining fields of the flash
136 * bank structure.
137 */
138 switch (part_number)
139 {
140 case 0x0a:
141 part_name = "TMS470R1A256";
142
143 if (bank->base >= 0x00040000)
144 {
145 ERROR("No %s flash bank contains base address 0x%08x.", part_name, bank->base);
146 return ERROR_FLASH_OPERATION_FAILED;
147 }
148 tms470_info->ordinal = 0;
149 bank->base = 0x00000000;
150 bank->size = 256 * 1024;
151 bank->num_sectors = TMS470R1A256_NUM_SECTORS;
152 bank->sectors = malloc(sizeof(TMS470R1A256_SECTORS));
153 if (!bank->sectors)
154 {
155 return ERROR_FLASH_OPERATION_FAILED;
156 }
157 (void)memcpy(bank->sectors, TMS470R1A256_SECTORS, sizeof(TMS470R1A256_SECTORS));
158 break;
159
160 case 0x2b:
161 part_name = "TMS470R1A288";
162
163 if ((bank->base >= 0x00000000) && (bank->base < 0x00008000))
164 {
165 tms470_info->ordinal = 0;
166 bank->base = 0x00000000;
167 bank->size = 32 * 1024;
168 bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS;
169 bank->sectors = malloc(sizeof(TMS470R1A288_BANK0_SECTORS));
170 if (!bank->sectors)
171 {
172 return ERROR_FLASH_OPERATION_FAILED;
173 }
174 (void)memcpy(bank->sectors, TMS470R1A288_BANK0_SECTORS, sizeof(TMS470R1A288_BANK0_SECTORS));
175 }
176 else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000))
177 {
178 tms470_info->ordinal = 1;
179 bank->base = 0x00040000;
180 bank->size = 256 * 1024;
181 bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS;
182 bank->sectors = malloc(sizeof(TMS470R1A288_BANK1_SECTORS));
183 if (!bank->sectors)
184 {
185 return ERROR_FLASH_OPERATION_FAILED;
186 }
187 (void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS, sizeof(TMS470R1A288_BANK1_SECTORS));
188 }
189 else
190 {
191 ERROR("No %s flash bank contains base address 0x%08x.", part_name, bank->base);
192 return ERROR_FLASH_OPERATION_FAILED;
193 }
194 break;
195
196 default:
197 WARNING("Could not identify part 0x%02x as a member of the TMS470 family.", part_number);
198 return ERROR_FLASH_OPERATION_FAILED;
199 }
200
201 /* turn off memory selects */
202 target_write_u32(target, 0xFFFFFFE4, 0x00000000);
203 target_write_u32(target, 0xFFFFFFE0, 0x00000000);
204
205 bank->chip_width = 32;
206 bank->bus_width = 32;
207
208 INFO("Identified %s, ver=%d, core=%s, nvmem=%s.", part_name, silicon_version, (technology_family ? "1.8v" : "3.3v"), (rom_flash ? "rom" : "flash"));
209
210 tms470_info->device_ident_reg = device_ident_reg;
211 tms470_info->silicon_version = silicon_version;
212 tms470_info->technology_family = technology_family;
213 tms470_info->rom_flash = rom_flash;
214 tms470_info->part_number = part_number;
215 tms470_info->part_name = part_name;
216
217 /*
218 * Disable reset on address access violation.
219 */
220 target_write_u32(target, 0xFFFFFFE0, 0x00004007);
221
222 return ERROR_OK;
223 }
224
225 /* ---------------------------------------------------------------------- */
226
227 u32 keysSet = 0;
228 u32 flashKeys[4];
229
230 int tms470_handle_flash_keyset_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
231 {
232 if (argc > 4)
233 {
234 command_print(cmd_ctx, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
235 return ERROR_INVALID_ARGUMENTS;
236 }
237 else if (argc == 4)
238 {
239 int i;
240
241 for (i = 0; i < 4; i++)
242 {
243 int start = (0 == strncmp(args[i], "0x", 2)) ? 2 : 0;
244
245 if (1 != sscanf(&args[i][start], "%x", &flashKeys[i]))
246 {
247 command_print(cmd_ctx, "could not process flash key %s", args[i]);
248 ERROR("could not process flash key %s", args[i]);
249 return ERROR_INVALID_ARGUMENTS;
250 }
251 }
252
253 keysSet = 1;
254 }
255 else if (argc != 0)
256 {
257 command_print(cmd_ctx, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
258 return ERROR_INVALID_ARGUMENTS;
259 }
260
261 if (keysSet)
262 {
263 command_print(cmd_ctx, "using flash keys 0x%08x, 0x%08x, 0x%08x, 0x%08x", flashKeys[0], flashKeys[1], flashKeys[2], flashKeys[3]);
264 }
265 else
266 {
267 command_print(cmd_ctx, "flash keys not set");
268 }
269
270 return ERROR_OK;
271 }
272
273 const u32 FLASH_KEYS_ALL_ONES[] = { 0xFFFFFFFF, 0xFFFFFFFF,
274 0xFFFFFFFF, 0xFFFFFFFF,
275 };
276
277 const u32 FLASH_KEYS_ALL_ZEROS[] = { 0x00000000, 0x00000000,
278 0x00000000, 0x00000000,
279 };
280
281 const u32 FLASH_KEYS_MIX1[] = { 0xf0fff0ff, 0xf0fff0ff,
282 0xf0fff0ff, 0xf0fff0ff
283 };
284
285 const u32 FLASH_KEYS_MIX2[] = { 0x0000ffff, 0x0000ffff,
286 0x0000ffff, 0x0000ffff
287 };
288
289 /* ---------------------------------------------------------------------- */
290
291 int oscMHz = 12;
292
293 int tms470_handle_osc_megahertz_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
294 {
295 if (argc > 1)
296 {
297 command_print(cmd_ctx, "tms470 osc_megahertz <MHz>");
298 return ERROR_INVALID_ARGUMENTS;
299 }
300 else if (argc == 1)
301 {
302 sscanf(args[0], "%d", &oscMHz);
303 }
304
305 if (oscMHz <= 0)
306 {
307 ERROR("osc_megahertz must be positive and non-zero!");
308 command_print(cmd_ctx, "osc_megahertz must be positive and non-zero!");
309 oscMHz = 12;
310 return ERROR_INVALID_ARGUMENTS;
311 }
312
313 command_print(cmd_ctx, "osc_megahertz=%d", oscMHz);
314
315 return ERROR_OK;
316 }
317
318 /* ---------------------------------------------------------------------- */
319
320 int plldis = 0;
321
322 int tms470_handle_plldis_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
323 {
324 if (argc > 1)
325 {
326 command_print(cmd_ctx, "tms470 plldis <0|1>");
327 return ERROR_INVALID_ARGUMENTS;
328 }
329 else if (argc == 1)
330 {
331 sscanf(args[0], "%d", &plldis);
332 plldis = plldis ? 1 : 0;
333 }
334
335 command_print(cmd_ctx, "plldis=%d", plldis);
336
337 return ERROR_OK;
338 }
339
340 /* ---------------------------------------------------------------------- */
341
342 int tms470_check_flash_unlocked(target_t * target)
343 {
344 u32 fmbbusy;
345
346 target_read_u32(target, 0xFFE89C08, &fmbbusy);
347 INFO("tms470 fmbbusy=0x%08x -> %s", fmbbusy, fmbbusy & 0x8000 ? "unlocked" : "LOCKED");
348 return fmbbusy & 0x8000 ? ERROR_OK : ERROR_FLASH_OPERATION_FAILED;
349 }
350
351 /* ---------------------------------------------------------------------- */
352
353 int tms470_try_flash_keys(target_t * target, const u32 * key_set)
354 {
355 u32 glbctrl, fmmstat;
356 int retval = ERROR_FLASH_OPERATION_FAILED;
357
358 /* set GLBCTRL.4 */
359 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
360 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
361
362 /* only perform the key match when 3VSTAT is clear */
363 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
364 if (!(fmmstat & 0x08))
365 {
366 unsigned i;
367 u32 fmbptr, fmbac2, orig_fmregopt;
368
369 target_write_u32(target, 0xFFE8BC04, fmmstat & ~0x07);
370
371 /* wait for pump ready */
372 do
373 {
374 target_read_u32(target, 0xFFE8A814, &fmbptr);
375 usleep(1000);
376 }
377 while (!(fmbptr & 0x0200));
378
379 /* force max wait states */
380 target_read_u32(target, 0xFFE88004, &fmbac2);
381 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
382
383 /* save current access mode, force normal read mode */
384 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
385 target_write_u32(target, 0xFFE89C00, 0x00);
386
387 for (i = 0; i < 4; i++)
388 {
389 u32 tmp;
390
391 /* There is no point displaying the value of tmp, it is
392 * filtered by the chip. The purpose of this read is to
393 * prime the unlocking logic rather than read out the value.
394 */
395 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
396
397 INFO("tms470 writing fmpkey=0x%08x", key_set[i]);
398 target_write_u32(target, 0xFFE89C0C, key_set[i]);
399 }
400
401 if (ERROR_OK == tms470_check_flash_unlocked(target))
402 {
403 /*
404 * There seems to be a side-effect of reading the FMPKEY
405 * register in that it re-enables the protection. So we
406 * re-enable it.
407 */
408 for (i = 0; i < 4; i++)
409 {
410 u32 tmp;
411
412 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
413 target_write_u32(target, 0xFFE89C0C, key_set[i]);
414 }
415 retval = ERROR_OK;
416 }
417
418 /* restore settings */
419 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
420 target_write_u32(target, 0xFFE88004, fmbac2);
421 }
422
423 /* clear config bit */
424 target_write_u32(target, 0xFFFFFFDC, glbctrl);
425
426 return retval;
427 }
428
429 /* ---------------------------------------------------------------------- */
430
431 int tms470_unlock_flash(struct flash_bank_s *bank)
432 {
433 target_t *target = bank->target;
434 const u32 *p_key_sets[5];
435 unsigned i, key_set_count;
436
437 if (keysSet)
438 {
439 key_set_count = 5;
440 p_key_sets[0] = flashKeys;
441 p_key_sets[1] = FLASH_KEYS_ALL_ONES;
442 p_key_sets[2] = FLASH_KEYS_ALL_ZEROS;
443 p_key_sets[3] = FLASH_KEYS_MIX1;
444 p_key_sets[4] = FLASH_KEYS_MIX2;
445 }
446 else
447 {
448 key_set_count = 4;
449 p_key_sets[0] = FLASH_KEYS_ALL_ONES;
450 p_key_sets[1] = FLASH_KEYS_ALL_ZEROS;
451 p_key_sets[2] = FLASH_KEYS_MIX1;
452 p_key_sets[3] = FLASH_KEYS_MIX2;
453 }
454
455 for (i = 0; i < key_set_count; i++)
456 {
457 if (tms470_try_flash_keys(target, p_key_sets[i]) == ERROR_OK)
458 {
459 INFO("tms470 flash is unlocked");
460 return ERROR_OK;
461 }
462 }
463
464 WARNING("tms470 could not unlock flash memory protection level 2");
465 return ERROR_FLASH_OPERATION_FAILED;
466 }
467
468 /* ---------------------------------------------------------------------- */
469
470 int tms470_flash_initialize_internal_state_machine(struct flash_bank_s *bank)
471 {
472 u32 fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
473 target_t *target = bank->target;
474 tms470_flash_bank_t *tms470_info = bank->driver_priv;
475 int result = ERROR_OK;
476
477 /*
478 * Select the desired bank to be programmed by writing BANK[2:0] of
479 * FMMAC2.
480 */
481 target_read_u32(target, 0xFFE8BC04, &fmmac2);
482 fmmac2 &= ~0x0007;
483 fmmac2 |= (tms470_info->ordinal & 7);
484 target_write_u32(target, 0xFFE8BC04, fmmac2);
485 DEBUG("set fmmac2=0x%04x", fmmac2);
486
487 /*
488 * Disable level 1 sector protection by setting bit 15 of FMMAC1.
489 */
490 target_read_u32(target, 0xFFE8BC00, &fmmac1);
491 fmmac1 |= 0x8000;
492 target_write_u32(target, 0xFFE8BC00, fmmac1);
493 DEBUG("set fmmac1=0x%04x", fmmac1);
494
495 /*
496 * FMTCREG=0x2fc0;
497 */
498 target_write_u32(target, 0xFFE8BC10, 0x2fc0);
499 DEBUG("set fmtcreg=0x2fc0");
500
501 /*
502 * MAXPP=50
503 */
504 target_write_u32(target, 0xFFE8A07C, 50);
505 DEBUG("set fmmaxpp=50");
506
507 /*
508 * MAXCP=0xf000+2000
509 */
510 target_write_u32(target, 0xFFE8A084, 0xf000 + 2000);
511 DEBUG("set fmmaxcp=0x%04x", 0xf000 + 2000);
512
513 /*
514 * configure VHV
515 */
516 target_read_u32(target, 0xFFE8A080, &fmmaxep);
517 if (fmmaxep == 0xf000)
518 {
519 fmmaxep = 0xf000 + 4095;
520 target_write_u32(target, 0xFFE8A80C, 0x9964);
521 DEBUG("set fmptr3=0x9964");
522 }
523 else
524 {
525 fmmaxep = 0xa000 + 4095;
526 target_write_u32(target, 0xFFE8A80C, 0x9b64);
527 DEBUG("set fmptr3=0x9b64");
528 }
529 target_write_u32(target, 0xFFE8A080, fmmaxep);
530 DEBUG("set fmmaxep=0x%04x", fmmaxep);
531
532 /*
533 * FMPTR4=0xa000
534 */
535 target_write_u32(target, 0xFFE8A810, 0xa000);
536 DEBUG("set fmptr4=0xa000");
537
538 /*
539 * FMPESETUP, delay parameter selected based on clock frequency.
540 *
541 * According to the TI App Note SPNU257 and flashing code, delay is
542 * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
543 * clock is usually derived from the ZPLL module, and selected by
544 * the plldis global.
545 */
546 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
547 sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * oscMHz / (1 + (glbctrl & 7));
548 delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
549 target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
550 DEBUG("set fmpsetup=0x%04x", (delay << 4) | (delay << 8));
551
552 /*
553 * FMPVEVACCESS, based on delay.
554 */
555 k = delay | (delay << 8);
556 target_write_u32(target, 0xFFE8A05C, k);
557 DEBUG("set fmpvevaccess=0x%04x", k);
558
559 /*
560 * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
561 */
562 k <<= 1;
563 target_write_u32(target, 0xFFE8A034, k);
564 DEBUG("set fmpchold=0x%04x", k);
565 target_write_u32(target, 0xFFE8A040, k);
566 DEBUG("set fmpvevhold=0x%04x", k);
567 target_write_u32(target, 0xFFE8A024, k);
568 DEBUG("set fmpvevsetup=0x%04x", k);
569
570 /*
571 * FMCVACCESS, based on delay.
572 */
573 k = delay * 16;
574 target_write_u32(target, 0xFFE8A060, k);
575 DEBUG("set fmcvaccess=0x%04x", k);
576
577 /*
578 * FMCSETUP, based on delay.
579 */
580 k = 0x3000 | delay * 20;
581 target_write_u32(target, 0xFFE8A020, k);
582 DEBUG("set fmcsetup=0x%04x", k);
583
584 /*
585 * FMEHOLD, based on delay.
586 */
587 k = (delay * 20) << 2;
588 target_write_u32(target, 0xFFE8A038, k);
589 DEBUG("set fmehold=0x%04x", k);
590
591 /*
592 * PWIDTH, CWIDTH, EWIDTH, based on delay.
593 */
594 target_write_u32(target, 0xFFE8A050, delay * 8);
595 DEBUG("set fmpwidth=0x%04x", delay * 8);
596 target_write_u32(target, 0xFFE8A058, delay * 1000);
597 DEBUG("set fmcwidth=0x%04x", delay * 1000);
598 target_write_u32(target, 0xFFE8A054, delay * 5400);
599 DEBUG("set fmewidth=0x%04x", delay * 5400);
600
601 return result;
602 }
603
604 /* ---------------------------------------------------------------------- */
605
606 int tms470_flash_status(struct flash_bank_s *bank)
607 {
608 target_t *target = bank->target;
609 int result = ERROR_OK;
610 u32 fmmstat;
611
612 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
613 DEBUG("set fmmstat=0x%04x", fmmstat);
614
615 if (fmmstat & 0x0080)
616 {
617 WARNING("tms470 flash command: erase still active after busy clear.");
618 result = ERROR_FLASH_OPERATION_FAILED;
619 }
620
621 if (fmmstat & 0x0040)
622 {
623 WARNING("tms470 flash command: program still active after busy clear.");
624 result = ERROR_FLASH_OPERATION_FAILED;
625 }
626
627 if (fmmstat & 0x0020)
628 {
629 WARNING("tms470 flash command: invalid data command.");
630 result = ERROR_FLASH_OPERATION_FAILED;
631 }
632
633 if (fmmstat & 0x0010)
634 {
635 WARNING("tms470 flash command: program, erase or validate sector failed.");
636 result = ERROR_FLASH_OPERATION_FAILED;
637 }
638
639 if (fmmstat & 0x0008)
640 {
641 WARNING("tms470 flash command: voltage instability detected.");
642 result = ERROR_FLASH_OPERATION_FAILED;
643 }
644
645 if (fmmstat & 0x0006)
646 {
647 WARNING("tms470 flash command: command suspend detected.");
648 result = ERROR_FLASH_OPERATION_FAILED;
649 }
650
651 if (fmmstat & 0x0001)
652 {
653 WARNING("tms470 flash command: sector was locked.");
654 result = ERROR_FLASH_OPERATION_FAILED;
655 }
656
657 return result;
658 }
659
660 /* ---------------------------------------------------------------------- */
661
662 int tms470_erase_sector(struct flash_bank_s *bank, int sector)
663 {
664 u32 glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
665 target_t *target = bank->target;
666 u32 flashAddr = bank->base + bank->sectors[sector].offset;
667 int result = ERROR_OK;
668
669 /*
670 * Set the bit GLBCTRL4 of the GLBCTRL register (in the System
671 * module) to enable writing to the flash registers }.
672 */
673 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
674 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
675 DEBUG("set glbctrl=0x%08x", glbctrl | 0x10);
676
677 /* Force normal read mode. */
678 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
679 target_write_u32(target, 0xFFE89C00, 0);
680 DEBUG("set fmregopt=0x%08x", 0);
681
682 (void)tms470_flash_initialize_internal_state_machine(bank);
683
684 /*
685 * Select one or more bits in FMBSEA or FMBSEB to disable Level 1
686 * protection for the particular sector to be erased/written.
687 */
688 if (sector < 16)
689 {
690 target_read_u32(target, 0xFFE88008, &fmbsea);
691 target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
692 DEBUG("set fmbsea=0x%04x", fmbsea | (1 << sector));
693 }
694 else
695 {
696 target_read_u32(target, 0xFFE8800C, &fmbseb);
697 target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
698 DEBUG("set fmbseb=0x%04x", fmbseb | (1 << (sector - 16)));
699 }
700 bank->sectors[sector].is_protected = 0;
701
702 /*
703 * clear status regiser, sent erase command, kickoff erase
704 */
705 target_write_u16(target, flashAddr, 0x0040);
706 DEBUG("write *(u16 *)0x%08x=0x0040", flashAddr);
707 target_write_u16(target, flashAddr, 0x0020);
708 DEBUG("write *(u16 *)0x%08x=0x0020", flashAddr);
709 target_write_u16(target, flashAddr, 0xffff);
710 DEBUG("write *(u16 *)0x%08x=0xffff", flashAddr);
711
712 /*
713 * Monitor FMMSTAT, busy until clear, then check and other flags for
714 * ultimate result of the operation.
715 */
716 do
717 {
718 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
719 if (fmmstat & 0x0100)
720 {
721 usleep(1000);
722 }
723 }
724 while (fmmstat & 0x0100);
725
726 result = tms470_flash_status(bank);
727
728 if (sector < 16)
729 {
730 target_write_u32(target, 0xFFE88008, fmbsea);
731 DEBUG("set fmbsea=0x%04x", fmbsea);
732 bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
733 }
734 else
735 {
736 target_write_u32(target, 0xFFE8800C, fmbseb);
737 DEBUG("set fmbseb=0x%04x", fmbseb);
738 bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
739 }
740 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
741 DEBUG("set fmregopt=0x%08x", orig_fmregopt);
742 target_write_u32(target, 0xFFFFFFDC, glbctrl);
743 DEBUG("set glbctrl=0x%08x", glbctrl);
744
745 if (result == ERROR_OK)
746 {
747 bank->sectors[sector].is_erased = 1;
748 }
749
750 return result;
751 }
752
753 /* ----------------------------------------------------------------------
754 Implementation of Flash Driver Interfaces
755 ---------------------------------------------------------------------- */
756
757 int tms470_register_commands(struct command_context_s *cmd_ctx)
758 {
759 command_t *tms470_cmd = register_command(cmd_ctx, NULL, "tms470", NULL, COMMAND_ANY, "applies to TI tms470 family");
760
761 register_command(cmd_ctx, tms470_cmd, "flash_keyset", tms470_handle_flash_keyset_command, COMMAND_ANY, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
762 register_command(cmd_ctx, tms470_cmd, "osc_megahertz", tms470_handle_osc_megahertz_command, COMMAND_ANY, "tms470 osc_megahertz <MHz>");
763 register_command(cmd_ctx, tms470_cmd, "plldis", tms470_handle_plldis_command, COMMAND_ANY, "tms470 plldis <0/1>");
764
765 return ERROR_OK;
766 }
767
768 /* ---------------------------------------------------------------------- */
769
770 int tms470_erase(struct flash_bank_s *bank, int first, int last)
771 {
772 tms470_flash_bank_t *tms470_info = bank->driver_priv;
773 int sector, result = ERROR_OK;
774
775 if (bank->target->state != TARGET_HALTED)
776 {
777 return ERROR_TARGET_NOT_HALTED;
778 }
779
780 tms470_read_part_info(bank);
781
782 if ((first < 0) || (first >= bank->num_sectors) || (last < 0) || (last >= bank->num_sectors) || (first > last))
783 {
784 ERROR("Sector range %d to %d invalid.", first, last);
785 return ERROR_FLASH_SECTOR_INVALID;
786 }
787
788 result = tms470_unlock_flash(bank);
789 if (result != ERROR_OK)
790 {
791 return result;
792 }
793
794 for (sector = first; sector <= last; sector++)
795 {
796 INFO("Erasing tms470 bank %d sector %d...", tms470_info->ordinal, sector);
797
798 result = tms470_erase_sector(bank, sector);
799
800 if (result != ERROR_OK)
801 {
802 ERROR("tms470 could not erase flash sector.");
803 break;
804 }
805 else
806 {
807 INFO("sector erased successfully.");
808 }
809 }
810
811 return result;
812 }
813
814 /* ---------------------------------------------------------------------- */
815
816 int tms470_protect(struct flash_bank_s *bank, int set, int first, int last)
817 {
818 tms470_flash_bank_t *tms470_info = bank->driver_priv;
819 target_t *target = bank->target;
820 u32 fmmac2, fmbsea, fmbseb;
821 int sector;
822
823 if (target->state != TARGET_HALTED)
824 {
825 return ERROR_TARGET_NOT_HALTED;
826 }
827
828 tms470_read_part_info(bank);
829
830 if ((first < 0) || (first >= bank->num_sectors) || (last < 0) || (last >= bank->num_sectors) || (first > last))
831 {
832 ERROR("Sector range %d to %d invalid.", first, last);
833 return ERROR_FLASH_SECTOR_INVALID;
834 }
835
836 /* enable the appropriate bank */
837 target_read_u32(target, 0xFFE8BC04, &fmmac2);
838 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
839
840 /* get the original sector proection flags for this bank */
841 target_read_u32(target, 0xFFE88008, &fmbsea);
842 target_read_u32(target, 0xFFE8800C, &fmbseb);
843
844 for (sector = 0; sector < bank->num_sectors; sector++)
845 {
846 if (sector < 16)
847 {
848 fmbsea = set ? fmbsea & ~(1 << sector) : fmbsea | (1 << sector);
849 bank->sectors[sector].is_protected = set ? 1 : 0;
850 }
851 else
852 {
853 fmbseb = set ? fmbseb & ~(1 << (sector - 16)) : fmbseb | (1 << (sector - 16));
854 bank->sectors[sector].is_protected = set ? 1 : 0;
855 }
856 }
857
858 /* update the protection bits */
859 target_write_u32(target, 0xFFE88008, fmbsea);
860 target_write_u32(target, 0xFFE8800C, fmbseb);
861
862 return ERROR_OK;
863 }
864
865 /* ---------------------------------------------------------------------- */
866
867 int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count)
868 {
869 target_t *target = bank->target;
870 u32 glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
871 int i, result = ERROR_OK;
872
873 if (target->state != TARGET_HALTED)
874 {
875 return ERROR_TARGET_NOT_HALTED;
876 }
877
878 tms470_read_part_info(bank);
879
880 INFO("Writing %d bytes starting at 0x%08x", count, bank->base + offset);
881
882 /* set GLBCTRL.4 */
883 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
884 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
885
886 (void)tms470_flash_initialize_internal_state_machine(bank);
887
888 /* force max wait states */
889 target_read_u32(target, 0xFFE88004, &fmbac2);
890 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
891
892 /* save current access mode, force normal read mode */
893 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
894 target_write_u32(target, 0xFFE89C00, 0x00);
895
896 /*
897 * Disable Level 1 protection for all sectors to be erased/written.
898 */
899 target_read_u32(target, 0xFFE88008, &fmbsea);
900 target_write_u32(target, 0xFFE88008, 0xffff);
901 target_read_u32(target, 0xFFE8800C, &fmbseb);
902 target_write_u32(target, 0xFFE8800C, 0xffff);
903
904 /* read MAXPP */
905 target_read_u32(target, 0xFFE8A07C, &fmmaxpp);
906
907 for (i = 0; i < count; i += 2)
908 {
909 u32 addr = bank->base + offset + i;
910 u16 word = (((u16) buffer[i]) << 8) | (u16) buffer[i + 1];
911
912 if (word != 0xffff)
913 {
914 INFO("writing 0x%04x at 0x%08x", word, addr);
915
916 /* clear status register */
917 target_write_u16(target, addr, 0x0040);
918 /* program flash command */
919 target_write_u16(target, addr, 0x0010);
920 /* burn the 16-bit word (big-endian) */
921 target_write_u16(target, addr, word);
922
923 /*
924 * Monitor FMMSTAT, busy until clear, then check and other flags
925 * for ultimate result of the operation.
926 */
927 do
928 {
929 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
930 if (fmmstat & 0x0100)
931 {
932 usleep(1000);
933 }
934 }
935 while (fmmstat & 0x0100);
936
937 if (fmmstat & 0x3ff)
938 {
939 ERROR("fmstat=0x%04x", fmmstat);
940 ERROR("Could not program word 0x%04x at address 0x%08x.", word, addr);
941 result = ERROR_FLASH_OPERATION_FAILED;
942 break;
943 }
944 }
945 else
946 {
947 INFO("skipping 0xffff at 0x%08x", addr);
948 }
949 }
950
951 /* restore */
952 target_write_u32(target, 0xFFE88008, fmbsea);
953 target_write_u32(target, 0xFFE8800C, fmbseb);
954 target_write_u32(target, 0xFFE88004, fmbac2);
955 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
956 target_write_u32(target, 0xFFFFFFDC, glbctrl);
957
958 return result;
959 }
960
961 /* ---------------------------------------------------------------------- */
962
963 int tms470_probe(struct flash_bank_s *bank)
964 {
965 if (bank->target->state != TARGET_HALTED)
966 {
967 WARNING("Cannot communicate... target not halted.");
968 return ERROR_TARGET_NOT_HALTED;
969 }
970
971 return tms470_read_part_info(bank);
972 }
973
974 int tms470_auto_probe(struct flash_bank_s *bank)
975 {
976 tms470_flash_bank_t *tms470_info = bank->driver_priv;
977
978 if (tms470_info->device_ident_reg)
979 return ERROR_OK;
980 return tms470_probe(bank);
981 }
982
983 /* ---------------------------------------------------------------------- */
984
985 int tms470_erase_check(struct flash_bank_s *bank)
986 {
987 target_t *target = bank->target;
988 tms470_flash_bank_t *tms470_info = bank->driver_priv;
989 int sector, result = ERROR_OK;
990 u32 fmmac2, fmbac2, glbctrl, orig_fmregopt;
991 static u8 buffer[64 * 1024];
992
993 if (target->state != TARGET_HALTED)
994 {
995 return ERROR_TARGET_NOT_HALTED;
996 }
997
998 if (!tms470_info->device_ident_reg)
999 {
1000 tms470_read_part_info(bank);
1001 }
1002
1003 /* set GLBCTRL.4 */
1004 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
1005 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
1006
1007 /* save current access mode, force normal read mode */
1008 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
1009 target_write_u32(target, 0xFFE89C00, 0x00);
1010
1011 /* enable the appropriate bank */
1012 target_read_u32(target, 0xFFE8BC04, &fmmac2);
1013 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1014
1015 /* TCR=0 */
1016 target_write_u32(target, 0xFFE8BC10, 0x2fc0);
1017
1018 /* clear TEZ in fmbrdy */
1019 target_write_u32(target, 0xFFE88010, 0x0b);
1020
1021 /* save current wait states, force max */
1022 target_read_u32(target, 0xFFE88004, &fmbac2);
1023 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
1024
1025 /*
1026 * The TI primitives inspect the flash memory by reading one 32-bit
1027 * word at a time. Here we read an entire sector and inspect it in
1028 * an attempt to reduce the JTAG overhead.
1029 */
1030 for (sector = 0; sector < bank->num_sectors; sector++)
1031 {
1032 if (bank->sectors[sector].is_erased != 1)
1033 {
1034 u32 i, addr = bank->base + bank->sectors[sector].offset;
1035
1036 INFO("checking flash bank %d sector %d", tms470_info->ordinal, sector);
1037
1038 target_read_buffer(target, addr, bank->sectors[sector].size, buffer);
1039
1040 bank->sectors[sector].is_erased = 1;
1041 for (i = 0; i < bank->sectors[sector].size; i++)
1042 {
1043 if (buffer[i] != 0xff)
1044 {
1045 WARNING("tms470 bank %d, sector %d, not erased.", tms470_info->ordinal, sector);
1046 WARNING("at location 0x%08x: flash data is 0x%02x.", addr + i, buffer[i]);
1047
1048 bank->sectors[sector].is_erased = 0;
1049 break;
1050 }
1051 }
1052 }
1053 if (bank->sectors[sector].is_erased != 1)
1054 {
1055 result = ERROR_FLASH_SECTOR_NOT_ERASED;
1056 break;
1057 }
1058 else
1059 {
1060 INFO("sector erased");
1061 }
1062 }
1063
1064 /* reset TEZ, wait states, read mode, GLBCTRL.4 */
1065 target_write_u32(target, 0xFFE88010, 0x0f);
1066 target_write_u32(target, 0xFFE88004, fmbac2);
1067 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
1068 target_write_u32(target, 0xFFFFFFDC, glbctrl);
1069
1070 return result;
1071 }
1072
1073 /* ---------------------------------------------------------------------- */
1074
1075 int tms470_protect_check(struct flash_bank_s *bank)
1076 {
1077 target_t *target = bank->target;
1078 tms470_flash_bank_t *tms470_info = bank->driver_priv;
1079 int sector, result = ERROR_OK;
1080 u32 fmmac2, fmbsea, fmbseb;
1081
1082 if (target->state != TARGET_HALTED)
1083 {
1084 return ERROR_TARGET_NOT_HALTED;
1085 }
1086
1087 if (!tms470_info->device_ident_reg)
1088 {
1089 tms470_read_part_info(bank);
1090 }
1091
1092 /* enable the appropriate bank */
1093 target_read_u32(target, 0xFFE8BC04, &fmmac2);
1094 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1095
1096 target_read_u32(target, 0xFFE88008, &fmbsea);
1097 target_read_u32(target, 0xFFE8800C, &fmbseb);
1098
1099 for (sector = 0; sector < bank->num_sectors; sector++)
1100 {
1101 int protected;
1102
1103 if (sector < 16)
1104 {
1105 protected = fmbsea & (1 << sector) ? 0 : 1;
1106 bank->sectors[sector].is_protected = protected;
1107 }
1108 else
1109 {
1110 protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
1111 bank->sectors[sector].is_protected = protected;
1112 }
1113
1114 DEBUG("bank %d sector %d is %s", tms470_info->ordinal, sector, protected ? "protected" : "not protected");
1115 }
1116
1117 return result;
1118 }
1119
1120 /* ---------------------------------------------------------------------- */
1121
1122 int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size)
1123 {
1124 int used = 0;
1125 tms470_flash_bank_t *tms470_info = bank->driver_priv;
1126
1127 if (!tms470_info->device_ident_reg)
1128 {
1129 tms470_read_part_info(bank);
1130 }
1131
1132 if (!tms470_info->device_ident_reg)
1133 {
1134 (void)snprintf(buf, buf_size, "Cannot identify target as a TMS470\n");
1135 return ERROR_FLASH_OPERATION_FAILED;
1136 }
1137
1138 used += snprintf(buf, buf_size, "\ntms470 information: Chip is %s\n", tms470_info->part_name);
1139 buf += used;
1140 buf_size -= used;
1141
1142 used += snprintf(buf, buf_size, "Flash protection level 2 is %s\n", tms470_check_flash_unlocked(bank->target) == ERROR_OK ? "disabled" : "enabled");
1143 buf += used;
1144 buf_size -= used;
1145
1146 return ERROR_OK;
1147 }
1148
1149 /* ---------------------------------------------------------------------- */
1150
1151 /*
1152 * flash bank tms470 <base> <size> <chip_width> <bus_width> <target>
1153 * [options...]
1154 */
1155
1156 int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
1157 {
1158 bank->driver_priv = malloc(sizeof(tms470_flash_bank_t));
1159
1160 if (!bank->driver_priv)
1161 {
1162 return ERROR_FLASH_OPERATION_FAILED;
1163 }
1164
1165 (void)memset(bank->driver_priv, 0, sizeof(tms470_flash_bank_t));
1166
1167 return ERROR_OK;
1168 }