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- cleaned up str7, str9 and stm32 flash drivers
[openocd.git] / src / flash / str9x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "str9x.h"
27 #include "flash.h"
28 #include "target.h"
29 #include "log.h"
30 #include "armv4_5.h"
31 #include "arm966e.h"
32 #include "algorithm.h"
33 #include "binarybuffer.h"
34
35 #include <stdlib.h>
36 #include <string.h>
37 #include <unistd.h>
38
39 str9x_mem_layout_t mem_layout_str9[] = {
40 {0x00000000, 0x10000, 0x01},
41 {0x00010000, 0x10000, 0x02},
42 {0x00020000, 0x10000, 0x04},
43 {0x00030000, 0x10000, 0x08},
44 {0x00040000, 0x10000, 0x10},
45 {0x00050000, 0x10000, 0x20},
46 {0x00060000, 0x10000, 0x40},
47 {0x00070000, 0x10000, 0x80},
48 {0x00080000, 0x02000, 0x100},
49 {0x00082000, 0x02000, 0x200},
50 {0x00084000, 0x02000, 0x400},
51 {0x00086000, 0x02000, 0x800}
52 };
53
54 int str9x_register_commands(struct command_context_s *cmd_ctx);
55 int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
56 int str9x_erase(struct flash_bank_s *bank, int first, int last);
57 int str9x_protect(struct flash_bank_s *bank, int set, int first, int last);
58 int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
59 int str9x_probe(struct flash_bank_s *bank);
60 int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
61 int str9x_protect_check(struct flash_bank_s *bank);
62 int str9x_erase_check(struct flash_bank_s *bank);
63 int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size);
64
65 int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
66
67 flash_driver_t str9x_flash =
68 {
69 .name = "str9x",
70 .register_commands = str9x_register_commands,
71 .flash_bank_command = str9x_flash_bank_command,
72 .erase = str9x_erase,
73 .protect = str9x_protect,
74 .write = str9x_write,
75 .probe = str9x_probe,
76 .erase_check = str9x_erase_check,
77 .protect_check = str9x_protect_check,
78 .info = str9x_info
79 };
80
81 int str9x_register_commands(struct command_context_s *cmd_ctx)
82 {
83 command_t *str9x_cmd = register_command(cmd_ctx, NULL, "str9x", NULL, COMMAND_ANY, NULL);
84
85 register_command(cmd_ctx, str9x_cmd, "flash_config", str9x_handle_flash_config_command, COMMAND_EXEC,
86 "configure str9 flash controller");
87
88 return ERROR_OK;
89 }
90
91 int str9x_build_block_list(struct flash_bank_s *bank)
92 {
93 str9x_flash_bank_t *str9x_info = bank->driver_priv;
94
95 int i;
96 int num_sectors = 0, b0_sectors = 0;
97
98 switch (bank->size)
99 {
100 case 256 * 1024:
101 b0_sectors = 4;
102 break;
103 case 512 * 1024:
104 b0_sectors = 8;
105 break;
106 default:
107 ERROR("BUG: unknown bank->size encountered");
108 exit(-1);
109 }
110
111 num_sectors = b0_sectors + 4;
112
113 bank->num_sectors = num_sectors;
114 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
115 str9x_info->sector_bits = malloc(sizeof(u32) * num_sectors);
116
117 num_sectors = 0;
118
119 for (i = 0; i < b0_sectors; i++)
120 {
121 bank->sectors[num_sectors].offset = mem_layout_str9[i].sector_start;
122 bank->sectors[num_sectors].size = mem_layout_str9[i].sector_size;
123 bank->sectors[num_sectors].is_erased = -1;
124 bank->sectors[num_sectors].is_protected = 1;
125 str9x_info->sector_bits[num_sectors++] = mem_layout_str9[i].sector_bit;
126 }
127
128 for (i = 8; i < 12; i++)
129 {
130 bank->sectors[num_sectors].offset = mem_layout_str9[i].sector_start;
131 bank->sectors[num_sectors].size = mem_layout_str9[i].sector_size;
132 bank->sectors[num_sectors].is_erased = -1;
133 bank->sectors[num_sectors].is_protected = 1;
134 str9x_info->sector_bits[num_sectors++] = mem_layout_str9[i].sector_bit;
135 }
136
137 return ERROR_OK;
138 }
139
140 /* flash bank str9x <base> <size> 0 0 <target#>
141 */
142 int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
143 {
144 str9x_flash_bank_t *str9x_info;
145
146 if (argc < 6)
147 {
148 WARNING("incomplete flash_bank str9x configuration");
149 return ERROR_FLASH_BANK_INVALID;
150 }
151
152 str9x_info = malloc(sizeof(str9x_flash_bank_t));
153 bank->driver_priv = str9x_info;
154
155 if (bank->base != 0x00000000)
156 {
157 WARNING("overriding flash base address for STR91x device with 0x00000000");
158 bank->base = 0x00000000;
159 }
160
161 str9x_build_block_list(bank);
162
163 str9x_info->write_algorithm = NULL;
164
165 return ERROR_OK;
166 }
167
168 int str9x_blank_check(struct flash_bank_s *bank, int first, int last)
169 {
170 target_t *target = bank->target;
171 u8 *buffer;
172 int i;
173 int nBytes;
174
175 if ((first < 0) || (last > bank->num_sectors))
176 return ERROR_FLASH_SECTOR_INVALID;
177
178 if (bank->target->state != TARGET_HALTED)
179 {
180 return ERROR_TARGET_NOT_HALTED;
181 }
182
183 buffer = malloc(256);
184
185 for (i = first; i <= last; i++)
186 {
187 bank->sectors[i].is_erased = 1;
188
189 target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
190
191 for (nBytes = 0; nBytes < 256; nBytes++)
192 {
193 if (buffer[nBytes] != 0xFF)
194 {
195 bank->sectors[i].is_erased = 0;
196 break;
197 }
198 }
199 }
200
201 free(buffer);
202
203 return ERROR_OK;
204 }
205
206 int str9x_protect_check(struct flash_bank_s *bank)
207 {
208 str9x_flash_bank_t *str9x_info = bank->driver_priv;
209 target_t *target = bank->target;
210
211 int i;
212 u32 adr;
213 u16 status;
214
215 if (bank->target->state != TARGET_HALTED)
216 {
217 return ERROR_TARGET_NOT_HALTED;
218 }
219
220 /* read level one protection */
221
222 adr = mem_layout_str9[10].sector_start + 4;
223
224 target_write_u32(target, adr, 0x90);
225 target_read_u16(target, adr, &status);
226 target_write_u32(target, adr, 0xFF);
227
228 for (i = 0; i < bank->num_sectors; i++)
229 {
230 if (status & str9x_info->sector_bits[i])
231 bank->sectors[i].is_protected = 1;
232 else
233 bank->sectors[i].is_protected = 0;
234 }
235
236 return ERROR_OK;
237 }
238
239 int str9x_erase(struct flash_bank_s *bank, int first, int last)
240 {
241 target_t *target = bank->target;
242 int i;
243 u32 adr;
244 u8 status;
245
246 if (bank->target->state != TARGET_HALTED)
247 {
248 return ERROR_TARGET_NOT_HALTED;
249 }
250
251 for (i = first; i <= last; i++)
252 {
253 adr = bank->sectors[i].offset;
254
255 /* erase sectors */
256 target_write_u16(target, adr, 0x20);
257 target_write_u16(target, adr, 0xD0);
258
259 /* get status */
260 target_write_u16(target, adr, 0x70);
261
262 while (1) {
263 target_read_u8(target, adr, &status);
264 if( status & 0x80 )
265 break;
266 usleep(1000);
267 }
268
269 /* clear status, also clear read array */
270 target_write_u16(target, adr, 0x50);
271
272 /* read array command */
273 target_write_u16(target, adr, 0xFF);
274
275 if( status & 0x22 )
276 {
277 ERROR("error erasing flash bank, status: 0x%x", status);
278 return ERROR_FLASH_OPERATION_FAILED;
279 }
280 }
281
282 for (i = first; i <= last; i++)
283 bank->sectors[i].is_erased = 1;
284
285 return ERROR_OK;
286 }
287
288 int str9x_protect(struct flash_bank_s *bank, int set, int first, int last)
289 {
290 target_t *target = bank->target;
291 int i;
292 u32 adr;
293 u8 status;
294
295 if (bank->target->state != TARGET_HALTED)
296 {
297 return ERROR_TARGET_NOT_HALTED;
298 }
299
300 for (i = first; i <= last; i++)
301 {
302 /* Level One Protection */
303
304 adr = bank->sectors[i].offset;
305
306 target_write_u16(target, adr, 0x60);
307 if( set )
308 target_write_u16(target, adr, 0x01);
309 else
310 target_write_u16(target, adr, 0xD0);
311
312 /* query status */
313 target_read_u8(target, adr, &status);
314 }
315
316 return ERROR_OK;
317 }
318
319 int str9x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
320 {
321 str9x_flash_bank_t *str9x_info = bank->driver_priv;
322 target_t *target = bank->target;
323 u32 buffer_size = 8192;
324 working_area_t *source;
325 u32 address = bank->base + offset;
326 reg_param_t reg_params[4];
327 armv4_5_algorithm_t armv4_5_info;
328 int retval;
329
330 u32 str9x_flash_write_code[] = {
331 /* write: */
332 0xe3c14003, /* bic r4, r1, #3 */
333 0xe3a03040, /* mov r3, #0x40 */
334 0xe1c430b0, /* strh r3, [r4, #0] */
335 0xe0d030b2, /* ldrh r3, [r0], #2 */
336 0xe0c130b2, /* strh r3, [r1], #2 */
337 0xe3a03070, /* mov r3, #0x70 */
338 0xe1c430b0, /* strh r3, [r4, #0] */
339 /* busy: */
340 0xe5d43000, /* ldrb r3, [r4, #0] */
341 0xe3130080, /* tst r3, #0x80 */
342 0x0afffffc, /* beq busy */
343 0xe3a05050, /* mov r5, #0x50 */
344 0xe1c450b0, /* strh r5, [r4, #0] */
345 0xe3a050ff, /* mov r5, #0xFF */
346 0xe1c450b0, /* strh r5, [r4, #0] */
347 0xe3130012, /* tst r3, #0x12 */
348 0x1a000001, /* bne exit */
349 0xe2522001, /* subs r2, r2, #1 */
350 0x1affffed, /* bne write */
351 /* exit: */
352 0xeafffffe, /* b exit */
353 };
354
355 /* flash write code */
356 if (target_alloc_working_area(target, 4 * 19, &str9x_info->write_algorithm) != ERROR_OK)
357 {
358 WARNING("no working area available, can't do block memory writes");
359 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
360 };
361
362 target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (u8*)str9x_flash_write_code);
363
364 /* memory buffer */
365 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
366 {
367 buffer_size /= 2;
368 if (buffer_size <= 256)
369 {
370 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
371 if (str9x_info->write_algorithm)
372 target_free_working_area(target, str9x_info->write_algorithm);
373
374 WARNING("no large enough working area available, can't do block memory writes");
375 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
376 }
377 }
378
379 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
380 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
381 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
382
383 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
384 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
385 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
386 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
387
388 while (count > 0)
389 {
390 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
391
392 target_write_buffer(target, source->address, thisrun_count * 2, buffer);
393
394 buf_set_u32(reg_params[0].value, 0, 32, source->address);
395 buf_set_u32(reg_params[1].value, 0, 32, address);
396 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
397
398 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, str9x_info->write_algorithm->address + (18 * 4), 10000, &armv4_5_info)) != ERROR_OK)
399 {
400 target_free_working_area(target, source);
401 target_free_working_area(target, str9x_info->write_algorithm);
402 ERROR("error executing str9x flash write algorithm");
403 return ERROR_FLASH_OPERATION_FAILED;
404 }
405
406 if (buf_get_u32(reg_params[3].value, 0, 32) != 0x80)
407 {
408 return ERROR_FLASH_OPERATION_FAILED;
409 }
410
411 buffer += thisrun_count * 2;
412 address += thisrun_count * 2;
413 count -= thisrun_count;
414 }
415
416 target_free_working_area(target, source);
417 target_free_working_area(target, str9x_info->write_algorithm);
418
419 destroy_reg_param(&reg_params[0]);
420 destroy_reg_param(&reg_params[1]);
421 destroy_reg_param(&reg_params[2]);
422 destroy_reg_param(&reg_params[3]);
423
424 return ERROR_OK;
425 }
426
427 int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
428 {
429 target_t *target = bank->target;
430 u32 words_remaining = (count / 2);
431 u32 bytes_remaining = (count & 0x00000001);
432 u32 address = bank->base + offset;
433 u32 bytes_written = 0;
434 u8 status;
435 u32 retval;
436 u32 check_address = offset;
437 u32 bank_adr;
438 int i;
439
440 if (bank->target->state != TARGET_HALTED)
441 {
442 return ERROR_TARGET_NOT_HALTED;
443 }
444
445 if (offset & 0x1)
446 {
447 WARNING("offset 0x%x breaks required 2-byte alignment", offset);
448 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
449 }
450
451 for (i = 0; i < bank->num_sectors; i++)
452 {
453 u32 sec_start = bank->sectors[i].offset;
454 u32 sec_end = sec_start + bank->sectors[i].size;
455
456 /* check if destination falls within the current sector */
457 if ((check_address >= sec_start) && (check_address < sec_end))
458 {
459 /* check if destination ends in the current sector */
460 if (offset + count < sec_end)
461 check_address = offset + count;
462 else
463 check_address = sec_end;
464 }
465 }
466
467 if (check_address != offset + count)
468 return ERROR_FLASH_DST_OUT_OF_BANK;
469
470 /* multiple half words (2-byte) to be programmed? */
471 if (words_remaining > 0)
472 {
473 /* try using a block write */
474 if ((retval = str9x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
475 {
476 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
477 {
478 /* if block write failed (no sufficient working area),
479 * we use normal (slow) single dword accesses */
480 WARNING("couldn't use block writes, falling back to single memory accesses");
481 }
482 else if (retval == ERROR_FLASH_OPERATION_FAILED)
483 {
484 ERROR("flash writing failed with error code: 0x%x", retval);
485 return ERROR_FLASH_OPERATION_FAILED;
486 }
487 }
488 else
489 {
490 buffer += words_remaining * 2;
491 address += words_remaining * 2;
492 words_remaining = 0;
493 }
494 }
495
496 while (words_remaining > 0)
497 {
498 bank_adr = address & ~0x03;
499
500 /* write data command */
501 target_write_u16(target, bank_adr, 0x40);
502 target->type->write_memory(target, address, 2, 1, buffer + bytes_written);
503
504 /* get status command */
505 target_write_u16(target, bank_adr, 0x70);
506
507 while (1) {
508 target_read_u8(target, bank_adr, &status);
509 if( status & 0x80 )
510 break;
511 usleep(1000);
512 }
513
514 /* clear status reg and read array */
515 target_write_u16(target, bank_adr, 0x50);
516 target_write_u16(target, bank_adr, 0xFF);
517
518 if (status & 0x10)
519 return ERROR_FLASH_OPERATION_FAILED;
520 else if (status & 0x02)
521 return ERROR_FLASH_OPERATION_FAILED;
522
523 bytes_written += 2;
524 words_remaining--;
525 address += 2;
526 }
527
528 if (bytes_remaining)
529 {
530 u8 last_halfword[2] = {0xff, 0xff};
531 int i = 0;
532
533 while(bytes_remaining > 0)
534 {
535 last_halfword[i++] = *(buffer + bytes_written);
536 bytes_remaining--;
537 bytes_written++;
538 }
539
540 bank_adr = address & ~0x03;
541
542 /* write data comamnd */
543 target_write_u16(target, bank_adr, 0x40);
544 target->type->write_memory(target, address, 2, 1, last_halfword);
545
546 /* query status command */
547 target_write_u16(target, bank_adr, 0x70);
548
549 while (1) {
550 target_read_u8(target, bank_adr, &status);
551 if( status & 0x80 )
552 break;
553 usleep(1000);
554 }
555
556 /* clear status reg and read array */
557 target_write_u16(target, bank_adr, 0x50);
558 target_write_u16(target, bank_adr, 0xFF);
559
560 if (status & 0x10)
561 return ERROR_FLASH_OPERATION_FAILED;
562 else if (status & 0x02)
563 return ERROR_FLASH_OPERATION_FAILED;
564 }
565
566 return ERROR_OK;
567 }
568
569 int str9x_probe(struct flash_bank_s *bank)
570 {
571 return ERROR_OK;
572 }
573
574 int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
575 {
576 return ERROR_OK;
577 }
578
579 int str9x_erase_check(struct flash_bank_s *bank)
580 {
581 return str9x_blank_check(bank, 0, bank->num_sectors - 1);
582 }
583
584 int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size)
585 {
586 snprintf(buf, buf_size, "str9x flash driver info" );
587 return ERROR_OK;
588 }
589
590 int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
591 {
592 str9x_flash_bank_t *str9x_info;
593 flash_bank_t *bank;
594 target_t *target = NULL;
595
596 if (argc < 4)
597 {
598 command_print(cmd_ctx, "usage: str9x flash_config <b0size> <b1size> <b0start> <b1start>");
599 return ERROR_OK;
600 }
601
602 bank = get_flash_bank_by_num(0);
603 str9x_info = bank->driver_priv;
604 target = bank->target;
605
606 if (bank->target->state != TARGET_HALTED)
607 {
608 return ERROR_TARGET_NOT_HALTED;
609 }
610
611 /* config flash controller */
612 target_write_u32(target, FLASH_BBSR, strtoul(args[0], NULL, 0));
613 target_write_u32(target, FLASH_NBBSR, strtoul(args[1], NULL, 0));
614 target_write_u32(target, FLASH_BBADR, (strtoul(args[2], NULL, 0) >> 2));
615 target_write_u32(target, FLASH_NBBADR, (strtoul(args[3], NULL, 0) >> 2));
616
617 /* set b18 instruction TCM order as per flash programming manual */
618 arm966e_write_cp15(target, 62, 0x40000);
619
620 /* enable flash bank 1 */
621 target_write_u32(target, FLASH_CR, 0x18);
622 return ERROR_OK;
623 }
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