- reset_run now works as expected on cortex-m3
[openocd.git] / src / flash / stm32x.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifndef STM32X_H
21 #define STM32X_H
22
23 #include "flash.h"
24 #include "target.h"
25
26 typedef struct stm32x_options_s
27 {
28 u16 RDP;
29 u16 user_options;
30 u16 protection[4];
31 } stm32x_options_t;
32
33 typedef struct stm32x_flash_bank_s
34 {
35 stm32x_options_t option_bytes;
36 working_area_t *write_algorithm;
37 } stm32x_flash_bank_t;
38
39 /* stm32x register locations */
40
41 #define STM32_FLASH_ACR 0x40022000
42 #define STM32_FLASH_KEYR 0x40022004
43 #define STM32_FLASH_OPTKEYR 0x40022008
44 #define STM32_FLASH_SR 0x4002200C
45 #define STM32_FLASH_CR 0x40022010
46 #define STM32_FLASH_AR 0x40022014
47 #define STM32_FLASH_OBR 0x4002201C
48 #define STM32_FLASH_WRPR 0x40022020
49
50 /* option byte location */
51
52 #define STM32_OB_RDP 0x1FFFF800
53 #define STM32_OB_USER 0x1FFFF802
54 #define STM32_OB_DATA0 0x1FFFF804
55 #define STM32_OB_DATA1 0x1FFFF806
56 #define STM32_OB_WRP0 0x1FFFF808
57 #define STM32_OB_WRP1 0x1FFFF80A
58 #define STM32_OB_WRP2 0x1FFFF80C
59 #define STM32_OB_WRP3 0x1FFFF80E
60
61 /* FLASH_CR register bits */
62
63 #define FLASH_PG (1<<0)
64 #define FLASH_PER (1<<1)
65 #define FLASH_MER (1<<2)
66 #define FLASH_OPTPG (1<<4)
67 #define FLASH_OPTER (1<<5)
68 #define FLASH_STRT (1<<6)
69 #define FLASH_LOCK (1<<7)
70 #define FLASH_OPTWRE (1<<9)
71
72 /* FLASH_SR regsiter bits */
73
74 #define FLASH_BSY (1<<0)
75 #define FLASH_PGERR (1<<2)
76 #define FLASH_WRPRTERR (1<<4)
77 #define FLASH_EOP (1<<5)
78
79 /* STM32_FLASH_OBR bit definitions (reading) */
80
81 #define OPT_ERROR 0
82 #define OPT_READOUT 1
83 #define OPT_RDWDGSW 2
84 #define OPT_RDRSTSTOP 3
85 #define OPT_RDRSTSTDBY 4
86
87 /* register unlock keys */
88
89 #define KEY1 0x45670123
90 #define KEY2 0xCDEF89AB
91
92 typedef struct stm32x_mem_layout_s {
93 u32 sector_start;
94 u32 sector_size;
95 } stm32x_mem_layout_t;
96
97 #endif /* STM32X_H */
98