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885f2cf0dd0796961566dc25dcc75446e96a7bf1
[openocd.git] / src / flash / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "stm32x.h"
27 #include "flash.h"
28 #include "target.h"
29 #include "log.h"
30 #include "armv7m.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
33
34 #include <stdlib.h>
35 #include <string.h>
36
37 int stm32x_register_commands(struct command_context_s *cmd_ctx);
38 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
39 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
40 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
41 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
42 int stm32x_probe(struct flash_bank_s *bank);
43 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 int stm32x_protect_check(struct flash_bank_s *bank);
45 int stm32x_erase_check(struct flash_bank_s *bank);
46 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
47
48 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53
54 flash_driver_t stm32x_flash =
55 {
56 .name = "stm32x",
57 .register_commands = stm32x_register_commands,
58 .flash_bank_command = stm32x_flash_bank_command,
59 .erase = stm32x_erase,
60 .protect = stm32x_protect,
61 .write = stm32x_write,
62 .probe = stm32x_probe,
63 .erase_check = stm32x_erase_check,
64 .protect_check = stm32x_protect_check,
65 .info = stm32x_info
66 };
67
68 int stm32x_register_commands(struct command_context_s *cmd_ctx)
69 {
70 command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
71
72 register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
73 "lock device");
74 register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
75 "unlock protected device");
76 register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
77 "mass erase device");
78 register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
79 "read device option bytes");
80 register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
81 "write device option bytes");
82 return ERROR_OK;
83 }
84
85 int stm32x_build_block_list(struct flash_bank_s *bank)
86 {
87 int i;
88 int num_sectors = 0;
89
90 switch (bank->size)
91 {
92 case 32 * 1024:
93 num_sectors = 32;
94 break;
95 case 64 * 1024:
96 num_sectors = 64;
97 break;
98 case 128 * 1024:
99 num_sectors = 128;
100 break;
101 default:
102 ERROR("BUG: unknown bank->size encountered");
103 exit(-1);
104 }
105
106 bank->num_sectors = num_sectors;
107 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
108
109 for (i = 0; i < num_sectors; i++)
110 {
111 bank->sectors[i].offset = i * 1024;
112 bank->sectors[i].size = 1024;
113 bank->sectors[i].is_erased = -1;
114 bank->sectors[i].is_protected = 1;
115 }
116
117 return ERROR_OK;
118 }
119
120 /* flash bank stm32x <base> <size> 0 0 <target#>
121 */
122 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
123 {
124 stm32x_flash_bank_t *stm32x_info;
125
126 if (argc < 6)
127 {
128 WARNING("incomplete flash_bank stm32x configuration");
129 return ERROR_FLASH_BANK_INVALID;
130 }
131
132 stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
133 bank->driver_priv = stm32x_info;
134
135 if (bank->base != 0x08000000)
136 {
137 WARNING("overriding flash base address for STM32x device with 0x08000000");
138 bank->base = 0x08000000;
139 }
140
141 stm32x_build_block_list(bank);
142
143 stm32x_info->write_algorithm = NULL;
144
145 return ERROR_OK;
146 }
147
148 u32 stm32x_get_flash_status(flash_bank_t *bank)
149 {
150 target_t *target = bank->target;
151 u32 status;
152
153 target_read_u32(target, STM32_FLASH_SR, &status);
154
155 return status;
156 }
157
158 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
159 {
160 u32 status;
161
162 /* wait for busy to clear */
163 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
164 {
165 DEBUG("status: 0x%x", status);
166 usleep(1000);
167 }
168
169 return status;
170 }
171
172 int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)
173 {
174 target_t *target = bank->target;
175 u8 *buffer;
176 int i;
177 int nBytes;
178
179 if ((first < 0) || (last > bank->num_sectors))
180 return ERROR_FLASH_SECTOR_INVALID;
181
182 if (target->state != TARGET_HALTED)
183 {
184 return ERROR_TARGET_NOT_HALTED;
185 }
186
187 buffer = malloc(256);
188
189 for (i = first; i <= last; i++)
190 {
191 bank->sectors[i].is_erased = 1;
192
193 target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
194
195 for (nBytes = 0; nBytes < 256; nBytes++)
196 {
197 if (buffer[nBytes] != 0xFF)
198 {
199 bank->sectors[i].is_erased = 0;
200 break;
201 }
202 }
203 }
204
205 free(buffer);
206
207 return ERROR_OK;
208 }
209
210 int stm32x_protect_check(struct flash_bank_s *bank)
211 {
212 target_t *target = bank->target;
213
214 u32 protection;
215 int i, s;
216
217 if (target->state != TARGET_HALTED)
218 {
219 return ERROR_TARGET_NOT_HALTED;
220 }
221
222 /* each bit refers to a 4bank protection */
223 target_read_u32(target, STM32_FLASH_WRPR, &protection);
224
225 for (i = 0; i < 32; i++)
226 {
227 int set = 1;
228
229 if( protection & (1 << i))
230 set = 0;
231
232 for (s = 0; s < 4; s++)
233 bank->sectors[(i * 4) + s].is_protected = set;
234 }
235
236 return ERROR_OK;
237 }
238
239 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
240 {
241 target_t *target = bank->target;
242
243 int i;
244 u32 status;
245
246 /* unlock flash registers */
247 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
248 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
249
250 if (target->state != TARGET_HALTED)
251 {
252 return ERROR_TARGET_NOT_HALTED;
253 }
254
255 for (i = first; i <= last; i++)
256 {
257 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
258 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
259 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
260
261 status = stm32x_wait_status_busy(bank, 10);
262
263 if( status & FLASH_WRPRTERR )
264 return ERROR_FLASH_OPERATION_FAILED;
265 if( status & FLASH_PGERR )
266 return ERROR_FLASH_OPERATION_FAILED;
267 bank->sectors[i].is_erased = 1;
268 }
269
270 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
271
272 return ERROR_OK;
273 }
274
275 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
276 {
277 target_t *target = bank->target;
278
279 if (target->state != TARGET_HALTED)
280 {
281 return ERROR_TARGET_NOT_HALTED;
282 }
283
284 return ERROR_OK;
285 }
286
287 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
288 {
289 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
290 target_t *target = bank->target;
291 u32 buffer_size = 8192;
292 working_area_t *source;
293 u32 address = bank->base + offset;
294 reg_param_t reg_params[4];
295 armv7m_algorithm_t armv7m_info;
296 int retval = ERROR_OK;
297
298 u8 stm32x_flash_write_code[] = {
299 /* write: */
300 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
301 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
302 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
303 0x23, 0x60, /* str r3, [r4, #0] */
304 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
305 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
306 /* busy: */
307 0x2B, 0x68, /* ldr r3, [r5, #0] */
308 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
309 0xFB, 0xD0, /* beq busy */
310 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
311 0x01, 0xD1, /* bne exit */
312 0x01, 0x3A, /* subs r2, r2, #1 */
313 0xED, 0xD1, /* bne write */
314 /* exit: */
315 0xFE, 0xE7, /* b exit */
316 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
317 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
318 };
319
320 /* flash write code */
321 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
322 {
323 WARNING("no working area available, can't do block memory writes");
324 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
325 };
326
327 target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
328
329 /* memory buffer */
330 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
331 {
332 buffer_size /= 2;
333 if (buffer_size <= 256)
334 {
335 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
336 if (stm32x_info->write_algorithm)
337 target_free_working_area(target, stm32x_info->write_algorithm);
338
339 WARNING("no large enough working area available, can't do block memory writes");
340 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
341 }
342 };
343
344 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
345 armv7m_info.core_mode = ARMV7M_MODE_ANY;
346 armv7m_info.core_state = ARMV7M_STATE_THUMB;
347
348 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
349 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
350 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
351 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
352
353 while (count > 0)
354 {
355 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
356
357 target_write_buffer(target, source->address, thisrun_count * 2, buffer);
358
359 buf_set_u32(reg_params[0].value, 0, 32, source->address);
360 buf_set_u32(reg_params[1].value, 0, 32, address);
361 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
362
363 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
364 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
365 {
366 ERROR("error executing str7x flash write algorithm");
367 break;
368 }
369
370 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
371 {
372 retval = ERROR_FLASH_OPERATION_FAILED;
373 break;
374 }
375
376 buffer += thisrun_count * 2;
377 address += thisrun_count * 2;
378 count -= thisrun_count;
379 }
380
381 target_free_working_area(target, source);
382 target_free_working_area(target, stm32x_info->write_algorithm);
383
384 destroy_reg_param(&reg_params[0]);
385 destroy_reg_param(&reg_params[1]);
386 destroy_reg_param(&reg_params[2]);
387 destroy_reg_param(&reg_params[3]);
388
389 return retval;
390 }
391
392 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
393 {
394 target_t *target = bank->target;
395 u32 words_remaining = (count / 2);
396 u32 bytes_remaining = (count & 0x00000001);
397 u32 address = bank->base + offset;
398 u32 bytes_written = 0;
399 u8 status;
400 u32 retval;
401
402 if (target->state != TARGET_HALTED)
403 {
404 return ERROR_TARGET_NOT_HALTED;
405 }
406
407 if (offset & 0x1)
408 {
409 WARNING("offset 0x%x breaks required 2-byte alignment", offset);
410 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
411 }
412
413 /* unlock flash registers */
414 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
415 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
416
417 /* multiple half words (2-byte) to be programmed? */
418 if (words_remaining > 0)
419 {
420 /* try using a block write */
421 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
422 {
423 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
424 {
425 /* if block write failed (no sufficient working area),
426 * we use normal (slow) single dword accesses */
427 WARNING("couldn't use block writes, falling back to single memory accesses");
428 }
429 else if (retval == ERROR_FLASH_OPERATION_FAILED)
430 {
431 ERROR("flash writing failed with error code: 0x%x", retval);
432 return ERROR_FLASH_OPERATION_FAILED;
433 }
434 }
435 else
436 {
437 buffer += words_remaining * 2;
438 address += words_remaining * 2;
439 words_remaining = 0;
440 }
441 }
442
443 while (words_remaining > 0)
444 {
445 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
446 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
447
448 status = stm32x_wait_status_busy(bank, 5);
449
450 if( status & FLASH_WRPRTERR )
451 return ERROR_FLASH_OPERATION_FAILED;
452 if( status & FLASH_PGERR )
453 return ERROR_FLASH_OPERATION_FAILED;
454
455 bytes_written += 2;
456 words_remaining--;
457 address += 2;
458 }
459
460 if (bytes_remaining)
461 {
462 u8 last_halfword[2] = {0xff, 0xff};
463 int i = 0;
464
465 while(bytes_remaining > 0)
466 {
467 last_halfword[i++] = *(buffer + bytes_written);
468 bytes_remaining--;
469 bytes_written++;
470 }
471
472 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
473 target_write_u16(target, address, *(u16*)last_halfword);
474
475 status = stm32x_wait_status_busy(bank, 5);
476
477 if( status & FLASH_WRPRTERR )
478 return ERROR_FLASH_OPERATION_FAILED;
479 if( status & FLASH_PGERR )
480 return ERROR_FLASH_OPERATION_FAILED;
481 }
482
483 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
484
485 return ERROR_OK;
486 }
487
488 int stm32x_probe(struct flash_bank_s *bank)
489 {
490 return ERROR_OK;
491 }
492
493 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
494 {
495 return ERROR_OK;
496 }
497
498 int stm32x_erase_check(struct flash_bank_s *bank)
499 {
500 return stm32x_blank_check(bank, 0, bank->num_sectors - 1);
501 }
502
503 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
504 {
505 snprintf(buf, buf_size, "stm32x flash driver info" );
506 return ERROR_OK;
507 }
508
509 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
510 {
511 flash_bank_t *bank;
512 u32 status;
513 target_t *target = NULL;
514 stm32x_flash_bank_t *stm32x_info = NULL;
515
516 if (argc < 1)
517 {
518 command_print(cmd_ctx, "stm32x lock <bank>");
519 return ERROR_OK;
520 }
521
522 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
523 if (!bank)
524 {
525 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
526 return ERROR_OK;
527 }
528
529 stm32x_info = bank->driver_priv;
530
531 target = bank->target;
532
533 if (target->state != TARGET_HALTED)
534 {
535 return ERROR_TARGET_NOT_HALTED;
536 }
537
538 /* unlock flash registers */
539 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
540 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
541
542 /* unlock option flash registers */
543 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
544 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
545
546 /* erase option bytes */
547 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
548 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
549
550 status = stm32x_wait_status_busy(bank, 10);
551
552 if( status & FLASH_WRPRTERR )
553 return ERROR_FLASH_OPERATION_FAILED;
554 if( status & FLASH_PGERR )
555 return ERROR_FLASH_OPERATION_FAILED;
556
557 /* program option bytes */
558 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
559
560 /* set readout protection */
561 target_write_u16(target, STM32_OB_ADR, 0);
562
563 status = stm32x_wait_status_busy(bank, 10);
564
565 if( status & FLASH_WRPRTERR )
566 return ERROR_FLASH_OPERATION_FAILED;
567 if( status & FLASH_PGERR )
568 return ERROR_FLASH_OPERATION_FAILED;
569
570 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
571 command_print(cmd_ctx, "stm32x locked");
572
573 return ERROR_OK;
574 }
575
576 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
577 {
578 flash_bank_t *bank;
579 u32 status;
580 target_t *target = NULL;
581 stm32x_flash_bank_t *stm32x_info = NULL;
582
583 if (argc < 1)
584 {
585 command_print(cmd_ctx, "stm32x unlock <bank>");
586 return ERROR_OK;
587 }
588
589 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
590 if (!bank)
591 {
592 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
593 return ERROR_OK;
594 }
595
596 stm32x_info = bank->driver_priv;
597
598 target = bank->target;
599
600 if (target->state != TARGET_HALTED)
601 {
602 return ERROR_TARGET_NOT_HALTED;
603 }
604
605 /* unlock flash registers */
606 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
607 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
608
609 /* unlock option flash registers */
610 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
611 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
612
613 /* erase option bytes */
614 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
615 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
616
617 status = stm32x_wait_status_busy(bank, 10);
618
619 if( status & FLASH_WRPRTERR )
620 return ERROR_FLASH_OPERATION_FAILED;
621 if( status & FLASH_PGERR )
622 return ERROR_FLASH_OPERATION_FAILED;
623
624 /* program option bytes */
625 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
626
627 /* clear readout protection and complementary option bytes */
628 target_write_u16(target, STM32_OB_ADR, 0x5AA5);
629
630 status = stm32x_wait_status_busy(bank, 10);
631
632 if( status & FLASH_WRPRTERR )
633 return ERROR_FLASH_OPERATION_FAILED;
634 if( status & FLASH_PGERR )
635 return ERROR_FLASH_OPERATION_FAILED;
636
637 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
638 command_print(cmd_ctx, "stm32x unlocked");
639
640 return ERROR_OK;
641 }
642
643 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
644 {
645 flash_bank_t *bank;
646 u32 optionbyte;
647 target_t *target = NULL;
648 stm32x_flash_bank_t *stm32x_info = NULL;
649
650 if (argc < 1)
651 {
652 command_print(cmd_ctx, "stm32x options_read <bank>");
653 return ERROR_OK;
654 }
655
656 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
657 if (!bank)
658 {
659 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
660 return ERROR_OK;
661 }
662
663 stm32x_info = bank->driver_priv;
664
665 target = bank->target;
666
667 if (target->state != TARGET_HALTED)
668 {
669 return ERROR_TARGET_NOT_HALTED;
670 }
671
672 //target_read_u32(target, STM32_OB_ADR, &optionbyte);
673 //command_print(cmd_ctx, "Option Byte 0: 0x%x", optionbyte);
674 //target_read_u32(target, STM32_OB_ADR+4, &optionbyte);
675 //command_print(cmd_ctx, "Option Byte 1: 0x%x", optionbyte);
676 //target_read_u32(target, STM32_OB_ADR+8, &optionbyte);
677 //command_print(cmd_ctx, "Option Byte 2: 0x%x", optionbyte);
678 //target_read_u32(target, STM32_OB_ADR+12, &optionbyte);
679 //command_print(cmd_ctx, "Option Byte 3: 0x%x", optionbyte);
680
681 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
682 command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
683
684 if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
685 command_print(cmd_ctx, "Option Byte Complement Error");
686
687 if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
688 command_print(cmd_ctx, "Readout Protection On");
689 else
690 command_print(cmd_ctx, "Readout Protection Off");
691
692 if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
693 command_print(cmd_ctx, "Software Watchdog");
694 else
695 command_print(cmd_ctx, "Hardware Watchdog");
696
697 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
698 command_print(cmd_ctx, "Stop: No reset generated");
699 else
700 command_print(cmd_ctx, "Stop: Reset generated");
701
702 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
703 command_print(cmd_ctx, "Standby: No reset generated");
704 else
705 command_print(cmd_ctx, "Standby: Reset generated");
706
707 return ERROR_OK;
708 }
709
710 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
711 {
712 flash_bank_t *bank;
713 target_t *target = NULL;
714 stm32x_flash_bank_t *stm32x_info = NULL;
715 u16 optionbyte = 0xF8;
716 u32 status;
717
718 if (argc < 4)
719 {
720 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
721 return ERROR_OK;
722 }
723
724 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
725 if (!bank)
726 {
727 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
728 return ERROR_OK;
729 }
730
731 stm32x_info = bank->driver_priv;
732
733 target = bank->target;
734
735 if (target->state != TARGET_HALTED)
736 {
737 return ERROR_TARGET_NOT_HALTED;
738 }
739
740 if (strcmp(args[1], "SWWDG") == 0)
741 {
742 optionbyte |= (1<<0);
743 }
744 else
745 {
746 optionbyte &= ~(1<<0);
747 }
748
749 if (strcmp(args[2], "NORSTSTNDBY") == 0)
750 {
751 optionbyte |= (1<<1);
752 }
753 else
754 {
755 optionbyte &= ~(1<<1);
756 }
757
758 if (strcmp(args[3], "NORSTSTOP") == 0)
759 {
760 optionbyte |= (1<<2);
761 }
762 else
763 {
764 optionbyte &= ~(1<<2);
765 }
766
767 /* unlock flash registers */
768 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
769 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
770
771 /* unlock option flash registers */
772 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
773 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
774
775 /* program option bytes */
776 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
777
778 /* write option byte */
779 target_write_u16(target, STM32_OB_ADR + 2, optionbyte);
780
781 status = stm32x_wait_status_busy(bank, 10);
782
783 if( status & FLASH_WRPRTERR )
784 return ERROR_FLASH_OPERATION_FAILED;
785 if( status & FLASH_PGERR )
786 return ERROR_FLASH_OPERATION_FAILED;
787
788 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
789
790 return ERROR_OK;
791 }
792
793 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
794 {
795 flash_bank_t *bank;
796 u32 status;
797 target_t *target = NULL;
798 stm32x_flash_bank_t *stm32x_info = NULL;
799
800 if (argc < 1)
801 {
802 command_print(cmd_ctx, "stm32x mass_erase <bank>");
803 return ERROR_OK;
804 }
805
806 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
807 if (!bank)
808 {
809 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
810 return ERROR_OK;
811 }
812
813 stm32x_info = bank->driver_priv;
814
815 target = bank->target;
816
817 if (target->state != TARGET_HALTED)
818 {
819 return ERROR_TARGET_NOT_HALTED;
820 }
821
822 /* unlock option flash registers */
823 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
824 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
825
826 /* mass erase flash memory */
827 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
828 target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
829
830 status = stm32x_wait_status_busy(bank, 10);
831
832 if( status & FLASH_WRPRTERR )
833 return ERROR_FLASH_OPERATION_FAILED;
834 if( status & FLASH_PGERR )
835 return ERROR_FLASH_OPERATION_FAILED;
836
837 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
838
839 return ERROR_OK;
840 }
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