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[openocd.git] / src / flash / stellaris.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 /***************************************************************************
22 * STELLARIS is tested on LM3S811
23 *
24 *
25 *
26 ***************************************************************************/
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "replacements.h"
32
33 #include "stellaris.h"
34 #include "cortex_m3.h"
35
36 #include "flash.h"
37 #include "target.h"
38 #include "log.h"
39 #include "binarybuffer.h"
40 #include "types.h"
41
42 #include <stdlib.h>
43 #include <string.h>
44 #include <unistd.h>
45
46 #define DID0_VER(did0) ((did0>>28)&0x07)
47 int stellaris_register_commands(struct command_context_s *cmd_ctx);
48 int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
49 int stellaris_erase(struct flash_bank_s *bank, int first, int last);
50 int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last);
51 int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
52 int stellaris_auto_probe(struct flash_bank_s *bank);
53 int stellaris_probe(struct flash_bank_s *bank);
54 int stellaris_erase_check(struct flash_bank_s *bank);
55 int stellaris_protect_check(struct flash_bank_s *bank);
56 int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size);
57
58 int stellaris_read_part_info(struct flash_bank_s *bank);
59 u32 stellaris_get_flash_status(flash_bank_t *bank);
60 void stellaris_set_flash_mode(flash_bank_t *bank,int mode);
61 u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
62
63 int stellaris_read_part_info(struct flash_bank_s *bank);
64
65 flash_driver_t stellaris_flash =
66 {
67 .name = "stellaris",
68 .register_commands = stellaris_register_commands,
69 .flash_bank_command = stellaris_flash_bank_command,
70 .erase = stellaris_erase,
71 .protect = stellaris_protect,
72 .write = stellaris_write,
73 .probe = stellaris_probe,
74 .auto_probe = stellaris_auto_probe,
75 .erase_check = stellaris_erase_check,
76 .protect_check = stellaris_protect_check,
77 .info = stellaris_info
78 };
79
80
81 struct {
82 u32 partno;
83 char *partname;
84 } StellarisParts[] =
85 {
86 {0x01,"LM3S101"},
87 {0x02,"LM3S102"},
88 {0x19,"LM3S300"},
89 {0x11,"LM3S301"},
90 {0x12,"LM3S310"},
91 {0x1A,"LM3S308"},
92 {0x13,"LM3S315"},
93 {0x14,"LM3S316"},
94 {0x17,"LM3S317"},
95 {0x18,"LM3S318"},
96 {0x15,"LM3S328"},
97 {0x2A,"LM3S600"},
98 {0x21,"LM3S601"},
99 {0x2B,"LM3S608"},
100 {0x22,"LM3S610"},
101 {0x23,"LM3S611"},
102 {0x24,"LM3S612"},
103 {0x25,"LM3S613"},
104 {0x26,"LM3S615"},
105 {0x28,"LM3S617"},
106 {0x29,"LM3S618"},
107 {0x27,"LM3S628"},
108 {0x38,"LM3S800"},
109 {0x31,"LM3S801"},
110 {0x39,"LM3S808"},
111 {0x32,"LM3S811"},
112 {0x33,"LM3S812"},
113 {0x34,"LM3S815"},
114 {0x36,"LM3S817"},
115 {0x37,"LM3S818"},
116 {0x35,"LM3S828"},
117 {0x51,"LM3S2110"},
118 {0x52,"LM3S2739"},
119 {0x53,"LM3S2651"},
120 {0x54,"LM3S2939"},
121 {0x55,"LM3S2965"},
122 {0x56,"LM3S2432"},
123 {0x57,"LM3S2620"},
124 {0x58,"LM3S2950"},
125 {0x59,"LM3S2412"},
126 {0x5A,"LM3S2533"},
127 {0x61,"LM3S8630"},
128 {0x62,"LM3S8970"},
129 {0x63,"LM3S8730"},
130 {0x64,"LM3S8530"},
131 {0x65,"LM3S8930"},
132 {0x71,"LM3S6610"},
133 {0x72,"LM3S6950"},
134 {0x73,"LM3S6965"},
135 {0x74,"LM3S6110"},
136 {0x75,"LM3S6432"},
137 {0x76,"LM3S6537"},
138 {0x77,"LM3S6753"},
139 {0x78,"LM3S6952"},
140 {0x82,"LM3S6422"},
141 {0x83,"LM3S6633"},
142 {0x84,"LM3S2139"},
143 {0x85,"LM3S2637"},
144 {0x86,"LM3S8738"},
145 {0x88,"LM3S8938"},
146 {0x89,"LM3S6938"},
147 {0x8B,"LM3S6637"},
148 {0x8C,"LM3S8933"},
149 {0x8D,"LM3S8733"},
150 {0x8E,"LM3S8538"},
151 {0x8F,"LM3S2948"},
152 {0xA1,"LM3S6100"},
153 {0xA2,"LM3S2410"},
154 {0xA3,"LM3S6730"},
155 {0xA4,"LM3S2730"},
156 {0xA5,"LM3S6420"},
157 {0xA6,"LM3S8962"},
158 {0xB3,"LM3S1635"},
159 {0xB4,"LM3S1850"},
160 {0xB5,"LM3S1960"},
161 {0xB7,"LM3S1937"},
162 {0xB8,"LM3S1968"},
163 {0xB9,"LM3S1751"},
164 {0xBA,"LM3S1439"},
165 {0xBB,"LM3S1512"},
166 {0xBC,"LM3S1435"},
167 {0xBD,"LM3S1637"},
168 {0xBE,"LM3S1958"},
169 {0xBF,"LM3S1110"},
170 {0xC0,"LM3S1620"},
171 {0xC1,"LM3S1150"},
172 {0xC2,"LM3S1165"},
173 {0xC3,"LM3S1133"},
174 {0xC4,"LM3S1162"},
175 {0xC5,"LM3S1138"},
176 {0xC6,"LM3S1332"},
177 {0xC7,"LM3S1538"},
178 {0xD0,"LM3S6815"},
179 {0xD1,"LM3S6816"},
180 {0xD2,"LM3S6915"},
181 {0xD3,"LM3S6916"},
182 {0xD4,"LM3S2016"},
183 {0xD5,"LM3S1615"},
184 {0xD6,"LM3S1616"},
185 {0xD7,"LM3S8971"},
186 {0xD8,"LM3S1108"},
187 {0xD9,"LM3S1101"},
188 {0xDA,"LM3S1608"},
189 {0xDB,"LM3S1601"},
190 {0xDC,"LM3S1918"},
191 {0xDD,"LM3S1911"},
192 {0xDE,"LM3S2108"},
193 {0xDF,"LM3S2101"},
194 {0xE0,"LM3S2608"},
195 {0xE1,"LM3S2601"},
196 {0xE2,"LM3S2918"},
197 {0xE3,"LM3S2911"},
198 {0xE4,"LM3S6118"},
199 {0xE5,"LM3S6111"},
200 {0xE6,"LM3S6618"},
201 {0xE7,"LM3S6611"},
202 {0xE8,"LM3S6918"},
203 {0xE9,"LM3S6911"},
204 {0,"Unknown part"}
205 };
206
207 char * StellarisClassname[2] =
208 {
209 "Sandstorm",
210 "Fury"
211 };
212
213 /***************************************************************************
214 * openocd command interface *
215 ***************************************************************************/
216
217 /* flash_bank stellaris <base> <size> 0 0 <target#>
218 */
219 int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
220 {
221 stellaris_flash_bank_t *stellaris_info;
222
223 if (argc < 6)
224 {
225 WARNING("incomplete flash_bank stellaris configuration");
226 return ERROR_FLASH_BANK_INVALID;
227 }
228
229 stellaris_info = calloc(sizeof(stellaris_flash_bank_t),1);
230 bank->base = 0x0;
231 bank->driver_priv = stellaris_info;
232
233 stellaris_info->target_name = "Unknown target";
234
235 /* part wasn't probed for info yet */
236 stellaris_info->did1 = 0;
237
238 /* TODO Use an optional main oscillator clock rate in kHz from arg[6] */
239 return ERROR_OK;
240 }
241
242 int stellaris_register_commands(struct command_context_s *cmd_ctx)
243 {
244 /*
245 command_t *stellaris_cmd = register_command(cmd_ctx, NULL, "stellaris", NULL, COMMAND_ANY, NULL);
246 register_command(cmd_ctx, stellaris_cmd, "gpnvm", stellaris_handle_gpnvm_command, COMMAND_EXEC,
247 "stellaris gpnvm <num> <bit> set|clear, set or clear stellaris gpnvm bit");
248 */
249 return ERROR_OK;
250 }
251
252 int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
253 {
254 int printed, device_class;
255 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
256
257 stellaris_read_part_info(bank);
258
259 if (stellaris_info->did1 == 0)
260 {
261 printed = snprintf(buf, buf_size, "Cannot identify target as a Stellaris\n");
262 buf += printed;
263 buf_size -= printed;
264 return ERROR_FLASH_OPERATION_FAILED;
265 }
266
267 if (DID0_VER(stellaris_info->did0)>0)
268 {
269 device_class = (stellaris_info->did0>>16)&0xFF;
270 }
271 else
272 {
273 device_class = 0;
274 }
275 printed = snprintf(buf, buf_size, "\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n",
276 device_class, StellarisClassname[device_class], stellaris_info->target_name,
277 'A' + (stellaris_info->did0>>8)&0xFF, (stellaris_info->did0)&0xFF);
278 buf += printed;
279 buf_size -= printed;
280
281 printed = snprintf(buf, buf_size, "did1: 0x%8.8x, arch: 0x%4.4x, eproc: %s, ramsize:%ik, flashsize: %ik\n",
282 stellaris_info->did1, stellaris_info->did1, "ARMV7M", (1+(stellaris_info->dc0>>16)&0xFFFF)/4, (1+stellaris_info->dc0&0xFFFF)*2);
283 buf += printed;
284 buf_size -= printed;
285
286 printed = snprintf(buf, buf_size, "master clock(estimated): %ikHz, rcc is 0x%x \n", stellaris_info->mck_freq / 1000, stellaris_info->rcc);
287 buf += printed;
288 buf_size -= printed;
289
290 if (stellaris_info->num_lockbits>0) {
291 printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", stellaris_info->pagesize, stellaris_info->num_lockbits, stellaris_info->lockbits,stellaris_info->num_pages/stellaris_info->num_lockbits);
292 buf += printed;
293 buf_size -= printed;
294 }
295 return ERROR_OK;
296 }
297
298 /***************************************************************************
299 * chip identification and status *
300 ***************************************************************************/
301
302 u32 stellaris_get_flash_status(flash_bank_t *bank)
303 {
304 target_t *target = bank->target;
305 u32 fmc;
306
307 target_read_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, &fmc);
308
309 return fmc;
310 }
311
312 /** Read clock configuration and set stellaris_info->usec_clocks*/
313
314 void stellaris_read_clock_info(flash_bank_t *bank)
315 {
316 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
317 target_t *target = bank->target;
318 u32 rcc, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
319 unsigned long mainfreq;
320
321 target_read_u32(target, SCB_BASE|RCC, &rcc);
322 DEBUG("Stellaris RCC %x",rcc);
323 target_read_u32(target, SCB_BASE|PLLCFG, &pllcfg);
324 DEBUG("Stellaris PLLCFG %x",pllcfg);
325 stellaris_info->rcc = rcc;
326
327 sysdiv = (rcc>>23)&0xF;
328 usesysdiv = (rcc>>22)&0x1;
329 bypass = (rcc>>11)&0x1;
330 oscsrc = (rcc>>4)&0x3;
331 /* xtal = (rcc>>6)&0xF; */
332 switch (oscsrc)
333 {
334 case 0:
335 mainfreq = 6000000; /* Default xtal */
336 break;
337 case 1:
338 mainfreq = 22500000; /* Internal osc. 15 MHz +- 50% */
339 break;
340 case 2:
341 mainfreq = 5625000; /* Internal osc. / 4 */
342 break;
343 case 3:
344 WARNING("Invalid oscsrc (3) in rcc register");
345 mainfreq = 6000000;
346 break;
347 }
348
349 if (!bypass)
350 mainfreq = 200000000; /* PLL out frec */
351
352 if (usesysdiv)
353 stellaris_info->mck_freq = mainfreq/(1+sysdiv);
354 else
355 stellaris_info->mck_freq = mainfreq;
356
357 /* Forget old flash timing */
358 stellaris_set_flash_mode(bank,0);
359 }
360
361 /* Setup the timimg registers */
362 void stellaris_set_flash_mode(flash_bank_t *bank,int mode)
363 {
364 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
365 target_t *target = bank->target;
366
367 u32 usecrl = (stellaris_info->mck_freq/1000000ul-1);
368 DEBUG("usecrl = %i",usecrl);
369 target_write_u32(target, SCB_BASE|USECRL , usecrl);
370
371 }
372
373 u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
374 {
375 u32 status;
376
377 /* Stellaris waits for cmdbit to clear */
378 while (((status = stellaris_get_flash_status(bank)) & waitbits) && (timeout-- > 0))
379 {
380 DEBUG("status: 0x%x", status);
381 usleep(1000);
382 }
383
384 /* Flash errors are reflected in the FLASH_CRIS register */
385
386 return status;
387 }
388
389
390 /* Send one command to the flash controller */
391 int stellaris_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen)
392 {
393 u32 fmc;
394 // stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
395 target_t *target = bank->target;
396
397 fmc = FMC_WRKEY | cmd;
398 target_write_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, fmc);
399 DEBUG("Flash command: 0x%x", fmc);
400
401 if (stellaris_wait_status_busy(bank, cmd, 100))
402 {
403 return ERROR_FLASH_OPERATION_FAILED;
404 }
405
406 return ERROR_OK;
407 }
408
409 /* Read device id register, main clock frequency register and fill in driver info structure */
410 int stellaris_read_part_info(struct flash_bank_s *bank)
411 {
412 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
413 target_t *target = bank->target;
414 u32 did0,did1, ver, fam, status;
415 int i;
416
417 /* Read and parse chip identification register */
418 target_read_u32(target, SCB_BASE|DID0, &did0);
419 target_read_u32(target, SCB_BASE|DID1, &did1);
420 target_read_u32(target, SCB_BASE|DC0, &stellaris_info->dc0);
421 target_read_u32(target, SCB_BASE|DC1, &stellaris_info->dc1);
422 DEBUG("did0 0x%x, did1 0x%x, dc0 0x%x, dc1 0x%x",did0, did1, stellaris_info->dc0,stellaris_info->dc1);
423
424 ver = did0 >> 28;
425 if((ver != 0) && (ver != 1))
426 {
427 WARNING("Unknown did0 version, cannot identify target");
428 return ERROR_FLASH_OPERATION_FAILED;
429 }
430
431 ver = did1 >> 28;
432 fam = (did1 >> 24) & 0xF;
433 if(((ver != 0) && (ver != 1)) || (fam != 0))
434 {
435 WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris");
436 }
437
438 if (did1 == 0)
439 {
440 WARNING("Cannot identify target as a Stellaris");
441 return ERROR_FLASH_OPERATION_FAILED;
442 }
443
444 for (i=0;StellarisParts[i].partno;i++)
445 {
446 if (StellarisParts[i].partno==((did1>>16)&0xFF))
447 break;
448 }
449
450 stellaris_info->target_name = StellarisParts[i].partname;
451
452 stellaris_info->did0 = did0;
453 stellaris_info->did1 = did1;
454
455 stellaris_info->num_lockbits = 1+stellaris_info->dc0&0xFFFF;
456 stellaris_info->num_pages = 2*(1+stellaris_info->dc0&0xFFFF);
457 stellaris_info->pagesize = 1024;
458 bank->size = 1024*stellaris_info->num_pages;
459 stellaris_info->pages_in_lockregion = 2;
460 target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits);
461
462 // Read main and master clock freqency register
463 stellaris_read_clock_info(bank);
464
465 status = stellaris_get_flash_status(bank);
466
467 return ERROR_OK;
468 }
469
470 /***************************************************************************
471 * flash operations *
472 ***************************************************************************/
473
474 int stellaris_erase_check(struct flash_bank_s *bank)
475 {
476 /*
477
478 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
479 target_t *target = bank->target;
480 int i;
481
482 */
483
484 return ERROR_OK;
485 }
486
487 int stellaris_protect_check(struct flash_bank_s *bank)
488 {
489 u32 status;
490
491 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
492
493 if (stellaris_info->did1 == 0)
494 {
495 stellaris_read_part_info(bank);
496 }
497
498 if (stellaris_info->did1 == 0)
499 {
500 WARNING("Cannot identify target as an AT91SAM");
501 return ERROR_FLASH_OPERATION_FAILED;
502 }
503
504 status = stellaris_get_flash_status(bank);
505 stellaris_info->lockbits = status >> 16;
506
507 return ERROR_OK;
508 }
509
510 int stellaris_erase(struct flash_bank_s *bank, int first, int last)
511 {
512 int banknr;
513 u32 flash_fmc, flash_cris;
514 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
515 target_t *target = bank->target;
516
517 if (stellaris_info->did1 == 0)
518 {
519 stellaris_read_part_info(bank);
520 }
521
522 if (stellaris_info->did1 == 0)
523 {
524 WARNING("Cannot identify target as Stellaris");
525 return ERROR_FLASH_OPERATION_FAILED;
526 }
527
528 if ((first < 0) || (last < first) || (last >= stellaris_info->num_pages))
529 {
530 return ERROR_FLASH_SECTOR_INVALID;
531 }
532
533 /* Configure the flash controller timing */
534 stellaris_read_clock_info(bank);
535 stellaris_set_flash_mode(bank,0);
536
537 /* Clear and disable flash programming interrupts */
538 target_write_u32(target, FLASH_CIM, 0);
539 target_write_u32(target, FLASH_MISC, PMISC|AMISC);
540
541 if ((first == 0) && (last == (stellaris_info->num_pages-1)))
542 {
543 target_write_u32(target, FLASH_FMA, 0);
544 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
545 /* Wait until erase complete */
546 do
547 {
548 target_read_u32(target, FLASH_FMC, &flash_fmc);
549 }
550 while(flash_fmc & FMC_MERASE);
551
552 /* if device has > 128k, then second erase cycle is needed */
553 if(stellaris_info->num_pages * stellaris_info->pagesize > 0x20000)
554 {
555 target_write_u32(target, FLASH_FMA, 0x20000);
556 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
557 /* Wait until erase complete */
558 do
559 {
560 target_read_u32(target, FLASH_FMC, &flash_fmc);
561 }
562 while(flash_fmc & FMC_MERASE);
563 }
564
565 return ERROR_OK;
566 }
567
568 for (banknr=first;banknr<=last;banknr++)
569 {
570 /* Address is first word in page */
571 target_write_u32(target, FLASH_FMA, banknr*stellaris_info->pagesize);
572 /* Write erase command */
573 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_ERASE);
574 /* Wait until erase complete */
575 do
576 {
577 target_read_u32(target, FLASH_FMC, &flash_fmc);
578 }
579 while(flash_fmc & FMC_ERASE);
580
581 /* Check acess violations */
582 target_read_u32(target, FLASH_CRIS, &flash_cris);
583 if(flash_cris & (AMASK))
584 {
585 WARNING("Error erasing flash page %i, flash_cris 0x%x", banknr, flash_cris);
586 target_write_u32(target, FLASH_CRIS, 0);
587 return ERROR_FLASH_OPERATION_FAILED;
588 }
589 }
590
591 return ERROR_OK;
592 }
593
594 int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last)
595 {
596 u32 fmppe, flash_fmc, flash_cris;
597 int lockregion;
598
599 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
600 target_t *target = bank->target;
601
602 if (bank->target->state != TARGET_HALTED)
603 {
604 return ERROR_TARGET_NOT_HALTED;
605 }
606
607 if ((first < 0) || (last < first) || (last >= stellaris_info->num_lockbits))
608 {
609 return ERROR_FLASH_SECTOR_INVALID;
610 }
611
612 if (stellaris_info->did1 == 0)
613 {
614 stellaris_read_part_info(bank);
615 }
616
617 if (stellaris_info->did1 == 0)
618 {
619 WARNING("Cannot identify target as an Stellaris MCU");
620 return ERROR_FLASH_OPERATION_FAILED;
621 }
622
623 /* Configure the flash controller timing */
624 stellaris_read_clock_info(bank);
625 stellaris_set_flash_mode(bank,0);
626
627 fmppe = stellaris_info->lockbits;
628 for (lockregion=first;lockregion<=last;lockregion++)
629 {
630 if (set)
631 fmppe &= ~(1<<lockregion);
632 else
633 fmppe |= (1<<lockregion);
634 }
635
636 /* Clear and disable flash programming interrupts */
637 target_write_u32(target, FLASH_CIM, 0);
638 target_write_u32(target, FLASH_MISC, PMISC|AMISC);
639
640 DEBUG("fmppe 0x%x",fmppe);
641 target_write_u32(target, SCB_BASE|FMPPE, fmppe);
642 /* Commit FMPPE */
643 target_write_u32(target, FLASH_FMA, 1);
644 /* Write commit command */
645 /* TODO safety check, sice this cannot be undone */
646 WARNING("Flash protection cannot be removed once commited, commit is NOT executed !");
647 /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
648 /* Wait until erase complete */
649 do
650 {
651 target_read_u32(target, FLASH_FMC, &flash_fmc);
652 }
653 while(flash_fmc & FMC_COMT);
654
655 /* Check acess violations */
656 target_read_u32(target, FLASH_CRIS, &flash_cris);
657 if(flash_cris & (AMASK))
658 {
659 WARNING("Error setting flash page protection, flash_cris 0x%x", flash_cris);
660 target_write_u32(target, FLASH_CRIS, 0);
661 return ERROR_FLASH_OPERATION_FAILED;
662 }
663
664 target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits);
665
666 return ERROR_OK;
667 }
668
669 u8 stellaris_write_code[] =
670 {
671 /*
672 Call with :
673 r0 = buffer address
674 r1 = destination address
675 r2 = bytecount (in) - endaddr (work)
676
677 Used registers:
678 r3 = pFLASH_CTRL_BASE
679 r4 = FLASHWRITECMD
680 r5 = #1
681 r6 = bytes written
682 r7 = temp reg
683 */
684 0x07,0x4B, /* ldr r3,pFLASH_CTRL_BASE */
685 0x08,0x4C, /* ldr r4,FLASHWRITECMD */
686 0x01,0x25, /* movs r5, 1 */
687 0x00,0x26, /* movs r6, #0 */
688 /* mainloop: */
689 0x19,0x60, /* str r1, [r3, #0] */
690 0x87,0x59, /* ldr r7, [r0, r6] */
691 0x5F,0x60, /* str r7, [r3, #4] */
692 0x9C,0x60, /* str r4, [r3, #8] */
693 /* waitloop: */
694 0x9F,0x68, /* ldr r7, [r3, #8] */
695 0x2F,0x42, /* tst r7, r5 */
696 0xFC,0xD1, /* bne waitloop */
697 0x04,0x31, /* adds r1, r1, #4 */
698 0x04,0x36, /* adds r6, r6, #4 */
699 0x96,0x42, /* cmp r6, r2 */
700 0xF4,0xD1, /* bne mainloop */
701 0x00,0xBE, /* bkpt #0 */
702 /* pFLASH_CTRL_BASE: */
703 0x00,0xD0,0x0F,0x40, /* .word 0x400FD000 */
704 /* FLASHWRITECMD: */
705 0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */
706 };
707
708 int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 wcount)
709 {
710 // stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
711 target_t *target = bank->target;
712 u32 buffer_size = 8192;
713 working_area_t *source;
714 working_area_t *write_algorithm;
715 u32 address = bank->base + offset;
716 reg_param_t reg_params[8];
717 armv7m_algorithm_t armv7m_info;
718 int retval;
719
720 DEBUG("(bank=%08X buffer=%08X offset=%08X wcount=%08X)",
721 (unsigned int)bank, (unsigned int)buffer, offset, wcount);
722
723 /* flash write code */
724 if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)
725 {
726 WARNING("no working area available, can't do block memory writes");
727 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
728 };
729
730 target_write_buffer(target, write_algorithm->address, sizeof(stellaris_write_code), stellaris_write_code);
731
732 /* memory buffer */
733 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
734 {
735 DEBUG("called target_alloc_working_area(target=%08X buffer_size=%08X source=%08X)",
736 (unsigned int)target, buffer_size, (unsigned int)source);
737 buffer_size /= 2;
738 if (buffer_size <= 256)
739 {
740 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
741 if (write_algorithm)
742 target_free_working_area(target, write_algorithm);
743
744 WARNING("no large enough working area available, can't do block memory writes");
745 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
746 }
747 };
748
749 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
750 armv7m_info.core_mode = ARMV7M_MODE_ANY;
751 armv7m_info.core_state = ARMV7M_STATE_THUMB;
752
753 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
754 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
755 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
756 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
757 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
758 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
759 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
760 init_reg_param(&reg_params[7], "r7", 32, PARAM_OUT);
761
762 while (wcount > 0)
763 {
764 u32 thisrun_count = (wcount > (buffer_size / 4)) ? (buffer_size / 4) : wcount;
765
766 target_write_buffer(target, source->address, thisrun_count * 4, buffer);
767
768 buf_set_u32(reg_params[0].value, 0, 32, source->address);
769 buf_set_u32(reg_params[1].value, 0, 32, address);
770 buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
771 WARNING("Algorithm flash write %i words to 0x%x, %i remaining",thisrun_count,address, wcount);
772 DEBUG("Algorithm flash write %i words to 0x%x, %i remaining",thisrun_count,address, wcount);
773 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)
774 {
775 ERROR("error executing stellaris flash write algorithm");
776 target_free_working_area(target, source);
777 destroy_reg_param(&reg_params[0]);
778 destroy_reg_param(&reg_params[1]);
779 destroy_reg_param(&reg_params[2]);
780 return ERROR_FLASH_OPERATION_FAILED;
781 }
782
783 buffer += thisrun_count * 4;
784 address += thisrun_count * 4;
785 wcount -= thisrun_count;
786 }
787
788
789 target_free_working_area(target, write_algorithm);
790 target_free_working_area(target, source);
791
792 destroy_reg_param(&reg_params[0]);
793 destroy_reg_param(&reg_params[1]);
794 destroy_reg_param(&reg_params[2]);
795 destroy_reg_param(&reg_params[3]);
796 destroy_reg_param(&reg_params[4]);
797 destroy_reg_param(&reg_params[5]);
798 destroy_reg_param(&reg_params[6]);
799 destroy_reg_param(&reg_params[7]);
800
801 return ERROR_OK;
802 }
803
804 int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
805 {
806 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
807 target_t *target = bank->target;
808 u32 address = offset;
809 u32 flash_cris,flash_fmc;
810 u32 retval;
811
812 DEBUG("(bank=%08X buffer=%08X offset=%08X count=%08X)",
813 (unsigned int)bank, (unsigned int)buffer, offset, count);
814
815 if (stellaris_info->did1 == 0)
816 {
817 stellaris_read_part_info(bank);
818 }
819
820 if (stellaris_info->did1 == 0)
821 {
822 WARNING("Cannot identify target as a Stellaris processor");
823 return ERROR_FLASH_OPERATION_FAILED;
824 }
825
826 if((offset & 3) || (count & 3))
827 {
828 WARNING("offset size must be word aligned");
829 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
830 }
831
832 if (offset + count > bank->size)
833 return ERROR_FLASH_DST_OUT_OF_BANK;
834
835 /* Configure the flash controller timing */
836 stellaris_read_clock_info(bank);
837 stellaris_set_flash_mode(bank,0);
838
839
840 /* Clear and disable flash programming interrupts */
841 target_write_u32(target, FLASH_CIM, 0);
842 target_write_u32(target, FLASH_MISC, PMISC|AMISC);
843
844 /* multiple words to be programmed? */
845 if (count > 0)
846 {
847 /* try using a block write */
848 if ((retval = stellaris_write_block(bank, buffer, offset, count/4)) != ERROR_OK)
849 {
850 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
851 {
852 /* if block write failed (no sufficient working area),
853 * we use normal (slow) single dword accesses */
854 WARNING("couldn't use block writes, falling back to single memory accesses");
855 }
856 else if (retval == ERROR_FLASH_OPERATION_FAILED)
857 {
858 /* if an error occured, we examine the reason, and quit */
859 target_read_u32(target, FLASH_CRIS, &flash_cris);
860
861 ERROR("flash writing failed with CRIS: 0x%x", flash_cris);
862 return ERROR_FLASH_OPERATION_FAILED;
863 }
864 }
865 else
866 {
867 buffer += count * 4;
868 address += count * 4;
869 count = 0;
870 }
871 }
872
873
874
875 while(count>0)
876 {
877 if (!(address&0xff)) DEBUG("0x%x",address);
878 /* Program one word */
879 target_write_u32(target, FLASH_FMA, address);
880 target_write_buffer(target, FLASH_FMD, 4, buffer);
881 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
882 //DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE);
883 /* Wait until write complete */
884 do
885 {
886 target_read_u32(target, FLASH_FMC, &flash_fmc);
887 }
888 while(flash_fmc & FMC_WRITE);
889 buffer += 4;
890 address += 4;
891 count -= 4;
892 }
893 /* Check acess violations */
894 target_read_u32(target, FLASH_CRIS, &flash_cris);
895 if(flash_cris & (AMASK))
896 {
897 DEBUG("flash_cris 0x%x", flash_cris);
898 return ERROR_FLASH_OPERATION_FAILED;
899 }
900 return ERROR_OK;
901 }
902
903
904 int stellaris_probe(struct flash_bank_s *bank)
905 {
906 /* we can't probe on an stellaris
907 * if this is an stellaris, it has the configured flash
908 */
909 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
910
911 stellaris_info->probed = 0;
912
913 if (stellaris_info->did1 == 0)
914 {
915 stellaris_read_part_info(bank);
916 }
917
918 if (stellaris_info->did1 == 0)
919 {
920 WARNING("Cannot identify target as a LMI Stellaris");
921 return ERROR_FLASH_OPERATION_FAILED;
922 }
923
924 stellaris_info->probed = 1;
925
926 return ERROR_OK;
927 }
928
929 int stellaris_auto_probe(struct flash_bank_s *bank)
930 {
931 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
932 if (stellaris_info->probed)
933 return ERROR_OK;
934 return stellaris_probe(bank);
935 }
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