target_t -> struct target
[openocd.git] / src / flash / s3c2440_nand.c
1 /***************************************************************************
2 * Copyright (C) 2007, 2008 by Ben Dooks *
3 * ben@fluff.org *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 /*
22 * S3C2440 OpenOCD NAND Flash controller support.
23 *
24 * Many thanks to Simtec Electronics for sponsoring this work.
25 */
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "s3c24xx_nand.h"
32
33
34 NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
35 {
36 struct s3c24xx_nand_controller *info;
37 CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
38
39 /* fill in the address fields for the core device */
40 info->cmd = S3C2440_NFCMD;
41 info->addr = S3C2440_NFADDR;
42 info->data = S3C2440_NFDATA;
43 info->nfstat = S3C2440_NFSTAT;
44
45 return ERROR_OK;
46 }
47
48 static int s3c2440_init(struct nand_device_s *nand)
49 {
50 struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
51 struct target *target = s3c24xx_info->target;
52
53 target_write_u32(target, S3C2410_NFCONF,
54 S3C2440_NFCONF_TACLS(3) |
55 S3C2440_NFCONF_TWRPH0(7) |
56 S3C2440_NFCONF_TWRPH1(7));
57
58 target_write_u32(target, S3C2440_NFCONT,
59 S3C2440_NFCONT_INITECC | S3C2440_NFCONT_ENABLE);
60
61 return ERROR_OK;
62 }
63
64 int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
65 {
66 struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
67 struct target *target = s3c24xx_info->target;
68 uint8_t status;
69
70 if (target->state != TARGET_HALTED) {
71 LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
72 return ERROR_NAND_OPERATION_FAILED;
73 }
74
75 do {
76 target_read_u8(target, s3c24xx_info->nfstat, &status);
77
78 if (status & S3C2440_NFSTAT_READY)
79 return 1;
80
81 alive_sleep(1);
82 } while (timeout-- > 0);
83
84
85 return 0;
86 }
87
88 /* use the fact we can read/write 4 bytes in one go via a single 32bit op */
89
90 int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
91 {
92 struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
93 struct target *target = s3c24xx_info->target;
94 uint32_t nfdata = s3c24xx_info->data;
95 uint32_t tmp;
96
97 LOG_INFO("%s: reading data: %p, %p, %d\n", __func__, nand, data, data_size);
98
99 if (target->state != TARGET_HALTED) {
100 LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
101 return ERROR_NAND_OPERATION_FAILED;
102 }
103
104 while (data_size >= 4) {
105 target_read_u32(target, nfdata, &tmp);
106
107 data[0] = tmp;
108 data[1] = tmp >> 8;
109 data[2] = tmp >> 16;
110 data[3] = tmp >> 24;
111
112 data_size -= 4;
113 data += 4;
114 }
115
116 while (data_size > 0) {
117 target_read_u8(target, nfdata, data);
118
119 data_size -= 1;
120 data += 1;
121 }
122
123 return ERROR_OK;
124 }
125
126 int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
127 {
128 struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
129 struct target *target = s3c24xx_info->target;
130 uint32_t nfdata = s3c24xx_info->data;
131 uint32_t tmp;
132
133 if (target->state != TARGET_HALTED) {
134 LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
135 return ERROR_NAND_OPERATION_FAILED;
136 }
137
138 while (data_size >= 4) {
139 tmp = le_to_h_u32(data);
140 target_write_u32(target, nfdata, tmp);
141
142 data_size -= 4;
143 data += 4;
144 }
145
146 while (data_size > 0) {
147 target_write_u8(target, nfdata, *data);
148
149 data_size -= 1;
150 data += 1;
151 }
152
153 return ERROR_OK;
154 }
155
156 struct nand_flash_controller s3c2440_nand_controller = {
157 .name = "s3c2440",
158 .nand_device_command = &s3c2440_nand_device_command,
159 .register_commands = &s3c24xx_register_commands,
160 .init = &s3c2440_init,
161 .reset = &s3c24xx_reset,
162 .command = &s3c24xx_command,
163 .address = &s3c24xx_address,
164 .write_data = &s3c24xx_write_data,
165 .read_data = &s3c24xx_read_data,
166 .write_page = s3c24xx_write_page,
167 .read_page = s3c24xx_read_page,
168 .write_block_data = &s3c2440_write_block_data,
169 .read_block_data = &s3c2440_read_block_data,
170 .controller_ready = &s3c24xx_controller_ready,
171 .nand_ready = &s3c2440_nand_ready,
172 };