b761951455ad8fe9e1918e3503aedfcbf9dae385
[openocd.git] / src / flash / nor / xmc4xxx.c
1 /**************************************************************************
2 * Copyright (C) 2015 Jeff Ciesielski <jeffciesielski@gmail.com> *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
17
18 #ifdef HAVE_CONFIG_H
19 #include "config.h"
20 #endif
21
22 #include "imp.h"
23 #include <helper/binarybuffer.h>
24 #include <target/algorithm.h>
25 #include <target/armv7m.h>
26
27 /* Maximum number of sectors */
28 #define MAX_XMC_SECTORS 12
29
30 /* System control unit registers */
31 #define SCU_REG_BASE 0x50004000
32
33 #define SCU_ID_CHIP 0x04
34
35 /* Base of the non-cached flash memory */
36 #define PFLASH_BASE 0x0C000000
37
38 /* User configuration block offsets */
39 #define UCB0_BASE 0x00000000
40 #define UCB1_BASE 0x00000400
41 #define UCB2_BASE 0x00000800
42
43 /* Flash register base */
44 #define FLASH_REG_BASE 0x58000000
45
46 /* PMU ID Registers */
47 #define FLASH_REG_PMU_ID (FLASH_REG_BASE | 0x0508)
48
49 /* PMU Fields */
50 #define PMU_MOD_REV_MASK 0xFF
51 #define PMU_MOD_TYPE_MASK 0xFF00
52 #define PMU_MOD_NO_MASK 0xFFFF0000
53
54 /* Prefetch Config */
55 #define FLASH_REG_PREF_PCON (FLASH_REG_BASE | 0x4000)
56
57 /* Prefetch Fields */
58 #define PCON_IBYP (1 << 0)
59 #define PCON_IINV (1 << 1)
60
61 /* Flash ID Register */
62 #define FLASH_REG_FLASH0_ID (FLASH_REG_BASE | 0x2008)
63
64 /* Flash Status Register */
65 #define FLASH_REG_FLASH0_FSR (FLASH_REG_BASE | 0x2010)
66
67 #define FSR_PBUSY (0)
68 #define FSR_FABUSY (1)
69 #define FSR_PROG (4)
70 #define FSR_ERASE (5)
71 #define FSR_PFPAGE (6)
72 #define FSR_PFOPER (8)
73 #define FSR_SQER (10)
74 #define FSR_PROER (11)
75 #define FSR_PFSBER (12)
76 #define FSR_PFDBER (14)
77 #define FSR_PROIN (16)
78 #define FSR_RPROIN (18)
79 #define FSR_RPRODIS (19)
80 #define FSR_WPROIN0 (21)
81 #define FSR_WPROIN1 (22)
82 #define FSR_WPROIN2 (23)
83 #define FSR_WPRODIS0 (25)
84 #define FSR_WPRODIS1 (26)
85 #define FSR_SLM (28)
86 #define FSR_VER (31)
87
88 #define FSR_PBUSY_MASK (0x01 << FSR_PBUSY)
89 #define FSR_FABUSY_MASK (0x01 << FSR_FABUSY)
90 #define FSR_PROG_MASK (0x01 << FSR_PROG)
91 #define FSR_ERASE_MASK (0x01 << FSR_ERASE)
92 #define FSR_PFPAGE_MASK (0x01 << FSR_PFPAGE)
93 #define FSR_PFOPER_MASK (0x01 << FSR_PFOPER)
94 #define FSR_SQER_MASK (0x01 << FSR_SQER)
95 #define FSR_PROER_MASK (0x01 << FSR_PROER)
96 #define FSR_PFSBER_MASK (0x01 << FSR_PFSBER)
97 #define FSR_PFDBER_MASK (0x01 << FSR_PFDBER)
98 #define FSR_PROIN_MASK (0x01 << FSR_PROIN)
99 #define FSR_RPROIN_MASK (0x01 << FSR_RPROIN)
100 #define FSR_RPRODIS_MASK (0x01 << FSR_RPRODIS)
101 #define FSR_WPROIN0_MASK (0x01 << FSR_WPROIN0)
102 #define FSR_WPROIN1_MASK (0x01 << FSR_WPROIN1)
103 #define FSR_WPROIN2_MASK (0x01 << FSR_WPROIN2)
104 #define FSR_WPRODIS0_MASK (0x01 << FSR_WPRODIS0)
105 #define FSR_WPRODIS1_MASK (0x01 << FSR_WPRODIS1)
106 #define FSR_SLM_MASK (0x01 << FSR_SLM)
107 #define FSR_VER_MASK (0x01 << FSR_VER)
108
109 /* Flash Config Register */
110 #define FLASH_REG_FLASH0_FCON (FLASH_REG_BASE | 0x2014)
111
112 #define FCON_WSPFLASH (0)
113 #define FCON_WSECPF (4)
114 #define FCON_IDLE (13)
115 #define FCON_ESLDIS (14)
116 #define FCON_SLEEP (15)
117 #define FCON_RPA (16)
118 #define FCON_DCF (17)
119 #define FCON_DDF (18)
120 #define FCON_VOPERM (24)
121 #define FCON_SQERM (25)
122 #define FCON_PROERM (26)
123 #define FCON_PFSBERM (27)
124 #define FCON_PFDBERM (29)
125 #define FCON_EOBM (31)
126
127 #define FCON_WSPFLASH_MASK (0x0f << FCON_WSPFLASH)
128 #define FCON_WSECPF_MASK (0x01 << FCON_WSECPF)
129 #define FCON_IDLE_MASK (0x01 << FCON_IDLE)
130 #define FCON_ESLDIS_MASK (0x01 << FCON_ESLDIS)
131 #define FCON_SLEEP_MASK (0x01 << FCON_SLEEP)
132 #define FCON_RPA_MASK (0x01 << FCON_RPA)
133 #define FCON_DCF_MASK (0x01 << FCON_DCF)
134 #define FCON_DDF_MASK (0x01 << FCON_DDF)
135 #define FCON_VOPERM_MASK (0x01 << FCON_VOPERM)
136 #define FCON_SQERM_MASK (0x01 << FCON_SQERM)
137 #define FCON_PROERM_MASK (0x01 << FCON_PROERM)
138 #define FCON_PFSBERM_MASK (0x01 << FCON_PFSBERM)
139 #define FCON_PFDBERM_MASK (0x01 << FCON_PFDBERM)
140 #define FCON_EOBM_MASK (0x01 << FCON_EOBM)
141
142 /* Flash Margin Control Register */
143 #define FLASH_REG_FLASH0_MARP (FLASH_REG_BASE | 0x2018)
144
145 #define MARP_MARGIN (0)
146 #define MARP_TRAPDIS (15)
147
148 #define MARP_MARGIN_MASK (0x0f << MARP_MARGIN)
149 #define MARP_TRAPDIS_MASK (0x01 << MARP_TRAPDIS)
150
151 /* Flash Protection Registers */
152 #define FLASH_REG_FLASH0_PROCON0 (FLASH_REG_BASE | 0x2020)
153 #define FLASH_REG_FLASH0_PROCON1 (FLASH_REG_BASE | 0x2024)
154 #define FLASH_REG_FLASH0_PROCON2 (FLASH_REG_BASE | 0x2028)
155
156 #define PROCON_S0L (0)
157 #define PROCON_S1L (1)
158 #define PROCON_S2L (2)
159 #define PROCON_S3L (3)
160 #define PROCON_S4L (4)
161 #define PROCON_S5L (5)
162 #define PROCON_S6L (6)
163 #define PROCON_S7L (7)
164 #define PROCON_S8L (8)
165 #define PROCON_S9L (9)
166 #define PROCON_S10_S11L (10)
167 #define PROCON_RPRO (15)
168
169 #define PROCON_S0L_MASK (0x01 << PROCON_S0L)
170 #define PROCON_S1L_MASK (0x01 << PROCON_S1L)
171 #define PROCON_S2L_MASK (0x01 << PROCON_S2L)
172 #define PROCON_S3L_MASK (0x01 << PROCON_S3L)
173 #define PROCON_S4L_MASK (0x01 << PROCON_S4L)
174 #define PROCON_S5L_MASK (0x01 << PROCON_S5L)
175 #define PROCON_S6L_MASK (0x01 << PROCON_S6L)
176 #define PROCON_S7L_MASK (0x01 << PROCON_S7L)
177 #define PROCON_S8L_MASK (0x01 << PROCON_S8L)
178 #define PROCON_S9L_MASK (0x01 << PROCON_S9L)
179 #define PROCON_S10_S11L_MASK (0x01 << PROCON_S10_S11L)
180 #define PROCON_RPRO_MASK (0x01 << PROCON_RPRO)
181
182 #define FLASH_PROTECT_CONFIRMATION_CODE 0x8AFE15C3
183
184 /* Flash controller configuration values */
185 #define FLASH_ID_XMC4500 0xA2
186 #define FLASH_ID_XMC4700_4800 0x92
187 #define FLASH_ID_XMC4100_4200 0x9C
188 #define FLASH_ID_XMC4400 0x9F
189
190 /* Timeouts */
191 #define FLASH_OP_TIMEOUT 5000
192
193 /* Flash commands (write/erase/protect) are performed using special
194 * command sequences that are written to magic addresses in the flash controller */
195 /* Command sequence addresses. See reference manual, section 8: Flash Command Sequences */
196 #define FLASH_CMD_ERASE_1 0x0C005554
197 #define FLASH_CMD_ERASE_2 0x0C00AAA8
198 #define FLASH_CMD_ERASE_3 FLASH_CMD_ERASE_1
199 #define FLASH_CMD_ERASE_4 FLASH_CMD_ERASE_1
200 #define FLASH_CMD_ERASE_5 FLASH_CMD_ERASE_2
201 /* ERASE_6 is the sector base address */
202
203 #define FLASH_CMD_CLEAR_STATUS FLASH_CMD_ERASE_1
204
205 #define FLASH_CMD_ENTER_PAGEMODE FLASH_CMD_ERASE_1
206
207 #define FLASH_CMD_LOAD_PAGE_1 0x0C0055F0
208 #define FLASH_CMD_LOAD_PAGE_2 0x0C0055F4
209
210 #define FLASH_CMD_WRITE_PAGE_1 FLASH_CMD_ERASE_1
211 #define FLASH_CMD_WRITE_PAGE_2 FLASH_CMD_ERASE_2
212 #define FLASH_CMD_WRITE_PAGE_3 FLASH_CMD_ERASE_1
213 /* WRITE_PAGE_4 is the page base address */
214
215 #define FLASH_CMD_TEMP_UNPROT_1 FLASH_CMD_ERASE_1
216 #define FLASH_CMD_TEMP_UNPROT_2 FLASH_CMD_ERASE_2
217 #define FLASH_CMD_TEMP_UNPROT_3 0x0C00553C
218 #define FLASH_CMD_TEMP_UNPROT_4 FLASH_CMD_ERASE_2
219 #define FLASH_CMD_TEMP_UNPROT_5 FLASH_CMD_ERASE_2
220 #define FLASH_CMD_TEMP_UNPROT_6 0x0C005558
221
222 struct xmc4xxx_flash_bank {
223 bool probed;
224
225 /* We need the flash controller ID to choose the sector layout */
226 uint32_t fcon_id;
227
228 /* Passwords used for protection operations */
229 uint32_t pw1;
230 uint32_t pw2;
231 bool pw_set;
232
233 /* Protection flags */
234 bool read_protected;
235
236 bool write_prot_otp[MAX_XMC_SECTORS];
237 };
238
239 struct xmc4xxx_command_seq {
240 uint32_t address;
241 uint32_t magic;
242 };
243
244 /* Sector capacities. See section 8 of xmc4x00_rm */
245 static const unsigned int sector_capacity_8[8] = {
246 16, 16, 16, 16, 16, 16, 16, 128
247 };
248
249 static const unsigned int sector_capacity_9[9] = {
250 16, 16, 16, 16, 16, 16, 16, 128, 256
251 };
252
253 static const unsigned int sector_capacity_12[12] = {
254 16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256
255 };
256
257 static const unsigned int sector_capacity_16[16] = {
258 16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256, 256, 256, 256, 256
259 };
260
261 static int xmc4xxx_write_command_sequence(struct flash_bank *bank,
262 struct xmc4xxx_command_seq *seq,
263 int seq_len)
264 {
265 int res = ERROR_OK;
266
267 for (int i = 0; i < seq_len; i++) {
268 res = target_write_u32(bank->target, seq[i].address,
269 seq[i].magic);
270 if (res != ERROR_OK)
271 return res;
272 }
273
274 return ERROR_OK;
275 }
276
277 static int xmc4xxx_load_bank_layout(struct flash_bank *bank)
278 {
279 const unsigned int *capacity = NULL;
280
281 /* At this point, we know which flash controller ID we're
282 * talking to and simply need to fill out the bank structure accordingly */
283 LOG_DEBUG("%d sectors", bank->num_sectors);
284
285 switch (bank->num_sectors) {
286 case 8:
287 capacity = sector_capacity_8;
288 break;
289 case 9:
290 capacity = sector_capacity_9;
291 break;
292 case 12:
293 capacity = sector_capacity_12;
294 break;
295 case 16:
296 capacity = sector_capacity_16;
297 break;
298 default:
299 LOG_ERROR("Unexpected number of sectors, %d\n",
300 bank->num_sectors);
301 return ERROR_FAIL;
302 }
303
304 /* This looks like a bank that we understand, now we know the
305 * corresponding sector capacities and we can add those up into the
306 * bank size. */
307 uint32_t total_offset = 0;
308 bank->sectors = calloc(bank->num_sectors,
309 sizeof(struct flash_sector));
310 for (int i = 0; i < bank->num_sectors; i++) {
311 bank->sectors[i].size = capacity[i] * 1024;
312 bank->sectors[i].offset = total_offset;
313 bank->sectors[i].is_erased = -1;
314 bank->sectors[i].is_protected = -1;
315
316 bank->size += bank->sectors[i].size;
317 LOG_DEBUG("\t%d: %uk", i, capacity[i]);
318 total_offset += bank->sectors[i].size;
319 }
320
321 /* This part doesn't follow the typical standard of 0xff
322 * being the erased value.*/
323 bank->default_padded_value = bank->erased_value = 0x00;
324
325 return ERROR_OK;
326 }
327
328 static int xmc4xxx_probe(struct flash_bank *bank)
329 {
330 int res;
331 uint32_t devid, config;
332 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
333 uint8_t flash_id;
334
335 if (fb->probed)
336 return ERROR_OK;
337
338 /* It's not possible for the DAP to access the OTP locations needed for
339 * probing the part info and Flash geometry so we require that the target
340 * be halted before proceeding. */
341 if (bank->target->state != TARGET_HALTED) {
342 LOG_WARNING("Cannot communicate... target not halted.");
343 return ERROR_TARGET_NOT_HALTED;
344 }
345
346 /* The SCU registers contain the ID of the chip */
347 res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &devid);
348 if (res != ERROR_OK) {
349 LOG_ERROR("Cannot read device identification register.");
350 return res;
351 }
352
353 /* Make sure this is a XMC4000 family device */
354 if ((devid & 0xF0000) != 0x40000 && devid != 0) {
355 LOG_ERROR("Platform ID doesn't match XMC4xxx: 0x%08" PRIx32, devid);
356 return ERROR_FAIL;
357 }
358
359 LOG_DEBUG("Found XMC4xxx with devid: 0x%08" PRIx32, devid);
360
361 /* Now sanity-check the Flash controller itself. */
362 res = target_read_u32(bank->target, FLASH_REG_FLASH0_ID,
363 &config);
364 if (res != ERROR_OK) {
365 LOG_ERROR("Cannot read Flash bank configuration.");
366 return res;
367 }
368 flash_id = (config & 0xff0000) >> 16;
369
370 /* The Flash configuration register is our only means of
371 * determining the sector layout. We need to make sure that
372 * we understand the type of controller we're dealing with */
373 switch (flash_id) {
374 case FLASH_ID_XMC4100_4200:
375 bank->num_sectors = 8;
376 LOG_DEBUG("XMC4xxx: XMC4100/4200 detected.");
377 break;
378 case FLASH_ID_XMC4400:
379 bank->num_sectors = 9;
380 LOG_DEBUG("XMC4xxx: XMC4400 detected.");
381 break;
382 case FLASH_ID_XMC4500:
383 bank->num_sectors = 12;
384 LOG_DEBUG("XMC4xxx: XMC4500 detected.");
385 break;
386 case FLASH_ID_XMC4700_4800:
387 bank->num_sectors = 16;
388 LOG_DEBUG("XMC4xxx: XMC4700/4800 detected.");
389 break;
390 default:
391 LOG_ERROR("XMC4xxx: Unexpected flash ID. got %02" PRIx8,
392 flash_id);
393 return ERROR_FAIL;
394 }
395
396 /* Retrieve information about the particular bank we're probing and fill in
397 * the bank structure accordingly. */
398 res = xmc4xxx_load_bank_layout(bank);
399 if (res == ERROR_OK) {
400 /* We're done */
401 fb->probed = true;
402 } else {
403 LOG_ERROR("Unable to load bank information.");
404 return ERROR_FAIL;
405 }
406
407 return ERROR_OK;
408 }
409
410 static int xmc4xxx_get_sector_start_addr(struct flash_bank *bank,
411 int sector, uint32_t *ret_addr)
412 {
413 /* Make sure we understand this sector */
414 if (sector > bank->num_sectors)
415 return ERROR_FAIL;
416
417 *ret_addr = bank->base + bank->sectors[sector].offset;
418
419 return ERROR_OK;
420
421 }
422
423 static int xmc4xxx_clear_flash_status(struct flash_bank *bank)
424 {
425 int res;
426 /* TODO: Do we need to check for sequence error? */
427 LOG_INFO("Clearing flash status");
428 res = target_write_u32(bank->target, FLASH_CMD_CLEAR_STATUS,
429 0xF5);
430 if (res != ERROR_OK) {
431 LOG_ERROR("Unable to write erase command sequence");
432 return res;
433 }
434
435 return ERROR_OK;
436 }
437
438 static int xmc4xxx_get_flash_status(struct flash_bank *bank, uint32_t *status)
439 {
440 int res;
441
442 res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, status);
443
444 if (res != ERROR_OK)
445 LOG_ERROR("Cannot read flash status register.");
446
447 return res;
448 }
449
450 static int xmc4xxx_wait_status_busy(struct flash_bank *bank, int timeout)
451 {
452 int res;
453 uint32_t status;
454
455 res = xmc4xxx_get_flash_status(bank, &status);
456 if (res != ERROR_OK)
457 return res;
458
459 /* While the flash controller is busy, wait */
460 while (status & FSR_PBUSY_MASK) {
461 res = xmc4xxx_get_flash_status(bank, &status);
462 if (res != ERROR_OK)
463 return res;
464
465 if (timeout-- <= 0) {
466 LOG_ERROR("Timed out waiting for flash");
467 return ERROR_FAIL;
468 }
469 alive_sleep(1);
470 keep_alive();
471 }
472
473 if (status & FSR_PROER_MASK) {
474 LOG_ERROR("XMC4xxx flash protected");
475 res = ERROR_FAIL;
476 }
477
478 return res;
479 }
480
481 static int xmc4xxx_erase_sector(struct flash_bank *bank, uint32_t address,
482 bool user_config)
483 {
484 int res;
485 uint32_t status;
486
487 /* See reference manual table 8.4: Command Sequences for Flash Control */
488 struct xmc4xxx_command_seq erase_cmd_seq[6] = {
489 {FLASH_CMD_ERASE_1, 0xAA},
490 {FLASH_CMD_ERASE_2, 0x55},
491 {FLASH_CMD_ERASE_3, 0x80},
492 {FLASH_CMD_ERASE_4, 0xAA},
493 {FLASH_CMD_ERASE_5, 0x55},
494 {0xFF, 0xFF} /* Needs filled in */
495 };
496
497 /* We need to fill in the base address of the sector we'll be
498 * erasing, as well as the magic code that determines whether
499 * this is a standard flash sector or a user configuration block */
500
501 erase_cmd_seq[5].address = address;
502 if (user_config) {
503 /* Removing flash protection requires the addition of
504 * the base address */
505 erase_cmd_seq[5].address += bank->base;
506 erase_cmd_seq[5].magic = 0xC0;
507 } else {
508 erase_cmd_seq[5].magic = 0x30;
509 }
510
511 res = xmc4xxx_write_command_sequence(bank, erase_cmd_seq,
512 ARRAY_SIZE(erase_cmd_seq));
513 if (res != ERROR_OK)
514 return res;
515
516 /* Read the flash status register */
517 res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, &status);
518 if (res != ERROR_OK) {
519 LOG_ERROR("Cannot read flash status register.");
520 return res;
521 }
522
523 /* Check for a sequence error */
524 if (status & FSR_SQER_MASK) {
525 LOG_ERROR("Error with flash erase sequence");
526 return ERROR_FAIL;
527 }
528
529 /* Make sure a flash erase was triggered */
530 if (!(status & FSR_ERASE_MASK)) {
531 LOG_ERROR("Flash failed to erase");
532 return ERROR_FAIL;
533 }
534
535 /* Now we must wait for the erase operation to end */
536 res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
537
538 return res;
539 }
540
541 static int xmc4xxx_erase(struct flash_bank *bank, int first, int last)
542 {
543 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
544 int res;
545
546 if (bank->target->state != TARGET_HALTED) {
547 LOG_ERROR("Unable to erase, target is not halted");
548 return ERROR_TARGET_NOT_HALTED;
549 }
550
551 if (!fb->probed) {
552 res = xmc4xxx_probe(bank);
553 if (res != ERROR_OK)
554 return res;
555 }
556
557 uint32_t tmp_addr;
558 /* Loop through the sectors and erase each one */
559 for (int i = first; i <= last; i++) {
560 res = xmc4xxx_get_sector_start_addr(bank, i, &tmp_addr);
561 if (res != ERROR_OK) {
562 LOG_ERROR("Invalid sector %d", i);
563 return res;
564 }
565
566 LOG_DEBUG("Erasing sector %d @ 0x%08"PRIx32, i, tmp_addr);
567
568 res = xmc4xxx_erase_sector(bank, tmp_addr, false);
569 if (res != ERROR_OK) {
570 LOG_ERROR("Unable to write erase command sequence");
571 goto clear_status_and_exit;
572 }
573
574 /* Now we must wait for the erase operation to end */
575 res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
576
577 if (res != ERROR_OK)
578 goto clear_status_and_exit;
579
580 bank->sectors[i].is_erased = 1;
581 }
582
583 clear_status_and_exit:
584 res = xmc4xxx_clear_flash_status(bank);
585 return res;
586
587 }
588
589 static int xmc4xxx_enter_page_mode(struct flash_bank *bank)
590 {
591 int res;
592 uint32_t status;
593
594 res = target_write_u32(bank->target, FLASH_CMD_ENTER_PAGEMODE, 0x50);
595 if (res != ERROR_OK) {
596 LOG_ERROR("Unable to write enter page mode command");
597 return ERROR_FAIL;
598 }
599
600 res = xmc4xxx_get_flash_status(bank, &status);
601
602 if (res != ERROR_OK)
603 return res;
604
605 /* Make sure we're in page mode */
606 if (!(status & FSR_PFPAGE_MASK)) {
607 LOG_ERROR("Unable to enter page mode");
608 return ERROR_FAIL;
609 }
610
611 /* Make sure we didn't encounter a sequence error */
612 if (status & FSR_SQER_MASK) {
613 LOG_ERROR("Sequence error while entering page mode");
614 return ERROR_FAIL;
615 }
616
617 return res;
618 }
619
620 static int xmc4xxx_write_page(struct flash_bank *bank, const uint8_t *pg_buf,
621 uint32_t offset, bool user_config)
622 {
623 int res;
624 uint32_t status;
625
626 /* Base of the flash write command */
627 struct xmc4xxx_command_seq write_cmd_seq[4] = {
628 {FLASH_CMD_WRITE_PAGE_1, 0xAA},
629 {FLASH_CMD_WRITE_PAGE_2, 0x55},
630 {FLASH_CMD_WRITE_PAGE_3, 0xFF}, /* Needs filled in */
631 {0xFF, 0xFF} /* Needs filled in */
632 };
633
634 /* The command sequence differs depending on whether this is
635 * being written to standard flash or the user configuration
636 * area */
637 if (user_config)
638 write_cmd_seq[2].magic = 0xC0;
639 else
640 write_cmd_seq[2].magic = 0xA0;
641
642 /* Finally, we need to add the address that this page will be
643 * written to */
644 write_cmd_seq[3].address = bank->base + offset;
645 write_cmd_seq[3].magic = 0xAA;
646
647
648 /* Flash pages are written 256 bytes at a time. For each 256
649 * byte chunk, we need to:
650 * 1. Enter page mode. This activates the flash write buffer
651 * 2. Load the page buffer with data (2x 32 bit words at a time)
652 * 3. Burn the page buffer into its intended location
653 * If the starting offset is not on a 256 byte boundary, we
654 * will need to pad the beginning of the write buffer
655 * accordingly. Likewise, if the last page does not fill the
656 * buffer, we should pad it to avoid leftover data from being
657 * written to flash
658 */
659 res = xmc4xxx_enter_page_mode(bank);
660 if (res != ERROR_OK)
661 return res;
662
663 /* Copy the data into the page buffer*/
664 for (int i = 0; i < 256; i += 8) {
665 uint32_t w_lo = target_buffer_get_u32(bank->target, &pg_buf[i]);
666 uint32_t w_hi = target_buffer_get_u32(bank->target, &pg_buf[i + 4]);
667 LOG_DEBUG("WLO: %08"PRIx32, w_lo);
668 LOG_DEBUG("WHI: %08"PRIx32, w_hi);
669
670 /* Data is loaded 2x 32 bit words at a time */
671 res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_1, w_lo);
672 if (res != ERROR_OK)
673 return res;
674
675 res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_2, w_hi);
676 if (res != ERROR_OK)
677 return res;
678
679 /* Check for an error */
680 res = xmc4xxx_get_flash_status(bank, &status);
681 if (res != ERROR_OK)
682 return res;
683
684 if (status & FSR_SQER_MASK) {
685 LOG_ERROR("Error loading page buffer");
686 return ERROR_FAIL;
687 }
688 }
689
690 /* The page buffer is now full, time to commit it to flash */
691
692 res = xmc4xxx_write_command_sequence(bank, write_cmd_seq, ARRAY_SIZE(write_cmd_seq));
693 if (res != ERROR_OK) {
694 LOG_ERROR("Unable to enter write command sequence");
695 return res;
696 }
697
698 /* Read the flash status register */
699 res = xmc4xxx_get_flash_status(bank, &status);
700 if (res != ERROR_OK)
701 return res;
702
703 /* Check for a sequence error */
704 if (status & FSR_SQER_MASK) {
705 LOG_ERROR("Error with flash write sequence");
706 return ERROR_FAIL;
707 }
708
709 /* Make sure a flash write was triggered */
710 if (!(status & FSR_PROG_MASK)) {
711 LOG_ERROR("Failed to write flash page");
712 return ERROR_FAIL;
713 }
714
715 /* Wait for the write operation to end */
716 res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
717 if (res != ERROR_OK)
718 return res;
719
720 /* TODO: Verify that page was written without error */
721 return res;
722 }
723
724 static int xmc4xxx_write(struct flash_bank *bank, const uint8_t *buffer,
725 uint32_t offset, uint32_t count)
726 {
727 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
728 int res = ERROR_OK;
729
730 if (bank->target->state != TARGET_HALTED) {
731 LOG_ERROR("Unable to erase, target is not halted");
732 return ERROR_TARGET_NOT_HALTED;
733 }
734
735 if (!fb->probed) {
736 res = xmc4xxx_probe(bank);
737 if (res != ERROR_OK)
738 return res;
739 }
740
741 /* Make sure we won't run off the end of the flash bank */
742 if ((offset + count) > (bank->size)) {
743 LOG_ERROR("Attempting to write past the end of flash");
744 return ERROR_FAIL;
745 }
746
747
748 /* Attempt to write the passed in buffer to flash */
749 /* Pages are written 256 bytes at a time, we need to handle
750 * scenarios where padding is required at the beginning and
751 * end of a page */
752 while (count) {
753 /* page working area */
754 uint8_t tmp_buf[256] = {0};
755
756 /* Amount of data we'll be writing to this page */
757 int remaining;
758 int end_pad;
759
760 remaining = MIN(count, sizeof(tmp_buf));
761 end_pad = sizeof(tmp_buf) - remaining;
762
763 /* Make sure we're starting on a page boundary */
764 int start_pad = offset % 256;
765 if (start_pad) {
766 LOG_INFO("Write does not start on a 256 byte boundary. "
767 "Padding by %d bytes", start_pad);
768 memset(tmp_buf, 0xff, start_pad);
769 /* Subtract the amount of start offset from
770 * the amount of data we'll need to write */
771 remaining -= start_pad;
772 }
773
774 /* Remove the amount we'll be writing from the total count */
775 count -= remaining;
776
777 /* Now copy in the remaining data */
778 memcpy(&tmp_buf[start_pad], buffer, remaining);
779
780 if (end_pad) {
781 LOG_INFO("Padding end of page @%08"PRIx32" by %d bytes",
782 bank->base + offset, end_pad);
783 memset(&tmp_buf[256 - end_pad], 0xff, end_pad);
784 }
785
786 /* Now commit this page to flash, if there was start
787 * padding, we should subtract that from the target offset */
788 res = xmc4xxx_write_page(bank, tmp_buf, (offset - start_pad), false);
789 if (res != ERROR_OK) {
790 LOG_ERROR("Unable to write flash page");
791 goto abort_write_and_exit;
792 }
793
794 /* Advance the buffer pointer */
795 buffer += remaining;
796
797 /* Advance the offset */
798 offset += remaining;
799 }
800
801 abort_write_and_exit:
802 xmc4xxx_clear_flash_status(bank);
803 return res;
804
805 }
806
807 static int xmc4xxx_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
808 {
809 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
810 uint32_t scu_idcode;
811
812 if (bank->target->state != TARGET_HALTED) {
813 LOG_WARNING("Cannot communicate... target not halted.");
814 return ERROR_TARGET_NOT_HALTED;
815 }
816
817 /* The SCU registers contain the ID of the chip */
818 int res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &scu_idcode);
819 if (res != ERROR_OK) {
820 LOG_ERROR("Cannot read device identification register.");
821 return res;
822 }
823
824 uint16_t dev_id = (scu_idcode & 0xfff0) >> 4;
825 uint16_t rev_id = scu_idcode & 0xf;
826 const char *dev_str;
827 const char *rev_str = NULL;
828
829 switch (dev_id) {
830 case 0x100:
831 dev_str = "XMC4100";
832
833 switch (rev_id) {
834 case 0x1:
835 rev_str = "AA";
836 break;
837 case 0x2:
838 rev_str = "AB";
839 break;
840 }
841 break;
842 case 0x200:
843 dev_str = "XMC4200";
844
845 switch (rev_id) {
846 case 0x1:
847 rev_str = "AA";
848 break;
849 case 0x2:
850 rev_str = "AB";
851 break;
852 }
853 break;
854 case 0x400:
855 dev_str = "XMC4400";
856
857 switch (rev_id) {
858 case 0x1:
859 rev_str = "AA";
860 break;
861 case 0x2:
862 rev_str = "AB";
863 break;
864 }
865 break;
866 case 0:
867 /* XMC4500 EES AA13 with date codes before GE212
868 * had zero SCU_IDCHIP
869 */
870 dev_str = "XMC4500 EES";
871 rev_str = "AA13";
872 break;
873 case 0x500:
874 dev_str = "XMC4500";
875
876 switch (rev_id) {
877 case 0x2:
878 rev_str = "AA";
879 break;
880 case 0x3:
881 rev_str = "AB";
882 break;
883 case 0x4:
884 rev_str = "AC";
885 break;
886 }
887 break;
888 case 0x700:
889 dev_str = "XMC4700";
890
891 switch (rev_id) {
892 case 0x1:
893 rev_str = "EES-AA";
894 break;
895 }
896 break;
897 case 0x800:
898 dev_str = "XMC4800";
899
900 switch (rev_id) {
901 case 0x1:
902 rev_str = "EES-AA";
903 break;
904 }
905 break;
906
907 default:
908 snprintf(buf, buf_size,
909 "Cannot identify target as an XMC4xxx. SCU_ID: %"PRIx32"\n",
910 scu_idcode);
911 return ERROR_OK;
912 }
913
914 /* String to declare protection data held in the private driver */
915 char prot_str[512] = {0};
916 if (fb->read_protected)
917 snprintf(prot_str, sizeof(prot_str), "\nFlash is read protected");
918
919 bool otp_enabled = false;
920 for (int i = 0; i < bank->num_sectors; i++)
921 if (fb->write_prot_otp[i])
922 otp_enabled = true;
923
924 /* If OTP Write protection is enabled (User 2), list each
925 * sector that has it enabled */
926 char otp_str[8];
927 if (otp_enabled) {
928 strcat(prot_str, "\nOTP Protection is enabled for sectors:\n");
929 for (int i = 0; i < bank->num_sectors; i++) {
930 if (fb->write_prot_otp[i]) {
931 snprintf(otp_str, sizeof(otp_str), "- %d\n", i);
932 strncat(prot_str, otp_str, ARRAY_SIZE(otp_str));
933 }
934 }
935 }
936
937 if (rev_str != NULL)
938 snprintf(buf, buf_size, "%s - Rev: %s%s",
939 dev_str, rev_str, prot_str);
940 else
941 snprintf(buf, buf_size, "%s - Rev: unknown (0x%01x)%s",
942 dev_str, rev_id, prot_str);
943
944 return ERROR_OK;
945 }
946
947 static int xmc4xxx_temp_unprotect(struct flash_bank *bank, int user_level)
948 {
949 struct xmc4xxx_flash_bank *fb;
950 int res = ERROR_OK;
951 uint32_t status = 0;
952
953 struct xmc4xxx_command_seq temp_unprot_seq[6] = {
954 {FLASH_CMD_TEMP_UNPROT_1, 0xAA},
955 {FLASH_CMD_TEMP_UNPROT_2, 0x55},
956 {FLASH_CMD_TEMP_UNPROT_3, 0xFF}, /* Needs filled in */
957 {FLASH_CMD_TEMP_UNPROT_4, 0xFF}, /* Needs filled in */
958 {FLASH_CMD_TEMP_UNPROT_5, 0xFF}, /* Needs filled in */
959 {FLASH_CMD_TEMP_UNPROT_6, 0x05}
960 };
961
962 if (user_level < 0 || user_level > 2) {
963 LOG_ERROR("Invalid user level, must be 0-2");
964 return ERROR_FAIL;
965 }
966
967 fb = bank->driver_priv;
968
969 /* Fill in the user level and passwords */
970 temp_unprot_seq[2].magic = user_level;
971 temp_unprot_seq[3].magic = fb->pw1;
972 temp_unprot_seq[4].magic = fb->pw2;
973
974 res = xmc4xxx_write_command_sequence(bank, temp_unprot_seq,
975 ARRAY_SIZE(temp_unprot_seq));
976 if (res != ERROR_OK) {
977 LOG_ERROR("Unable to write temp unprotect sequence");
978 return res;
979 }
980
981 res = xmc4xxx_get_flash_status(bank, &status);
982 if (res != ERROR_OK)
983 return res;
984
985 if (status & FSR_WPRODIS0) {
986 LOG_INFO("Flash is temporarily unprotected");
987 } else {
988 LOG_INFO("Unable to disable flash protection");
989 res = ERROR_FAIL;
990 }
991
992
993 return res;
994 }
995
996 static int xmc4xxx_flash_unprotect(struct flash_bank *bank, int32_t level)
997 {
998 uint32_t addr;
999 int res;
1000
1001 switch (level) {
1002 case 0:
1003 addr = UCB0_BASE;
1004 break;
1005 case 1:
1006 addr = UCB1_BASE;
1007 break;
1008 default:
1009 LOG_ERROR("Invalid user level. Must be 0-1");
1010 return ERROR_FAIL;
1011 }
1012
1013 res = xmc4xxx_erase_sector(bank, addr, true);
1014
1015 if (res != ERROR_OK)
1016 LOG_ERROR("Error erasing user configuration block");
1017
1018 return res;
1019 }
1020
1021 /* Reference: "XMC4500 Flash Protection.pptx" app note */
1022 static int xmc4xxx_flash_protect(struct flash_bank *bank, int level, bool read_protect,
1023 int first, int last)
1024 {
1025 /* User configuration block buffers */
1026 uint8_t ucp0_buf[8 * sizeof(uint32_t)] = {0};
1027 uint32_t ucb_base = 0;
1028 uint32_t procon = 0;
1029 int res = ERROR_OK;
1030 uint32_t status = 0;
1031 bool proin = false;
1032
1033 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1034
1035 /* Read protect only works for user 0, make sure we don't try
1036 * to do something silly */
1037 if (level != 0 && read_protect) {
1038 LOG_ERROR("Read protection is for user level 0 only!");
1039 return ERROR_FAIL;
1040 }
1041
1042 /* Check to see if protection is already installed for the
1043 * specified user level. If it is, the user configuration
1044 * block will need to be erased before we can continue */
1045
1046 /* Grab the flash status register*/
1047 res = xmc4xxx_get_flash_status(bank, &status);
1048 if (res != ERROR_OK)
1049 return res;
1050
1051 switch (level) {
1052 case 0:
1053 if ((status & FSR_RPROIN_MASK) || (status & FSR_WPROIN0_MASK))
1054 proin = true;
1055 break;
1056 case 1:
1057 if (status & FSR_WPROIN1_MASK)
1058 proin = true;
1059 break;
1060 case 2:
1061 if (status & FSR_WPROIN2_MASK)
1062 proin = true;
1063 break;
1064 }
1065
1066 if (proin) {
1067 LOG_ERROR("Flash protection is installed for user %d"
1068 " and must be removed before continuing", level);
1069 return ERROR_FAIL;
1070 }
1071
1072 /* If this device has 12 flash sectors, protection for
1073 * sectors 10 & 11 are handled jointly. If we are trying to
1074 * write all sectors, we should decrement
1075 * last to ensure we don't write to a register bit that
1076 * doesn't exist*/
1077 if ((bank->num_sectors == 12) && (last == 12))
1078 last--;
1079
1080 /* We need to fill out the procon register representation
1081 * that we will be writing to the device */
1082 for (int i = first; i <= last; i++)
1083 procon |= 1 << i;
1084
1085 /* If read protection is requested, set the appropriate bit
1086 * (we checked that this is allowed above) */
1087 if (read_protect)
1088 procon |= PROCON_RPRO_MASK;
1089
1090 LOG_DEBUG("Setting flash protection with procon:");
1091 LOG_DEBUG("PROCON: %"PRIx32, procon);
1092
1093 /* First we need to copy in the procon register to the buffer
1094 * we're going to attempt to write. This is written twice */
1095 target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], procon);
1096 target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], procon);
1097
1098 /* Now we must copy in both flash passwords. As with the
1099 * procon data, this must be written twice (4 total words
1100 * worth of data) */
1101 target_buffer_set_u32(bank->target, &ucp0_buf[4 * 4], fb->pw1);
1102 target_buffer_set_u32(bank->target, &ucp0_buf[5 * 4], fb->pw2);
1103 target_buffer_set_u32(bank->target, &ucp0_buf[6 * 4], fb->pw1);
1104 target_buffer_set_u32(bank->target, &ucp0_buf[7 * 4], fb->pw2);
1105
1106 /* Finally, (if requested) we copy in the confirmation
1107 * code so that the protection is permanent and will
1108 * require a password to undo. */
1109 target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
1110 target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
1111
1112 /* Now that the data is copied into place, we must write
1113 * these pages into flash */
1114
1115 /* The user configuration block base depends on what level of
1116 * protection we're trying to install, select the proper one */
1117 switch (level) {
1118 case 0:
1119 ucb_base = UCB0_BASE;
1120 break;
1121 case 1:
1122 ucb_base = UCB1_BASE;
1123 break;
1124 case 2:
1125 ucb_base = UCB2_BASE;
1126 break;
1127 }
1128
1129 /* Write the user config pages */
1130 res = xmc4xxx_write_page(bank, ucp0_buf, ucb_base, true);
1131 if (res != ERROR_OK) {
1132 LOG_ERROR("Error writing user configuration block 0");
1133 return res;
1134 }
1135
1136 return ERROR_OK;
1137 }
1138
1139 static int xmc4xxx_protect(struct flash_bank *bank, int set, int first, int last)
1140 {
1141 int ret;
1142 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1143
1144 /* Check for flash passwords */
1145 if (!fb->pw_set) {
1146 LOG_ERROR("Flash passwords not set, use xmc4xxx flash_password to set them");
1147 return ERROR_FAIL;
1148 }
1149
1150 /* We want to clear flash protection temporarily*/
1151 if (set == 0) {
1152 LOG_WARNING("Flash protection will be temporarily disabled"
1153 " for all pages (User 0 only)!");
1154 ret = xmc4xxx_temp_unprotect(bank, 0);
1155 return ret;
1156 }
1157
1158 /* Install write protection for user 0 on the specified pages */
1159 ret = xmc4xxx_flash_protect(bank, 0, false, first, last);
1160
1161 return ret;
1162 }
1163
1164 static int xmc4xxx_protect_check(struct flash_bank *bank)
1165 {
1166 int ret;
1167 uint32_t protection[3] = {0};
1168 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1169
1170 ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON0, &protection[0]);
1171 if (ret != ERROR_OK) {
1172 LOG_ERROR("Unable to read flash User0 protection register");
1173 return ret;
1174 }
1175
1176 ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON1, &protection[1]);
1177 if (ret != ERROR_OK) {
1178 LOG_ERROR("Unable to read flash User1 protection register");
1179 return ret;
1180 }
1181
1182 ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON2, &protection[2]);
1183 if (ret != ERROR_OK) {
1184 LOG_ERROR("Unable to read flash User2 protection register");
1185 return ret;
1186 }
1187
1188 int sectors = bank->num_sectors;
1189
1190 /* On devices with 12 sectors, sectors 10 & 11 are ptected
1191 * together instead of individually */
1192 if (sectors == 12)
1193 sectors--;
1194
1195 /* Clear the protection status */
1196 for (int i = 0; i < bank->num_sectors; i++) {
1197 bank->sectors[i].is_protected = 0;
1198 fb->write_prot_otp[i] = false;
1199 }
1200 fb->read_protected = false;
1201
1202 /* The xmc4xxx series supports 3 levels of user protection
1203 * (User0, User1 (low priority), and User 2(OTP), we need to
1204 * check all 3 */
1205 for (unsigned int i = 0; i < ARRAY_SIZE(protection); i++) {
1206
1207 /* Check for write protection on every available
1208 * sector */
1209 for (int j = 0; j < sectors; j++) {
1210 int set = (protection[i] & (1 << j)) ? 1 : 0;
1211 bank->sectors[j].is_protected |= set;
1212
1213 /* Handle sector 11 */
1214 if (j == 10)
1215 bank->sectors[j + 1].is_protected |= set;
1216
1217 /* User 2 indicates this protection is
1218 * permanent, make note in the private driver structure */
1219 if (i == 2 && set) {
1220 fb->write_prot_otp[j] = true;
1221
1222 /* Handle sector 11 */
1223 if (j == 10)
1224 fb->write_prot_otp[j + 1] = true;
1225 }
1226
1227 }
1228 }
1229
1230 /* XMC4xxx also supports read proptection, make a note
1231 * in the private driver structure */
1232 if (protection[0] & PROCON_RPRO_MASK)
1233 fb->read_protected = true;
1234
1235 return ERROR_OK;
1236 }
1237
1238 FLASH_BANK_COMMAND_HANDLER(xmc4xxx_flash_bank_command)
1239 {
1240 bank->driver_priv = malloc(sizeof(struct xmc4xxx_flash_bank));
1241
1242 if (!bank->driver_priv)
1243 return ERROR_FLASH_OPERATION_FAILED;
1244
1245 (void)memset(bank->driver_priv, 0, sizeof(struct xmc4xxx_flash_bank));
1246
1247 return ERROR_OK;
1248 }
1249
1250 COMMAND_HANDLER(xmc4xxx_handle_flash_password_command)
1251 {
1252 int res;
1253 struct flash_bank *bank;
1254
1255 if (CMD_ARGC < 3)
1256 return ERROR_COMMAND_SYNTAX_ERROR;
1257
1258 res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1259 if (res != ERROR_OK)
1260 return res;
1261
1262 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1263
1264 errno = 0;
1265
1266 /* We skip over the flash bank */
1267 fb->pw1 = strtol(CMD_ARGV[1], NULL, 16);
1268
1269 if (errno)
1270 return ERROR_COMMAND_SYNTAX_ERROR;
1271
1272 fb->pw2 = strtol(CMD_ARGV[2], NULL, 16);
1273
1274 if (errno)
1275 return ERROR_COMMAND_SYNTAX_ERROR;
1276
1277 fb->pw_set = true;
1278
1279 command_print(CMD_CTX, "XMC4xxx flash passwords set to:\n");
1280 command_print(CMD_CTX, "-0x%08"PRIx32"\n", fb->pw1);
1281 command_print(CMD_CTX, "-0x%08"PRIx32"\n", fb->pw2);
1282 return ERROR_OK;
1283 }
1284
1285 COMMAND_HANDLER(xmc4xxx_handle_flash_unprotect_command)
1286 {
1287 struct flash_bank *bank;
1288 int res;
1289 int32_t level;
1290
1291 if (CMD_ARGC < 2)
1292 return ERROR_COMMAND_SYNTAX_ERROR;
1293
1294 res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1295 if (res != ERROR_OK)
1296 return res;
1297
1298 COMMAND_PARSE_NUMBER(s32, CMD_ARGV[1], level);
1299
1300 res = xmc4xxx_flash_unprotect(bank, level);
1301
1302 return res;
1303 }
1304
1305 static const struct command_registration xmc4xxx_exec_command_handlers[] = {
1306 {
1307 .name = "flash_password",
1308 .handler = xmc4xxx_handle_flash_password_command,
1309 .mode = COMMAND_EXEC,
1310 .usage = "bank_id password1 password2",
1311 .help = "Set the flash passwords used for protect operations. "
1312 "Passwords should be in standard hex form (0x00000000). "
1313 "(You must call this before any other protect commands) "
1314 "NOTE: The xmc4xxx's UCB area only allows for FOUR cycles. "
1315 "Please use protection carefully!",
1316 },
1317 {
1318 .name = "flash_unprotect",
1319 .handler = xmc4xxx_handle_flash_unprotect_command,
1320 .mode = COMMAND_EXEC,
1321 .usage = "bank_id user_level[0-1]",
1322 .help = "Permanently Removes flash protection (read and write) "
1323 "for the specified user level",
1324 }, COMMAND_REGISTRATION_DONE
1325 };
1326
1327 static const struct command_registration xmc4xxx_command_handlers[] = {
1328 {
1329 .name = "xmc4xxx",
1330 .mode = COMMAND_ANY,
1331 .help = "xmc4xxx flash command group",
1332 .usage = "",
1333 .chain = xmc4xxx_exec_command_handlers,
1334 },
1335 COMMAND_REGISTRATION_DONE
1336 };
1337
1338 struct flash_driver xmc4xxx_flash = {
1339 .name = "xmc4xxx",
1340 .commands = xmc4xxx_command_handlers,
1341 .flash_bank_command = xmc4xxx_flash_bank_command,
1342 .erase = xmc4xxx_erase,
1343 .write = xmc4xxx_write,
1344 .read = default_flash_read,
1345 .probe = xmc4xxx_probe,
1346 .auto_probe = xmc4xxx_probe,
1347 .erase_check = default_flash_blank_check,
1348 .info = xmc4xxx_get_info_command,
1349 .protect_check = xmc4xxx_protect_check,
1350 .protect = xmc4xxx_protect,
1351 };