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flash/str7x: After reset init the flash is unlocked
[openocd.git] / src / flash / nor / str7x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include "str7x.h"
29 #include <target/arm.h>
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32
33
34 struct str7x_mem_layout mem_layout_str7bank0[] = {
35 {0x00000000, 0x02000, 0x01},
36 {0x00002000, 0x02000, 0x02},
37 {0x00004000, 0x02000, 0x04},
38 {0x00006000, 0x02000, 0x08},
39 {0x00008000, 0x08000, 0x10},
40 {0x00010000, 0x10000, 0x20},
41 {0x00020000, 0x10000, 0x40},
42 {0x00030000, 0x10000, 0x80}
43 };
44
45 struct str7x_mem_layout mem_layout_str7bank1[] = {
46 {0x00000000, 0x02000, 0x10000},
47 {0x00002000, 0x02000, 0x20000}
48 };
49
50 static int str7x_get_flash_adr(struct flash_bank *bank, uint32_t reg)
51 {
52 struct str7x_flash_bank *str7x_info = bank->driver_priv;
53 return (str7x_info->register_base | reg);
54 }
55
56 static int str7x_build_block_list(struct flash_bank *bank)
57 {
58 struct str7x_flash_bank *str7x_info = bank->driver_priv;
59
60 int i;
61 int num_sectors;
62 int b0_sectors = 0, b1_sectors = 0;
63
64 switch (bank->size)
65 {
66 case 16 * 1024:
67 b1_sectors = 2;
68 break;
69 case 64 * 1024:
70 b0_sectors = 5;
71 break;
72 case 128 * 1024:
73 b0_sectors = 6;
74 break;
75 case 256 * 1024:
76 b0_sectors = 8;
77 break;
78 default:
79 LOG_ERROR("BUG: unknown bank->size encountered");
80 exit(-1);
81 }
82
83 num_sectors = b0_sectors + b1_sectors;
84
85 bank->num_sectors = num_sectors;
86 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
87 str7x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
88
89 num_sectors = 0;
90
91 for (i = 0; i < b0_sectors; i++)
92 {
93 bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
94 bank->sectors[num_sectors].size = mem_layout_str7bank0[i].sector_size;
95 bank->sectors[num_sectors].is_erased = -1;
96 /* the reset_init handler marks all the sectors unprotected,
97 * matching hardware after reset; keep the driver in sync
98 */
99 bank->sectors[num_sectors].is_protected = 0;
100 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
101 }
102
103 for (i = 0; i < b1_sectors; i++)
104 {
105 bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
106 bank->sectors[num_sectors].size = mem_layout_str7bank1[i].sector_size;
107 bank->sectors[num_sectors].is_erased = -1;
108 /* the reset_init handler marks all the sectors unprotected,
109 * matching hardware after reset; keep the driver in sync
110 */
111 bank->sectors[num_sectors].is_protected = 0;
112 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank1[i].sector_bit;
113 }
114
115 return ERROR_OK;
116 }
117
118 /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
119 */
120 FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command)
121 {
122 struct str7x_flash_bank *str7x_info;
123
124 if (CMD_ARGC < 7)
125 {
126 LOG_WARNING("incomplete flash_bank str7x configuration");
127 return ERROR_FLASH_BANK_INVALID;
128 }
129
130 str7x_info = malloc(sizeof(struct str7x_flash_bank));
131 bank->driver_priv = str7x_info;
132
133 /* set default bits for str71x flash */
134 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA1 | FLASH_BSYA0);
135 str7x_info->disable_bit = (1 << 1);
136
137 if (strcmp(CMD_ARGV[6], "STR71x") == 0)
138 {
139 str7x_info->register_base = 0x40100000;
140 }
141 else if (strcmp(CMD_ARGV[6], "STR73x") == 0)
142 {
143 str7x_info->register_base = 0x80100000;
144 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA0);
145 }
146 else if (strcmp(CMD_ARGV[6], "STR75x") == 0)
147 {
148 str7x_info->register_base = 0x20100000;
149 str7x_info->disable_bit = (1 << 0);
150 }
151 else
152 {
153 LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV[6]);
154 free(str7x_info);
155 return ERROR_FLASH_BANK_INVALID;
156 }
157
158 str7x_build_block_list(bank);
159
160 str7x_info->write_algorithm = NULL;
161
162 return ERROR_OK;
163 }
164
165 static uint32_t str7x_status(struct flash_bank *bank)
166 {
167 struct target *target = bank->target;
168 uint32_t retval;
169
170 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
171
172 return retval;
173 }
174
175 static uint32_t str7x_result(struct flash_bank *bank)
176 {
177 struct target *target = bank->target;
178 uint32_t retval;
179
180 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &retval);
181
182 return retval;
183 }
184
185 static int str7x_protect_check(struct flash_bank *bank)
186 {
187 struct str7x_flash_bank *str7x_info = bank->driver_priv;
188 struct target *target = bank->target;
189
190 int i;
191 uint32_t retval;
192
193 if (bank->target->state != TARGET_HALTED)
194 {
195 LOG_ERROR("Target not halted");
196 return ERROR_TARGET_NOT_HALTED;
197 }
198
199 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &retval);
200
201 for (i = 0; i < bank->num_sectors; i++)
202 {
203 if (retval & str7x_info->sector_bits[i])
204 bank->sectors[i].is_protected = 0;
205 else
206 bank->sectors[i].is_protected = 1;
207 }
208
209 return ERROR_OK;
210 }
211
212 static int str7x_erase(struct flash_bank *bank, int first, int last)
213 {
214 struct str7x_flash_bank *str7x_info = bank->driver_priv;
215 struct target *target = bank->target;
216
217 int i;
218 uint32_t cmd;
219 uint32_t retval;
220 uint32_t sectors = 0;
221
222 if (bank->target->state != TARGET_HALTED)
223 {
224 LOG_ERROR("Target not halted");
225 return ERROR_TARGET_NOT_HALTED;
226 }
227
228 for (i = first; i <= last; i++)
229 {
230 sectors |= str7x_info->sector_bits[i];
231 }
232
233 LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
234
235 /* clear FLASH_ER register */
236 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
237
238 cmd = FLASH_SER;
239 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
240
241 cmd = sectors;
242 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
243
244 cmd = FLASH_SER | FLASH_WMS;
245 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
246
247 while (((retval = str7x_status(bank)) & str7x_info->busy_bits)) {
248 alive_sleep(1);
249 }
250
251 retval = str7x_result(bank);
252
253 if (retval)
254 {
255 LOG_ERROR("error erasing flash bank, FLASH_ER: 0x%" PRIx32 "", retval);
256 return ERROR_FLASH_OPERATION_FAILED;
257 }
258
259 for (i = first; i <= last; i++)
260 bank->sectors[i].is_erased = 1;
261
262 return ERROR_OK;
263 }
264
265 static int str7x_protect(struct flash_bank *bank, int set, int first, int last)
266 {
267 struct str7x_flash_bank *str7x_info = bank->driver_priv;
268 struct target *target = bank->target;
269 int i;
270 uint32_t cmd;
271 uint32_t retval;
272 uint32_t protect_blocks;
273
274 if (bank->target->state != TARGET_HALTED)
275 {
276 LOG_ERROR("Target not halted");
277 return ERROR_TARGET_NOT_HALTED;
278 }
279
280 protect_blocks = 0xFFFFFFFF;
281
282 if (set)
283 {
284 for (i = first; i <= last; i++)
285 protect_blocks &= ~(str7x_info->sector_bits[i]);
286 }
287
288 /* clear FLASH_ER register */
289 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
290
291 cmd = FLASH_SPR;
292 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
293
294 cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
295 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
296
297 cmd = protect_blocks;
298 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
299
300 cmd = FLASH_SPR | FLASH_WMS;
301 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
302
303 while (((retval = str7x_status(bank)) & str7x_info->busy_bits)) {
304 alive_sleep(1);
305 }
306
307 retval = str7x_result(bank);
308
309 LOG_DEBUG("retval: 0x%8.8" PRIx32 "", retval);
310
311 if (retval & FLASH_ERER)
312 return ERROR_FLASH_SECTOR_NOT_ERASED;
313 else if (retval & FLASH_WPF)
314 return ERROR_FLASH_OPERATION_FAILED;
315
316 return ERROR_OK;
317 }
318
319 static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
320 {
321 struct str7x_flash_bank *str7x_info = bank->driver_priv;
322 struct target *target = bank->target;
323 uint32_t buffer_size = 8192;
324 struct working_area *source;
325 uint32_t address = bank->base + offset;
326 struct reg_param reg_params[6];
327 struct arm_algorithm armv4_5_info;
328 int retval = ERROR_OK;
329
330 uint32_t str7x_flash_write_code[] = {
331 /* write: */
332 0xe3a04201, /* mov r4, #0x10000000 */
333 0xe5824000, /* str r4, [r2, #0x0] */
334 0xe5821010, /* str r1, [r2, #0x10] */
335 0xe4904004, /* ldr r4, [r0], #4 */
336 0xe5824008, /* str r4, [r2, #0x8] */
337 0xe4904004, /* ldr r4, [r0], #4 */
338 0xe582400c, /* str r4, [r2, #0xc] */
339 0xe3a04209, /* mov r4, #0x90000000 */
340 0xe5824000, /* str r4, [r2, #0x0] */
341 /* busy: */
342 0xe5924000, /* ldr r4, [r2, #0x0] */
343 0xe1140005, /* tst r4, r5 */
344 0x1afffffc, /* bne busy */
345 0xe5924014, /* ldr r4, [r2, #0x14] */
346 0xe31400ff, /* tst r4, #0xff */
347 0x03140c01, /* tsteq r4, #0x100 */
348 0x1a000002, /* bne exit */
349 0xe2811008, /* add r1, r1, #0x8 */
350 0xe2533001, /* subs r3, r3, #1 */
351 0x1affffec, /* bne write */
352 /* exit: */
353 0xeafffffe, /* b exit */
354 };
355
356 /* flash write code */
357 if (target_alloc_working_area(target, 4 * 20, &str7x_info->write_algorithm) != ERROR_OK)
358 {
359 LOG_WARNING("no working area available, can't do block memory writes");
360 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
361 };
362
363 target_write_buffer(target, str7x_info->write_algorithm->address, 20 * 4, (uint8_t*)str7x_flash_write_code);
364
365 /* memory buffer */
366 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
367 {
368 buffer_size /= 2;
369 if (buffer_size <= 256)
370 {
371 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
372 if (str7x_info->write_algorithm)
373 target_free_working_area(target, str7x_info->write_algorithm);
374
375 LOG_WARNING("no large enough working area available, can't do block memory writes");
376 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
377 }
378 }
379
380 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
381 armv4_5_info.core_mode = ARM_MODE_SVC;
382 armv4_5_info.core_state = ARM_STATE_ARM;
383
384 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
385 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
386 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
387 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
388 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
389 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
390
391 while (count > 0)
392 {
393 uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
394
395 target_write_buffer(target, source->address, thisrun_count * 8, buffer);
396
397 buf_set_u32(reg_params[0].value, 0, 32, source->address);
398 buf_set_u32(reg_params[1].value, 0, 32, address);
399 buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
400 buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
401 buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
402
403 if ((retval = target_run_algorithm(target, 0, NULL, 6, reg_params, str7x_info->write_algorithm->address, str7x_info->write_algorithm->address + (19 * 4), 10000, &armv4_5_info)) != ERROR_OK)
404 {
405 LOG_ERROR("error executing str7x flash write algorithm");
406 retval = ERROR_FLASH_OPERATION_FAILED;
407 break;
408 }
409
410 if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
411 {
412 retval = ERROR_FLASH_OPERATION_FAILED;
413 break;
414 }
415
416 buffer += thisrun_count * 8;
417 address += thisrun_count * 8;
418 count -= thisrun_count;
419 }
420
421 target_free_working_area(target, source);
422 target_free_working_area(target, str7x_info->write_algorithm);
423
424 destroy_reg_param(&reg_params[0]);
425 destroy_reg_param(&reg_params[1]);
426 destroy_reg_param(&reg_params[2]);
427 destroy_reg_param(&reg_params[3]);
428 destroy_reg_param(&reg_params[4]);
429 destroy_reg_param(&reg_params[5]);
430
431 return retval;
432 }
433
434 static int str7x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
435 {
436 struct target *target = bank->target;
437 struct str7x_flash_bank *str7x_info = bank->driver_priv;
438 uint32_t dwords_remaining = (count / 8);
439 uint32_t bytes_remaining = (count & 0x00000007);
440 uint32_t address = bank->base + offset;
441 uint32_t bytes_written = 0;
442 uint32_t cmd;
443 int retval;
444 uint32_t check_address = offset;
445 int i;
446
447 if (bank->target->state != TARGET_HALTED)
448 {
449 LOG_ERROR("Target not halted");
450 return ERROR_TARGET_NOT_HALTED;
451 }
452
453 if (offset & 0x7)
454 {
455 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset);
456 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
457 }
458
459 for (i = 0; i < bank->num_sectors; i++)
460 {
461 uint32_t sec_start = bank->sectors[i].offset;
462 uint32_t sec_end = sec_start + bank->sectors[i].size;
463
464 /* check if destination falls within the current sector */
465 if ((check_address >= sec_start) && (check_address < sec_end))
466 {
467 /* check if destination ends in the current sector */
468 if (offset + count < sec_end)
469 check_address = offset + count;
470 else
471 check_address = sec_end;
472 }
473 }
474
475 if (check_address != offset + count)
476 return ERROR_FLASH_DST_OUT_OF_BANK;
477
478 /* clear FLASH_ER register */
479 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
480
481 /* multiple dwords (8-byte) to be programmed? */
482 if (dwords_remaining > 0)
483 {
484 /* try using a block write */
485 if ((retval = str7x_write_block(bank, buffer, offset, dwords_remaining)) != ERROR_OK)
486 {
487 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
488 {
489 /* if block write failed (no sufficient working area),
490 * we use normal (slow) single dword accesses */
491 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
492 }
493 else if (retval == ERROR_FLASH_OPERATION_FAILED)
494 {
495 /* if an error occured, we examine the reason, and quit */
496 retval = str7x_result(bank);
497
498 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
499 return ERROR_FLASH_OPERATION_FAILED;
500 }
501 }
502 else
503 {
504 buffer += dwords_remaining * 8;
505 address += dwords_remaining * 8;
506 dwords_remaining = 0;
507 }
508 }
509
510 while (dwords_remaining > 0)
511 {
512 /* command */
513 cmd = FLASH_DWPG;
514 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
515
516 /* address */
517 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
518
519 /* data word 1 */
520 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, buffer + bytes_written);
521 bytes_written += 4;
522
523 /* data word 2 */
524 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, buffer + bytes_written);
525 bytes_written += 4;
526
527 /* start programming cycle */
528 cmd = FLASH_DWPG | FLASH_WMS;
529 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
530
531 while (((retval = str7x_status(bank)) & str7x_info->busy_bits))
532 {
533 alive_sleep(1);
534 }
535
536 retval = str7x_result(bank);
537
538 if (retval & FLASH_PGER)
539 return ERROR_FLASH_OPERATION_FAILED;
540 else if (retval & FLASH_WPF)
541 return ERROR_FLASH_OPERATION_FAILED;
542
543 dwords_remaining--;
544 address += 8;
545 }
546
547 if (bytes_remaining)
548 {
549 uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
550 int i = 0;
551
552 while (bytes_remaining > 0)
553 {
554 last_dword[i++] = *(buffer + bytes_written);
555 bytes_remaining--;
556 bytes_written++;
557 }
558
559 /* command */
560 cmd = FLASH_DWPG;
561 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
562
563 /* address */
564 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
565
566 /* data word 1 */
567 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, last_dword);
568 bytes_written += 4;
569
570 /* data word 2 */
571 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, last_dword + 4);
572 bytes_written += 4;
573
574 /* start programming cycle */
575 cmd = FLASH_DWPG | FLASH_WMS;
576 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
577
578 while (((retval = str7x_status(bank)) & str7x_info->busy_bits))
579 {
580 alive_sleep(1);
581 }
582
583 retval = str7x_result(bank);
584
585 if (retval & FLASH_PGER)
586 return ERROR_FLASH_OPERATION_FAILED;
587 else if (retval & FLASH_WPF)
588 return ERROR_FLASH_OPERATION_FAILED;
589 }
590
591 return ERROR_OK;
592 }
593
594 static int str7x_probe(struct flash_bank *bank)
595 {
596 return ERROR_OK;
597 }
598
599 #if 0
600 COMMAND_HANDLER(str7x_handle_part_id_command)
601 {
602 return ERROR_OK;
603 }
604 #endif
605
606 static int str7x_info(struct flash_bank *bank, char *buf, int buf_size)
607 {
608 snprintf(buf, buf_size, "str7x flash driver info");
609 /* STR7x flash doesn't support sector protection interrogation.
610 * FLASH_NVWPAR acts as a write only register; its read value
611 * doesn't reflect the actual protection state of the sectors.
612 */
613 LOG_WARNING("STR7x flash lock information might not be correct "
614 "due to hardware limitations.");
615 return ERROR_OK;
616 }
617
618 COMMAND_HANDLER(str7x_handle_disable_jtag_command)
619 {
620 struct target *target = NULL;
621 struct str7x_flash_bank *str7x_info = NULL;
622
623 uint32_t flash_cmd;
624 uint16_t ProtectionLevel = 0;
625 uint16_t ProtectionRegs;
626
627 if (CMD_ARGC < 1)
628 {
629 command_print(CMD_CTX, "str7x disable_jtag <bank>");
630 return ERROR_OK;
631 }
632
633 struct flash_bank *bank;
634 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
635 if (ERROR_OK != retval)
636 return retval;
637
638 str7x_info = bank->driver_priv;
639
640 target = bank->target;
641
642 if (target->state != TARGET_HALTED)
643 {
644 LOG_ERROR("Target not halted");
645 return ERROR_TARGET_NOT_HALTED;
646 }
647
648 /* first we get protection status */
649 uint32_t reg;
650 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &reg);
651
652 if (!(reg & str7x_info->disable_bit))
653 {
654 ProtectionLevel = 1;
655 }
656
657 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &reg);
658 ProtectionRegs = ~(reg >> 16);
659
660 while (((ProtectionRegs) != 0) && (ProtectionLevel < 16))
661 {
662 ProtectionRegs >>= 1;
663 ProtectionLevel++;
664 }
665
666 if (ProtectionLevel == 0)
667 {
668 flash_cmd = FLASH_SPR;
669 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
670 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
671 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), 0xFFFFFFFD);
672 flash_cmd = FLASH_SPR | FLASH_WMS;
673 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
674 }
675 else
676 {
677 flash_cmd = FLASH_SPR;
678 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
679 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
680 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), ~(1 << (15 + ProtectionLevel)));
681 flash_cmd = FLASH_SPR | FLASH_WMS;
682 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
683 }
684
685 return ERROR_OK;
686 }
687
688 static const struct command_registration str7x_exec_command_handlers[] = {
689 {
690 .name = "disable_jtag",
691 .handler = str7x_handle_disable_jtag_command,
692 .mode = COMMAND_EXEC,
693 .help = "disable jtag access",
694 },
695 COMMAND_REGISTRATION_DONE
696 };
697 static const struct command_registration str7x_command_handlers[] = {
698 {
699 .name = "str7x",
700 .mode = COMMAND_ANY,
701 .help = "str7x flash command group",
702 .chain = str7x_exec_command_handlers,
703 },
704 COMMAND_REGISTRATION_DONE
705 };
706
707 struct flash_driver str7x_flash = {
708 .name = "str7x",
709 .commands = str7x_command_handlers,
710 .flash_bank_command = str7x_flash_bank_command,
711 .erase = str7x_erase,
712 .protect = str7x_protect,
713 .write = str7x_write,
714 .probe = str7x_probe,
715 .auto_probe = str7x_probe,
716 .erase_check = default_flash_blank_check,
717 .protect_check = str7x_protect_check,
718 .info = str7x_info,
719 };
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