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error handling: the error number is not part of the user interface
[openocd.git] / src / flash / nor / str7x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2010 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "imp.h"
31 #include <target/arm.h>
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34
35
36 /* Flash registers */
37
38 #define FLASH_CR0 0x00000000
39 #define FLASH_CR1 0x00000004
40 #define FLASH_DR0 0x00000008
41 #define FLASH_DR1 0x0000000C
42 #define FLASH_AR 0x00000010
43 #define FLASH_ER 0x00000014
44 #define FLASH_NVWPAR 0x0000DFB0
45 #define FLASH_NVAPR0 0x0000DFB8
46 #define FLASH_NVAPR1 0x0000DFBC
47
48 /* FLASH_CR0 register bits */
49
50 #define FLASH_WMS 0x80000000
51 #define FLASH_SUSP 0x40000000
52 #define FLASH_WPG 0x20000000
53 #define FLASH_DWPG 0x10000000
54 #define FLASH_SER 0x08000000
55 #define FLASH_SPR 0x01000000
56 #define FLASH_BER 0x04000000
57 #define FLASH_MER 0x02000000
58 #define FLASH_LOCK 0x00000010
59 #define FLASH_BSYA1 0x00000004
60 #define FLASH_BSYA0 0x00000002
61
62 /* FLASH_CR1 register bits */
63
64 #define FLASH_B1S 0x02000000
65 #define FLASH_B0S 0x01000000
66 #define FLASH_B1F1 0x00020000
67 #define FLASH_B1F0 0x00010000
68 #define FLASH_B0F7 0x00000080
69 #define FLASH_B0F6 0x00000040
70 #define FLASH_B0F5 0x00000020
71 #define FLASH_B0F4 0x00000010
72 #define FLASH_B0F3 0x00000008
73 #define FLASH_B0F2 0x00000004
74 #define FLASH_B0F1 0x00000002
75 #define FLASH_B0F0 0x00000001
76
77 /* FLASH_ER register bits */
78
79 #define FLASH_WPF 0x00000100
80 #define FLASH_RESER 0x00000080
81 #define FLASH_SEQER 0x00000040
82 #define FLASH_10ER 0x00000008
83 #define FLASH_PGER 0x00000004
84 #define FLASH_ERER 0x00000002
85 #define FLASH_ERR 0x00000001
86
87
88 struct str7x_flash_bank
89 {
90 uint32_t *sector_bits;
91 uint32_t disable_bit;
92 uint32_t busy_bits;
93 uint32_t register_base;
94 struct working_area *write_algorithm;
95 };
96
97 struct str7x_mem_layout {
98 uint32_t sector_start;
99 uint32_t sector_size;
100 uint32_t sector_bit;
101 };
102
103 enum str7x_status_codes
104 {
105 STR7X_CMD_SUCCESS = 0,
106 STR7X_INVALID_COMMAND = 1,
107 STR7X_SRC_ADDR_ERROR = 2,
108 STR7X_DST_ADDR_ERROR = 3,
109 STR7X_SRC_ADDR_NOT_MAPPED = 4,
110 STR7X_DST_ADDR_NOT_MAPPED = 5,
111 STR7X_COUNT_ERROR = 6,
112 STR7X_INVALID_SECTOR = 7,
113 STR7X_SECTOR_NOT_BLANK = 8,
114 STR7X_SECTOR_NOT_PREPARED = 9,
115 STR7X_COMPARE_ERROR = 10,
116 STR7X_BUSY = 11
117 };
118
119 static struct str7x_mem_layout mem_layout_str7bank0[] = {
120 {0x00000000, 0x02000, 0x01},
121 {0x00002000, 0x02000, 0x02},
122 {0x00004000, 0x02000, 0x04},
123 {0x00006000, 0x02000, 0x08},
124 {0x00008000, 0x08000, 0x10},
125 {0x00010000, 0x10000, 0x20},
126 {0x00020000, 0x10000, 0x40},
127 {0x00030000, 0x10000, 0x80}
128 };
129
130 static struct str7x_mem_layout mem_layout_str7bank1[] = {
131 {0x00000000, 0x02000, 0x10000},
132 {0x00002000, 0x02000, 0x20000}
133 };
134
135 static int str7x_get_flash_adr(struct flash_bank *bank, uint32_t reg)
136 {
137 struct str7x_flash_bank *str7x_info = bank->driver_priv;
138 return (str7x_info->register_base | reg);
139 }
140
141 static int str7x_build_block_list(struct flash_bank *bank)
142 {
143 struct str7x_flash_bank *str7x_info = bank->driver_priv;
144
145 int i;
146 int num_sectors;
147 int b0_sectors = 0, b1_sectors = 0;
148
149 switch (bank->size)
150 {
151 case 16 * 1024:
152 b1_sectors = 2;
153 break;
154 case 64 * 1024:
155 b0_sectors = 5;
156 break;
157 case 128 * 1024:
158 b0_sectors = 6;
159 break;
160 case 256 * 1024:
161 b0_sectors = 8;
162 break;
163 default:
164 LOG_ERROR("BUG: unknown bank->size encountered");
165 exit(-1);
166 }
167
168 num_sectors = b0_sectors + b1_sectors;
169
170 bank->num_sectors = num_sectors;
171 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
172 str7x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
173
174 num_sectors = 0;
175
176 for (i = 0; i < b0_sectors; i++)
177 {
178 bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
179 bank->sectors[num_sectors].size = mem_layout_str7bank0[i].sector_size;
180 bank->sectors[num_sectors].is_erased = -1;
181 /* the reset_init handler marks all the sectors unprotected,
182 * matching hardware after reset; keep the driver in sync
183 */
184 bank->sectors[num_sectors].is_protected = 0;
185 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
186 }
187
188 for (i = 0; i < b1_sectors; i++)
189 {
190 bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
191 bank->sectors[num_sectors].size = mem_layout_str7bank1[i].sector_size;
192 bank->sectors[num_sectors].is_erased = -1;
193 /* the reset_init handler marks all the sectors unprotected,
194 * matching hardware after reset; keep the driver in sync
195 */
196 bank->sectors[num_sectors].is_protected = 0;
197 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank1[i].sector_bit;
198 }
199
200 return ERROR_OK;
201 }
202
203 /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
204 */
205 FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command)
206 {
207 struct str7x_flash_bank *str7x_info;
208
209 if (CMD_ARGC < 7)
210 {
211 LOG_WARNING("incomplete flash_bank str7x configuration");
212 return ERROR_FLASH_BANK_INVALID;
213 }
214
215 str7x_info = malloc(sizeof(struct str7x_flash_bank));
216 bank->driver_priv = str7x_info;
217
218 /* set default bits for str71x flash */
219 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA1 | FLASH_BSYA0);
220 str7x_info->disable_bit = (1 << 1);
221
222 if (strcmp(CMD_ARGV[6], "STR71x") == 0)
223 {
224 str7x_info->register_base = 0x40100000;
225 }
226 else if (strcmp(CMD_ARGV[6], "STR73x") == 0)
227 {
228 str7x_info->register_base = 0x80100000;
229 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA0);
230 }
231 else if (strcmp(CMD_ARGV[6], "STR75x") == 0)
232 {
233 str7x_info->register_base = 0x20100000;
234 str7x_info->disable_bit = (1 << 0);
235 }
236 else
237 {
238 LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV[6]);
239 free(str7x_info);
240 return ERROR_FLASH_BANK_INVALID;
241 }
242
243 str7x_build_block_list(bank);
244
245 str7x_info->write_algorithm = NULL;
246
247 return ERROR_OK;
248 }
249
250 /* wait for flash to become idle or report errors.
251
252 FIX!!! what's the maximum timeout??? The documentation doesn't
253 state any maximum time.... by inspection it seems > 1000ms is to be
254 expected.
255
256 10000ms is long enough that it should cover anything, yet not
257 quite be equivalent to an infinite loop.
258
259 */
260 static int str7x_waitbusy(struct flash_bank *bank)
261 {
262 int err;
263 int i;
264 struct target *target = bank->target;
265 struct str7x_flash_bank *str7x_info = bank->driver_priv;
266
267 for (i = 0 ; i < 10000; i++)
268 {
269 uint32_t retval;
270 err = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
271 if (err != ERROR_OK)
272 return err;
273
274 if ((retval & str7x_info->busy_bits) == 0)
275 return ERROR_OK;
276
277 alive_sleep(1);
278 }
279 LOG_ERROR("Timed out waiting for str7x flash");
280 return ERROR_FAIL;
281 }
282
283
284 static int str7x_result(struct flash_bank *bank)
285 {
286 struct target *target = bank->target;
287 uint32_t retval;
288
289 int err;
290 err = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &retval);
291 if (err != ERROR_OK)
292 return err;
293
294 if (retval & FLASH_WPF)
295 {
296 LOG_ERROR("str7x hw write protection set");
297 err = ERROR_FAIL;
298 }
299 if (retval & FLASH_RESER)
300 {
301 LOG_ERROR("str7x suspended program erase not resumed");
302 err = ERROR_FAIL;
303 }
304 if (retval & FLASH_10ER)
305 {
306 LOG_ERROR("str7x trying to set bit to 1 when it is already 0");
307 err = ERROR_FAIL;
308 }
309 if (retval & FLASH_PGER)
310 {
311 LOG_ERROR("str7x program error");
312 err = ERROR_FAIL;
313 }
314 if (retval & FLASH_ERER)
315 {
316 LOG_ERROR("str7x erase error");
317 err = ERROR_FAIL;
318 }
319 if (err == ERROR_OK)
320 {
321 if (retval & FLASH_ERR)
322 {
323 /* this should always be set if one of the others are set... */
324 LOG_ERROR("str7x write operation failed / bad setup");
325 err = ERROR_FAIL;
326 }
327 }
328
329 return retval;
330 }
331
332 static int str7x_protect_check(struct flash_bank *bank)
333 {
334 struct str7x_flash_bank *str7x_info = bank->driver_priv;
335 struct target *target = bank->target;
336
337 int i;
338 uint32_t retval;
339
340 if (bank->target->state != TARGET_HALTED)
341 {
342 LOG_ERROR("Target not halted");
343 return ERROR_TARGET_NOT_HALTED;
344 }
345
346 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &retval);
347
348 for (i = 0; i < bank->num_sectors; i++)
349 {
350 if (retval & str7x_info->sector_bits[i])
351 bank->sectors[i].is_protected = 0;
352 else
353 bank->sectors[i].is_protected = 1;
354 }
355
356 return ERROR_OK;
357 }
358
359 static int str7x_erase(struct flash_bank *bank, int first, int last)
360 {
361 struct str7x_flash_bank *str7x_info = bank->driver_priv;
362 struct target *target = bank->target;
363
364 int i;
365 uint32_t cmd;
366 uint32_t sectors = 0;
367 int err;
368
369 if (bank->target->state != TARGET_HALTED)
370 {
371 LOG_ERROR("Target not halted");
372 return ERROR_TARGET_NOT_HALTED;
373 }
374
375 for (i = first; i <= last; i++)
376 {
377 sectors |= str7x_info->sector_bits[i];
378 }
379
380 LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
381
382 /* clear FLASH_ER register */
383 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
384 if (err != ERROR_OK)
385 return err;
386
387 cmd = FLASH_SER;
388 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
389 if (err != ERROR_OK)
390 return err;
391
392 cmd = sectors;
393 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
394 if (err != ERROR_OK)
395 return err;
396
397 cmd = FLASH_SER | FLASH_WMS;
398 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
399 if (err != ERROR_OK)
400 return err;
401
402 err = str7x_waitbusy(bank);
403 if (err != ERROR_OK)
404 return err;
405
406 err = str7x_result(bank);
407 if (err != ERROR_OK)
408 return err;
409
410 for (i = first; i <= last; i++)
411 bank->sectors[i].is_erased = 1;
412
413 return ERROR_OK;
414 }
415
416 static int str7x_protect(struct flash_bank *bank, int set, int first, int last)
417 {
418 struct str7x_flash_bank *str7x_info = bank->driver_priv;
419 struct target *target = bank->target;
420 int i;
421 uint32_t cmd;
422 uint32_t protect_blocks;
423
424 if (bank->target->state != TARGET_HALTED)
425 {
426 LOG_ERROR("Target not halted");
427 return ERROR_TARGET_NOT_HALTED;
428 }
429
430 protect_blocks = 0xFFFFFFFF;
431
432 if (set)
433 {
434 for (i = first; i <= last; i++)
435 protect_blocks &= ~(str7x_info->sector_bits[i]);
436 }
437
438 /* clear FLASH_ER register */
439 int err;
440 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
441 if (err != ERROR_OK)
442 return err;
443
444 cmd = FLASH_SPR;
445 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
446 if (err != ERROR_OK)
447 return err;
448
449 cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
450 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
451 if (err != ERROR_OK)
452 return err;
453
454 cmd = protect_blocks;
455 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
456 if (err != ERROR_OK)
457 return err;
458
459 cmd = FLASH_SPR | FLASH_WMS;
460 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
461 if (err != ERROR_OK)
462 return err;
463
464 err = str7x_waitbusy(bank);
465 if (err != ERROR_OK)
466 return err;
467
468 err = str7x_result(bank);
469 if (err != ERROR_OK)
470 return err;
471
472 return ERROR_OK;
473 }
474
475 static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer,
476 uint32_t offset, uint32_t count)
477 {
478 struct str7x_flash_bank *str7x_info = bank->driver_priv;
479 struct target *target = bank->target;
480 uint32_t buffer_size = 32768;
481 struct working_area *source;
482 uint32_t address = bank->base + offset;
483 struct reg_param reg_params[6];
484 struct arm_algorithm armv4_5_info;
485 int retval = ERROR_OK;
486
487 /* see contib/loaders/flash/str7x.s for src */
488
489 static const uint32_t str7x_flash_write_code[] = {
490 /* write: */
491 0xe3a04201, /* mov r4, #0x10000000 */
492 0xe5824000, /* str r4, [r2, #0x0] */
493 0xe5821010, /* str r1, [r2, #0x10] */
494 0xe4904004, /* ldr r4, [r0], #4 */
495 0xe5824008, /* str r4, [r2, #0x8] */
496 0xe4904004, /* ldr r4, [r0], #4 */
497 0xe582400c, /* str r4, [r2, #0xc] */
498 0xe3a04209, /* mov r4, #0x90000000 */
499 0xe5824000, /* str r4, [r2, #0x0] */
500 /* busy: */
501 0xe5924000, /* ldr r4, [r2, #0x0] */
502 0xe1140005, /* tst r4, r5 */
503 0x1afffffc, /* bne busy */
504 0xe5924014, /* ldr r4, [r2, #0x14] */
505 0xe31400ff, /* tst r4, #0xff */
506 0x03140c01, /* tsteq r4, #0x100 */
507 0x1a000002, /* bne exit */
508 0xe2811008, /* add r1, r1, #0x8 */
509 0xe2533001, /* subs r3, r3, #1 */
510 0x1affffec, /* bne write */
511 /* exit: */
512 0xeafffffe, /* b exit */
513 };
514
515 /* flash write code */
516 if (target_alloc_working_area_try(target, sizeof(str7x_flash_write_code),
517 &str7x_info->write_algorithm) != ERROR_OK)
518 {
519 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
520 };
521
522 target_write_buffer(target, str7x_info->write_algorithm->address,
523 sizeof(str7x_flash_write_code),
524 (uint8_t*)str7x_flash_write_code);
525
526 /* memory buffer */
527 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
528 {
529 buffer_size /= 2;
530 if (buffer_size <= 256)
531 {
532 /* if we already allocated the writing code, but failed to get a
533 * buffer, free the algorithm */
534 if (str7x_info->write_algorithm)
535 target_free_working_area(target, str7x_info->write_algorithm);
536
537 LOG_WARNING("no large enough working area available, can't do block memory writes");
538 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
539 }
540 }
541
542 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
543 armv4_5_info.core_mode = ARM_MODE_SVC;
544 armv4_5_info.core_state = ARM_STATE_ARM;
545
546 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
547 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
548 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
549 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
550 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
551 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
552
553 while (count > 0)
554 {
555 uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
556
557 target_write_buffer(target, source->address, thisrun_count * 8, buffer);
558
559 buf_set_u32(reg_params[0].value, 0, 32, source->address);
560 buf_set_u32(reg_params[1].value, 0, 32, address);
561 buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
562 buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
563 buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
564
565 if ((retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
566 str7x_info->write_algorithm->address,
567 str7x_info->write_algorithm->address + (sizeof(str7x_flash_write_code) - 4),
568 10000, &armv4_5_info)) != ERROR_OK)
569 {
570 break;
571 }
572
573 if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
574 {
575 retval = str7x_result(bank);
576 break;
577 }
578
579 buffer += thisrun_count * 8;
580 address += thisrun_count * 8;
581 count -= thisrun_count;
582 }
583
584 target_free_working_area(target, source);
585 target_free_working_area(target, str7x_info->write_algorithm);
586
587 destroy_reg_param(&reg_params[0]);
588 destroy_reg_param(&reg_params[1]);
589 destroy_reg_param(&reg_params[2]);
590 destroy_reg_param(&reg_params[3]);
591 destroy_reg_param(&reg_params[4]);
592 destroy_reg_param(&reg_params[5]);
593
594 return retval;
595 }
596
597 static int str7x_write(struct flash_bank *bank, uint8_t *buffer,
598 uint32_t offset, uint32_t count)
599 {
600 struct target *target = bank->target;
601 uint32_t dwords_remaining = (count / 8);
602 uint32_t bytes_remaining = (count & 0x00000007);
603 uint32_t address = bank->base + offset;
604 uint32_t bytes_written = 0;
605 uint32_t cmd;
606 int retval;
607 uint32_t check_address = offset;
608 int i;
609
610 if (bank->target->state != TARGET_HALTED)
611 {
612 LOG_ERROR("Target not halted");
613 return ERROR_TARGET_NOT_HALTED;
614 }
615
616 if (offset & 0x7)
617 {
618 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset);
619 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
620 }
621
622 for (i = 0; i < bank->num_sectors; i++)
623 {
624 uint32_t sec_start = bank->sectors[i].offset;
625 uint32_t sec_end = sec_start + bank->sectors[i].size;
626
627 /* check if destination falls within the current sector */
628 if ((check_address >= sec_start) && (check_address < sec_end))
629 {
630 /* check if destination ends in the current sector */
631 if (offset + count < sec_end)
632 check_address = offset + count;
633 else
634 check_address = sec_end;
635 }
636 }
637
638 if (check_address != offset + count)
639 return ERROR_FLASH_DST_OUT_OF_BANK;
640
641 /* clear FLASH_ER register */
642 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
643
644 /* multiple dwords (8-byte) to be programmed? */
645 if (dwords_remaining > 0)
646 {
647 /* try using a block write */
648 if ((retval = str7x_write_block(bank, buffer, offset,
649 dwords_remaining)) != ERROR_OK)
650 {
651 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
652 {
653 /* if block write failed (no sufficient working area),
654 * we use normal (slow) single dword accesses */
655 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
656 } else
657 {
658 return retval;
659 }
660 }
661 else
662 {
663 buffer += dwords_remaining * 8;
664 address += dwords_remaining * 8;
665 dwords_remaining = 0;
666 }
667 }
668
669 while (dwords_remaining > 0)
670 {
671 /* command */
672 cmd = FLASH_DWPG;
673 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
674
675 /* address */
676 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
677
678 /* data word 1 */
679 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
680 4, 1, buffer + bytes_written);
681 bytes_written += 4;
682
683 /* data word 2 */
684 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
685 4, 1, buffer + bytes_written);
686 bytes_written += 4;
687
688 /* start programming cycle */
689 cmd = FLASH_DWPG | FLASH_WMS;
690 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
691
692 int err;
693 err = str7x_waitbusy(bank);
694 if (err != ERROR_OK)
695 return err;
696
697 err = str7x_result(bank);
698 if (err != ERROR_OK)
699 return err;
700
701 dwords_remaining--;
702 address += 8;
703 }
704
705 if (bytes_remaining)
706 {
707 uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
708 i = 0;
709
710 while (bytes_remaining > 0)
711 {
712 last_dword[i++] = *(buffer + bytes_written);
713 bytes_remaining--;
714 bytes_written++;
715 }
716
717 /* command */
718 cmd = FLASH_DWPG;
719 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
720
721 /* address */
722 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
723
724 /* data word 1 */
725 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
726 4, 1, last_dword);
727 bytes_written += 4;
728
729 /* data word 2 */
730 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
731 4, 1, last_dword + 4);
732 bytes_written += 4;
733
734 /* start programming cycle */
735 cmd = FLASH_DWPG | FLASH_WMS;
736 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
737
738 int err;
739 err = str7x_waitbusy(bank);
740 if (err != ERROR_OK)
741 return err;
742
743 err = str7x_result(bank);
744 if (err != ERROR_OK)
745 return err;
746 }
747
748 return ERROR_OK;
749 }
750
751 static int str7x_probe(struct flash_bank *bank)
752 {
753 return ERROR_OK;
754 }
755
756 #if 0
757 COMMAND_HANDLER(str7x_handle_part_id_command)
758 {
759 return ERROR_OK;
760 }
761 #endif
762
763 static int get_str7x_info(struct flash_bank *bank, char *buf, int buf_size)
764 {
765 snprintf(buf, buf_size, "str7x flash driver info");
766 /* STR7x flash doesn't support sector protection interrogation.
767 * FLASH_NVWPAR acts as a write only register; its read value
768 * doesn't reflect the actual protection state of the sectors.
769 */
770 LOG_WARNING("STR7x flash lock information might not be correct "
771 "due to hardware limitations.");
772 return ERROR_OK;
773 }
774
775 COMMAND_HANDLER(str7x_handle_disable_jtag_command)
776 {
777 struct target *target = NULL;
778 struct str7x_flash_bank *str7x_info = NULL;
779
780 uint32_t flash_cmd;
781 uint16_t ProtectionLevel = 0;
782 uint16_t ProtectionRegs;
783
784 if (CMD_ARGC < 1)
785 {
786 command_print(CMD_CTX, "str7x disable_jtag <bank>");
787 return ERROR_OK;
788 }
789
790 struct flash_bank *bank;
791 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
792 if (ERROR_OK != retval)
793 return retval;
794
795 str7x_info = bank->driver_priv;
796
797 target = bank->target;
798
799 if (target->state != TARGET_HALTED)
800 {
801 LOG_ERROR("Target not halted");
802 return ERROR_TARGET_NOT_HALTED;
803 }
804
805 /* first we get protection status */
806 uint32_t reg;
807 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &reg);
808
809 if (!(reg & str7x_info->disable_bit))
810 {
811 ProtectionLevel = 1;
812 }
813
814 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &reg);
815 ProtectionRegs = ~(reg >> 16);
816
817 while (((ProtectionRegs) != 0) && (ProtectionLevel < 16))
818 {
819 ProtectionRegs >>= 1;
820 ProtectionLevel++;
821 }
822
823 if (ProtectionLevel == 0)
824 {
825 flash_cmd = FLASH_SPR;
826 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
827 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
828 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), 0xFFFFFFFD);
829 flash_cmd = FLASH_SPR | FLASH_WMS;
830 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
831 }
832 else
833 {
834 flash_cmd = FLASH_SPR;
835 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
836 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
837 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0),
838 ~(1 << (15 + ProtectionLevel)));
839 flash_cmd = FLASH_SPR | FLASH_WMS;
840 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
841 }
842
843 return ERROR_OK;
844 }
845
846 static const struct command_registration str7x_exec_command_handlers[] = {
847 {
848 .name = "disable_jtag",
849 .handler = str7x_handle_disable_jtag_command,
850 .mode = COMMAND_EXEC,
851 .help = "disable jtag access",
852 },
853 COMMAND_REGISTRATION_DONE
854 };
855
856 static const struct command_registration str7x_command_handlers[] = {
857 {
858 .name = "str7x",
859 .mode = COMMAND_ANY,
860 .help = "str7x flash command group",
861 .chain = str7x_exec_command_handlers,
862 },
863 COMMAND_REGISTRATION_DONE
864 };
865
866 struct flash_driver str7x_flash = {
867 .name = "str7x",
868 .commands = str7x_command_handlers,
869 .flash_bank_command = str7x_flash_bank_command,
870 .erase = str7x_erase,
871 .protect = str7x_protect,
872 .write = str7x_write,
873 .read = default_flash_read,
874 .probe = str7x_probe,
875 .auto_probe = str7x_probe,
876 .erase_check = default_flash_blank_check,
877 .protect_check = str7x_protect_check,
878 .info = get_str7x_info,
879 };
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