3d8ce5423e96ee46e7a8375147f669a3f877b4c7
[openocd.git] / src / flash / nor / str7x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2010 √ėyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <target/arm.h>
33 #include <helper/binarybuffer.h>
34 #include <target/algorithm.h>
35
36 /* Flash registers */
37
38 #define FLASH_CR0 0x00000000
39 #define FLASH_CR1 0x00000004
40 #define FLASH_DR0 0x00000008
41 #define FLASH_DR1 0x0000000C
42 #define FLASH_AR 0x00000010
43 #define FLASH_ER 0x00000014
44 #define FLASH_NVWPAR 0x0000DFB0
45 #define FLASH_NVAPR0 0x0000DFB8
46 #define FLASH_NVAPR1 0x0000DFBC
47
48 /* FLASH_CR0 register bits */
49
50 #define FLASH_WMS 0x80000000
51 #define FLASH_SUSP 0x40000000
52 #define FLASH_WPG 0x20000000
53 #define FLASH_DWPG 0x10000000
54 #define FLASH_SER 0x08000000
55 #define FLASH_SPR 0x01000000
56 #define FLASH_BER 0x04000000
57 #define FLASH_MER 0x02000000
58 #define FLASH_LOCK 0x00000010
59 #define FLASH_BSYA1 0x00000004
60 #define FLASH_BSYA0 0x00000002
61
62 /* FLASH_CR1 register bits */
63
64 #define FLASH_B1S 0x02000000
65 #define FLASH_B0S 0x01000000
66 #define FLASH_B1F1 0x00020000
67 #define FLASH_B1F0 0x00010000
68 #define FLASH_B0F7 0x00000080
69 #define FLASH_B0F6 0x00000040
70 #define FLASH_B0F5 0x00000020
71 #define FLASH_B0F4 0x00000010
72 #define FLASH_B0F3 0x00000008
73 #define FLASH_B0F2 0x00000004
74 #define FLASH_B0F1 0x00000002
75 #define FLASH_B0F0 0x00000001
76
77 /* FLASH_ER register bits */
78
79 #define FLASH_WPF 0x00000100
80 #define FLASH_RESER 0x00000080
81 #define FLASH_SEQER 0x00000040
82 #define FLASH_10ER 0x00000008
83 #define FLASH_PGER 0x00000004
84 #define FLASH_ERER 0x00000002
85 #define FLASH_ERR 0x00000001
86
87
88 struct str7x_flash_bank {
89 uint32_t *sector_bits;
90 uint32_t disable_bit;
91 uint32_t busy_bits;
92 uint32_t register_base;
93 };
94
95 struct str7x_mem_layout {
96 uint32_t sector_start;
97 uint32_t sector_size;
98 uint32_t sector_bit;
99 };
100
101 enum str7x_status_codes {
102 STR7X_CMD_SUCCESS = 0,
103 STR7X_INVALID_COMMAND = 1,
104 STR7X_SRC_ADDR_ERROR = 2,
105 STR7X_DST_ADDR_ERROR = 3,
106 STR7X_SRC_ADDR_NOT_MAPPED = 4,
107 STR7X_DST_ADDR_NOT_MAPPED = 5,
108 STR7X_COUNT_ERROR = 6,
109 STR7X_INVALID_SECTOR = 7,
110 STR7X_SECTOR_NOT_BLANK = 8,
111 STR7X_SECTOR_NOT_PREPARED = 9,
112 STR7X_COMPARE_ERROR = 10,
113 STR7X_BUSY = 11
114 };
115
116 static struct str7x_mem_layout mem_layout_str7bank0[] = {
117 {0x00000000, 0x02000, 0x01},
118 {0x00002000, 0x02000, 0x02},
119 {0x00004000, 0x02000, 0x04},
120 {0x00006000, 0x02000, 0x08},
121 {0x00008000, 0x08000, 0x10},
122 {0x00010000, 0x10000, 0x20},
123 {0x00020000, 0x10000, 0x40},
124 {0x00030000, 0x10000, 0x80}
125 };
126
127 static struct str7x_mem_layout mem_layout_str7bank1[] = {
128 {0x00000000, 0x02000, 0x10000},
129 {0x00002000, 0x02000, 0x20000}
130 };
131
132 static int str7x_get_flash_adr(struct flash_bank *bank, uint32_t reg)
133 {
134 struct str7x_flash_bank *str7x_info = bank->driver_priv;
135 return str7x_info->register_base | reg;
136 }
137
138 static int str7x_build_block_list(struct flash_bank *bank)
139 {
140 struct str7x_flash_bank *str7x_info = bank->driver_priv;
141
142 int i;
143 int num_sectors;
144 int b0_sectors = 0, b1_sectors = 0;
145
146 switch (bank->size) {
147 case 16 * 1024:
148 b1_sectors = 2;
149 break;
150 case 64 * 1024:
151 b0_sectors = 5;
152 break;
153 case 128 * 1024:
154 b0_sectors = 6;
155 break;
156 case 256 * 1024:
157 b0_sectors = 8;
158 break;
159 default:
160 LOG_ERROR("BUG: unknown bank->size encountered");
161 exit(-1);
162 }
163
164 num_sectors = b0_sectors + b1_sectors;
165
166 bank->num_sectors = num_sectors;
167 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
168 str7x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
169
170 num_sectors = 0;
171
172 for (i = 0; i < b0_sectors; i++) {
173 bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
174 bank->sectors[num_sectors].size = mem_layout_str7bank0[i].sector_size;
175 bank->sectors[num_sectors].is_erased = -1;
176 /* the reset_init handler marks all the sectors unprotected,
177 * matching hardware after reset; keep the driver in sync
178 */
179 bank->sectors[num_sectors].is_protected = 0;
180 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
181 }
182
183 for (i = 0; i < b1_sectors; i++) {
184 bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
185 bank->sectors[num_sectors].size = mem_layout_str7bank1[i].sector_size;
186 bank->sectors[num_sectors].is_erased = -1;
187 /* the reset_init handler marks all the sectors unprotected,
188 * matching hardware after reset; keep the driver in sync
189 */
190 bank->sectors[num_sectors].is_protected = 0;
191 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank1[i].sector_bit;
192 }
193
194 return ERROR_OK;
195 }
196
197 /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
198 */
199 FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command)
200 {
201 struct str7x_flash_bank *str7x_info;
202
203 if (CMD_ARGC < 7)
204 return ERROR_COMMAND_SYNTAX_ERROR;
205
206 str7x_info = malloc(sizeof(struct str7x_flash_bank));
207 bank->driver_priv = str7x_info;
208
209 /* set default bits for str71x flash */
210 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA1 | FLASH_BSYA0);
211 str7x_info->disable_bit = (1 << 1);
212
213 if (strcmp(CMD_ARGV[6], "STR71x") == 0)
214 str7x_info->register_base = 0x40100000;
215 else if (strcmp(CMD_ARGV[6], "STR73x") == 0) {
216 str7x_info->register_base = 0x80100000;
217 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA0);
218 } else if (strcmp(CMD_ARGV[6], "STR75x") == 0) {
219 str7x_info->register_base = 0x20100000;
220 str7x_info->disable_bit = (1 << 0);
221 } else {
222 LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV[6]);
223 free(str7x_info);
224 return ERROR_FLASH_BANK_INVALID;
225 }
226
227 str7x_build_block_list(bank);
228
229 return ERROR_OK;
230 }
231
232 /* wait for flash to become idle or report errors.
233
234 FIX!!! what's the maximum timeout??? The documentation doesn't
235 state any maximum time.... by inspection it seems > 1000ms is to be
236 expected.
237
238 10000ms is long enough that it should cover anything, yet not
239 quite be equivalent to an infinite loop.
240
241 */
242 static int str7x_waitbusy(struct flash_bank *bank)
243 {
244 int err;
245 int i;
246 struct target *target = bank->target;
247 struct str7x_flash_bank *str7x_info = bank->driver_priv;
248
249 for (i = 0 ; i < 10000; i++) {
250 uint32_t retval;
251 err = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
252 if (err != ERROR_OK)
253 return err;
254
255 if ((retval & str7x_info->busy_bits) == 0)
256 return ERROR_OK;
257
258 alive_sleep(1);
259 }
260 LOG_ERROR("Timed out waiting for str7x flash");
261 return ERROR_FAIL;
262 }
263
264
265 static int str7x_result(struct flash_bank *bank)
266 {
267 struct target *target = bank->target;
268 uint32_t flash_flags;
269
270 int retval;
271 retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &flash_flags);
272 if (retval != ERROR_OK)
273 return retval;
274
275 if (flash_flags & FLASH_WPF) {
276 LOG_ERROR("str7x hw write protection set");
277 retval = ERROR_FAIL;
278 }
279 if (flash_flags & FLASH_RESER) {
280 LOG_ERROR("str7x suspended program erase not resumed");
281 retval = ERROR_FAIL;
282 }
283 if (flash_flags & FLASH_10ER) {
284 LOG_ERROR("str7x trying to set bit to 1 when it is already 0");
285 retval = ERROR_FAIL;
286 }
287 if (flash_flags & FLASH_PGER) {
288 LOG_ERROR("str7x program error");
289 retval = ERROR_FAIL;
290 }
291 if (flash_flags & FLASH_ERER) {
292 LOG_ERROR("str7x erase error");
293 retval = ERROR_FAIL;
294 }
295 if (retval == ERROR_OK) {
296 if (flash_flags & FLASH_ERR) {
297 /* this should always be set if one of the others are set... */
298 LOG_ERROR("str7x write operation failed / bad setup");
299 retval = ERROR_FAIL;
300 }
301 }
302
303 return retval;
304 }
305
306 static int str7x_protect_check(struct flash_bank *bank)
307 {
308 struct str7x_flash_bank *str7x_info = bank->driver_priv;
309 struct target *target = bank->target;
310
311 int i;
312 uint32_t flash_flags;
313
314 if (bank->target->state != TARGET_HALTED) {
315 LOG_ERROR("Target not halted");
316 return ERROR_TARGET_NOT_HALTED;
317 }
318
319 int retval;
320 retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &flash_flags);
321 if (retval != ERROR_OK)
322 return retval;
323
324 for (i = 0; i < bank->num_sectors; i++) {
325 if (flash_flags & str7x_info->sector_bits[i])
326 bank->sectors[i].is_protected = 0;
327 else
328 bank->sectors[i].is_protected = 1;
329 }
330
331 return ERROR_OK;
332 }
333
334 static int str7x_erase(struct flash_bank *bank, int first, int last)
335 {
336 struct str7x_flash_bank *str7x_info = bank->driver_priv;
337 struct target *target = bank->target;
338
339 int i;
340 uint32_t cmd;
341 uint32_t sectors = 0;
342 int err;
343
344 if (bank->target->state != TARGET_HALTED) {
345 LOG_ERROR("Target not halted");
346 return ERROR_TARGET_NOT_HALTED;
347 }
348
349 for (i = first; i <= last; i++)
350 sectors |= str7x_info->sector_bits[i];
351
352 LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
353
354 /* clear FLASH_ER register */
355 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
356 if (err != ERROR_OK)
357 return err;
358
359 cmd = FLASH_SER;
360 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
361 if (err != ERROR_OK)
362 return err;
363
364 cmd = sectors;
365 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
366 if (err != ERROR_OK)
367 return err;
368
369 cmd = FLASH_SER | FLASH_WMS;
370 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
371 if (err != ERROR_OK)
372 return err;
373
374 err = str7x_waitbusy(bank);
375 if (err != ERROR_OK)
376 return err;
377
378 err = str7x_result(bank);
379 if (err != ERROR_OK)
380 return err;
381
382 for (i = first; i <= last; i++)
383 bank->sectors[i].is_erased = 1;
384
385 return ERROR_OK;
386 }
387
388 static int str7x_protect(struct flash_bank *bank, int set, int first, int last)
389 {
390 struct str7x_flash_bank *str7x_info = bank->driver_priv;
391 struct target *target = bank->target;
392 int i;
393 uint32_t cmd;
394 uint32_t protect_blocks;
395
396 if (bank->target->state != TARGET_HALTED) {
397 LOG_ERROR("Target not halted");
398 return ERROR_TARGET_NOT_HALTED;
399 }
400
401 protect_blocks = 0xFFFFFFFF;
402
403 if (set) {
404 for (i = first; i <= last; i++)
405 protect_blocks &= ~(str7x_info->sector_bits[i]);
406 }
407
408 /* clear FLASH_ER register */
409 int err;
410 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
411 if (err != ERROR_OK)
412 return err;
413
414 cmd = FLASH_SPR;
415 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
416 if (err != ERROR_OK)
417 return err;
418
419 cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
420 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
421 if (err != ERROR_OK)
422 return err;
423
424 cmd = protect_blocks;
425 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
426 if (err != ERROR_OK)
427 return err;
428
429 cmd = FLASH_SPR | FLASH_WMS;
430 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
431 if (err != ERROR_OK)
432 return err;
433
434 err = str7x_waitbusy(bank);
435 if (err != ERROR_OK)
436 return err;
437
438 err = str7x_result(bank);
439 if (err != ERROR_OK)
440 return err;
441
442 return ERROR_OK;
443 }
444
445 static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer,
446 uint32_t offset, uint32_t count)
447 {
448 struct str7x_flash_bank *str7x_info = bank->driver_priv;
449 struct target *target = bank->target;
450 uint32_t buffer_size = 32768;
451 struct working_area *write_algorithm;
452 struct working_area *source;
453 uint32_t address = bank->base + offset;
454 struct reg_param reg_params[6];
455 struct arm_algorithm arm_algo;
456 int retval = ERROR_OK;
457
458 /* see contib/loaders/flash/str7x.s for src */
459
460 static const uint32_t str7x_flash_write_code[] = {
461 /* write: */
462 0xe3a04201, /* mov r4, #0x10000000 */
463 0xe5824000, /* str r4, [r2, #0x0] */
464 0xe5821010, /* str r1, [r2, #0x10] */
465 0xe4904004, /* ldr r4, [r0], #4 */
466 0xe5824008, /* str r4, [r2, #0x8] */
467 0xe4904004, /* ldr r4, [r0], #4 */
468 0xe582400c, /* str r4, [r2, #0xc] */
469 0xe3a04209, /* mov r4, #0x90000000 */
470 0xe5824000, /* str r4, [r2, #0x0] */
471 /* busy: */
472 0xe5924000, /* ldr r4, [r2, #0x0] */
473 0xe1140005, /* tst r4, r5 */
474 0x1afffffc, /* bne busy */
475 0xe5924014, /* ldr r4, [r2, #0x14] */
476 0xe31400ff, /* tst r4, #0xff */
477 0x03140c01, /* tsteq r4, #0x100 */
478 0x1a000002, /* bne exit */
479 0xe2811008, /* add r1, r1, #0x8 */
480 0xe2533001, /* subs r3, r3, #1 */
481 0x1affffec, /* bne write */
482 /* exit: */
483 0xeafffffe, /* b exit */
484 };
485
486 /* flash write code */
487 if (target_alloc_working_area_try(target, sizeof(str7x_flash_write_code),
488 &write_algorithm) != ERROR_OK) {
489 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
490 };
491
492 target_write_buffer(target, write_algorithm->address,
493 sizeof(str7x_flash_write_code),
494 (uint8_t *)str7x_flash_write_code);
495
496 /* memory buffer */
497 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
498 buffer_size /= 2;
499 if (buffer_size <= 256) {
500 /* we already allocated the writing code, but failed to get a
501 * buffer, free the algorithm */
502 target_free_working_area(target, write_algorithm);
503
504 LOG_WARNING("no large enough working area available, can't do block memory writes");
505 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
506 }
507 }
508
509 arm_algo.common_magic = ARM_COMMON_MAGIC;
510 arm_algo.core_mode = ARM_MODE_SVC;
511 arm_algo.core_state = ARM_STATE_ARM;
512
513 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
514 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
515 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
516 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
517 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
518 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
519
520 while (count > 0) {
521 uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
522
523 target_write_buffer(target, source->address, thisrun_count * 8, buffer);
524
525 buf_set_u32(reg_params[0].value, 0, 32, source->address);
526 buf_set_u32(reg_params[1].value, 0, 32, address);
527 buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
528 buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
529 buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
530
531 retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
532 write_algorithm->address,
533 write_algorithm->address + (sizeof(str7x_flash_write_code) - 4),
534 10000, &arm_algo);
535 if (retval != ERROR_OK)
536 break;
537
538 if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00) {
539 retval = str7x_result(bank);
540 break;
541 }
542
543 buffer += thisrun_count * 8;
544 address += thisrun_count * 8;
545 count -= thisrun_count;
546 }
547
548 target_free_working_area(target, source);
549 target_free_working_area(target, write_algorithm);
550
551 destroy_reg_param(&reg_params[0]);
552 destroy_reg_param(&reg_params[1]);
553 destroy_reg_param(&reg_params[2]);
554 destroy_reg_param(&reg_params[3]);
555 destroy_reg_param(&reg_params[4]);
556 destroy_reg_param(&reg_params[5]);
557
558 return retval;
559 }
560
561 static int str7x_write(struct flash_bank *bank, uint8_t *buffer,
562 uint32_t offset, uint32_t count)
563 {
564 struct target *target = bank->target;
565 uint32_t dwords_remaining = (count / 8);
566 uint32_t bytes_remaining = (count & 0x00000007);
567 uint32_t address = bank->base + offset;
568 uint32_t bytes_written = 0;
569 uint32_t cmd;
570 int retval;
571 uint32_t check_address = offset;
572 int i;
573
574 if (bank->target->state != TARGET_HALTED) {
575 LOG_ERROR("Target not halted");
576 return ERROR_TARGET_NOT_HALTED;
577 }
578
579 if (offset & 0x7) {
580 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset);
581 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
582 }
583
584 for (i = 0; i < bank->num_sectors; i++) {
585 uint32_t sec_start = bank->sectors[i].offset;
586 uint32_t sec_end = sec_start + bank->sectors[i].size;
587
588 /* check if destination falls within the current sector */
589 if ((check_address >= sec_start) && (check_address < sec_end)) {
590 /* check if destination ends in the current sector */
591 if (offset + count < sec_end)
592 check_address = offset + count;
593 else
594 check_address = sec_end;
595 }
596 }
597
598 if (check_address != offset + count)
599 return ERROR_FLASH_DST_OUT_OF_BANK;
600
601 /* clear FLASH_ER register */
602 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
603
604 /* multiple dwords (8-byte) to be programmed? */
605 if (dwords_remaining > 0) {
606 /* try using a block write */
607 retval = str7x_write_block(bank, buffer, offset, dwords_remaining);
608 if (retval != ERROR_OK) {
609 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
610 /* if block write failed (no sufficient working area),
611 * we use normal (slow) single dword accesses */
612 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
613 } else {
614 return retval;
615 }
616 } else {
617 buffer += dwords_remaining * 8;
618 address += dwords_remaining * 8;
619 dwords_remaining = 0;
620 }
621 }
622
623 while (dwords_remaining > 0) {
624 /* command */
625 cmd = FLASH_DWPG;
626 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
627
628 /* address */
629 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
630
631 /* data word 1 */
632 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
633 4, 1, buffer + bytes_written);
634 bytes_written += 4;
635
636 /* data word 2 */
637 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
638 4, 1, buffer + bytes_written);
639 bytes_written += 4;
640
641 /* start programming cycle */
642 cmd = FLASH_DWPG | FLASH_WMS;
643 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
644
645 int err;
646 err = str7x_waitbusy(bank);
647 if (err != ERROR_OK)
648 return err;
649
650 err = str7x_result(bank);
651 if (err != ERROR_OK)
652 return err;
653
654 dwords_remaining--;
655 address += 8;
656 }
657
658 if (bytes_remaining) {
659 uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
660
661 /* copy the last remaining bytes into the write buffer */
662 memcpy(last_dword, buffer+bytes_written, bytes_remaining);
663
664 /* command */
665 cmd = FLASH_DWPG;
666 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
667
668 /* address */
669 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
670
671 /* data word 1 */
672 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
673 4, 1, last_dword);
674
675 /* data word 2 */
676 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
677 4, 1, last_dword + 4);
678
679 /* start programming cycle */
680 cmd = FLASH_DWPG | FLASH_WMS;
681 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
682
683 int err;
684 err = str7x_waitbusy(bank);
685 if (err != ERROR_OK)
686 return err;
687
688 err = str7x_result(bank);
689 if (err != ERROR_OK)
690 return err;
691 }
692
693 return ERROR_OK;
694 }
695
696 static int str7x_probe(struct flash_bank *bank)
697 {
698 return ERROR_OK;
699 }
700
701 #if 0
702 COMMAND_HANDLER(str7x_handle_part_id_command)
703 {
704 return ERROR_OK;
705 }
706 #endif
707
708 static int get_str7x_info(struct flash_bank *bank, char *buf, int buf_size)
709 {
710 /* Setting the write protection on a sector is a permanent change but it
711 * can be disabled temporarily. FLASH_NVWPAR reflects the permanent
712 * protection state of the sectors, not the temporary.
713 */
714 snprintf(buf, buf_size, "STR7x flash protection info is only valid after a power cycle, "
715 "clearing the protection is only temporary and may not be reflected in the current "
716 "info returned.");
717 return ERROR_OK;
718 }
719
720 COMMAND_HANDLER(str7x_handle_disable_jtag_command)
721 {
722 struct target *target = NULL;
723 struct str7x_flash_bank *str7x_info = NULL;
724
725 uint32_t flash_cmd;
726 uint16_t ProtectionLevel = 0;
727 uint16_t ProtectionRegs;
728
729 if (CMD_ARGC < 1)
730 return ERROR_COMMAND_SYNTAX_ERROR;
731
732 struct flash_bank *bank;
733 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
734 if (ERROR_OK != retval)
735 return retval;
736
737 str7x_info = bank->driver_priv;
738
739 target = bank->target;
740
741 if (target->state != TARGET_HALTED) {
742 LOG_ERROR("Target not halted");
743 return ERROR_TARGET_NOT_HALTED;
744 }
745
746 /* first we get protection status */
747 uint32_t reg;
748 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &reg);
749
750 if (!(reg & str7x_info->disable_bit))
751 ProtectionLevel = 1;
752
753 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &reg);
754 ProtectionRegs = ~(reg >> 16);
755
756 while (((ProtectionRegs) != 0) && (ProtectionLevel < 16)) {
757 ProtectionRegs >>= 1;
758 ProtectionLevel++;
759 }
760
761 if (ProtectionLevel == 0) {
762 flash_cmd = FLASH_SPR;
763 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
764 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
765 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), 0xFFFFFFFD);
766 flash_cmd = FLASH_SPR | FLASH_WMS;
767 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
768 } else {
769 flash_cmd = FLASH_SPR;
770 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
771 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
772 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0),
773 ~(1 << (15 + ProtectionLevel)));
774 flash_cmd = FLASH_SPR | FLASH_WMS;
775 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
776 }
777
778 return ERROR_OK;
779 }
780
781 static const struct command_registration str7x_exec_command_handlers[] = {
782 {
783 .name = "disable_jtag",
784 .usage = "<bank>",
785 .handler = str7x_handle_disable_jtag_command,
786 .mode = COMMAND_EXEC,
787 .help = "disable jtag access",
788 },
789 COMMAND_REGISTRATION_DONE
790 };
791
792 static const struct command_registration str7x_command_handlers[] = {
793 {
794 .name = "str7x",
795 .mode = COMMAND_ANY,
796 .help = "str7x flash command group",
797 .usage = "",
798 .chain = str7x_exec_command_handlers,
799 },
800 COMMAND_REGISTRATION_DONE
801 };
802
803 struct flash_driver str7x_flash = {
804 .name = "str7x",
805 .commands = str7x_command_handlers,
806 .flash_bank_command = str7x_flash_bank_command,
807 .erase = str7x_erase,
808 .protect = str7x_protect,
809 .write = str7x_write,
810 .read = default_flash_read,
811 .probe = str7x_probe,
812 .auto_probe = str7x_probe,
813 .erase_check = default_flash_blank_check,
814 .protect_check = str7x_protect_check,
815 .info = get_str7x_info,
816 };