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[openocd.git] / src / flash / nor / str7x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2010 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <target/arm.h>
31 #include <helper/binarybuffer.h>
32 #include <target/algorithm.h>
33
34 /* Flash registers */
35
36 #define FLASH_CR0 0x00000000
37 #define FLASH_CR1 0x00000004
38 #define FLASH_DR0 0x00000008
39 #define FLASH_DR1 0x0000000C
40 #define FLASH_AR 0x00000010
41 #define FLASH_ER 0x00000014
42 #define FLASH_NVWPAR 0x0000DFB0
43 #define FLASH_NVAPR0 0x0000DFB8
44 #define FLASH_NVAPR1 0x0000DFBC
45
46 /* FLASH_CR0 register bits */
47
48 #define FLASH_WMS 0x80000000
49 #define FLASH_SUSP 0x40000000
50 #define FLASH_WPG 0x20000000
51 #define FLASH_DWPG 0x10000000
52 #define FLASH_SER 0x08000000
53 #define FLASH_SPR 0x01000000
54 #define FLASH_BER 0x04000000
55 #define FLASH_MER 0x02000000
56 #define FLASH_LOCK 0x00000010
57 #define FLASH_BSYA1 0x00000004
58 #define FLASH_BSYA0 0x00000002
59
60 /* FLASH_CR1 register bits */
61
62 #define FLASH_B1S 0x02000000
63 #define FLASH_B0S 0x01000000
64 #define FLASH_B1F1 0x00020000
65 #define FLASH_B1F0 0x00010000
66 #define FLASH_B0F7 0x00000080
67 #define FLASH_B0F6 0x00000040
68 #define FLASH_B0F5 0x00000020
69 #define FLASH_B0F4 0x00000010
70 #define FLASH_B0F3 0x00000008
71 #define FLASH_B0F2 0x00000004
72 #define FLASH_B0F1 0x00000002
73 #define FLASH_B0F0 0x00000001
74
75 /* FLASH_ER register bits */
76
77 #define FLASH_WPF 0x00000100
78 #define FLASH_RESER 0x00000080
79 #define FLASH_SEQER 0x00000040
80 #define FLASH_10ER 0x00000008
81 #define FLASH_PGER 0x00000004
82 #define FLASH_ERER 0x00000002
83 #define FLASH_ERR 0x00000001
84
85
86 struct str7x_flash_bank {
87 uint32_t *sector_bits;
88 uint32_t disable_bit;
89 uint32_t busy_bits;
90 uint32_t register_base;
91 };
92
93 struct str7x_mem_layout {
94 uint32_t sector_start;
95 uint32_t sector_size;
96 uint32_t sector_bit;
97 };
98
99 enum str7x_status_codes {
100 STR7X_CMD_SUCCESS = 0,
101 STR7X_INVALID_COMMAND = 1,
102 STR7X_SRC_ADDR_ERROR = 2,
103 STR7X_DST_ADDR_ERROR = 3,
104 STR7X_SRC_ADDR_NOT_MAPPED = 4,
105 STR7X_DST_ADDR_NOT_MAPPED = 5,
106 STR7X_COUNT_ERROR = 6,
107 STR7X_INVALID_SECTOR = 7,
108 STR7X_SECTOR_NOT_BLANK = 8,
109 STR7X_SECTOR_NOT_PREPARED = 9,
110 STR7X_COMPARE_ERROR = 10,
111 STR7X_BUSY = 11
112 };
113
114 static const struct str7x_mem_layout mem_layout_str7bank0[] = {
115 {0x00000000, 0x02000, 0x01},
116 {0x00002000, 0x02000, 0x02},
117 {0x00004000, 0x02000, 0x04},
118 {0x00006000, 0x02000, 0x08},
119 {0x00008000, 0x08000, 0x10},
120 {0x00010000, 0x10000, 0x20},
121 {0x00020000, 0x10000, 0x40},
122 {0x00030000, 0x10000, 0x80}
123 };
124
125 static const struct str7x_mem_layout mem_layout_str7bank1[] = {
126 {0x00000000, 0x02000, 0x10000},
127 {0x00002000, 0x02000, 0x20000}
128 };
129
130 static int str7x_get_flash_adr(struct flash_bank *bank, uint32_t reg)
131 {
132 struct str7x_flash_bank *str7x_info = bank->driver_priv;
133 return str7x_info->register_base | reg;
134 }
135
136 static int str7x_build_block_list(struct flash_bank *bank)
137 {
138 struct str7x_flash_bank *str7x_info = bank->driver_priv;
139
140 int i;
141 int num_sectors;
142 int b0_sectors = 0, b1_sectors = 0;
143
144 switch (bank->size) {
145 case 16 * 1024:
146 b1_sectors = 2;
147 break;
148 case 64 * 1024:
149 b0_sectors = 5;
150 break;
151 case 128 * 1024:
152 b0_sectors = 6;
153 break;
154 case 256 * 1024:
155 b0_sectors = 8;
156 break;
157 default:
158 LOG_ERROR("BUG: unknown bank->size encountered");
159 exit(-1);
160 }
161
162 num_sectors = b0_sectors + b1_sectors;
163
164 bank->num_sectors = num_sectors;
165 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
166 str7x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
167
168 num_sectors = 0;
169
170 for (i = 0; i < b0_sectors; i++) {
171 bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
172 bank->sectors[num_sectors].size = mem_layout_str7bank0[i].sector_size;
173 bank->sectors[num_sectors].is_erased = -1;
174 /* the reset_init handler marks all the sectors unprotected,
175 * matching hardware after reset; keep the driver in sync
176 */
177 bank->sectors[num_sectors].is_protected = 0;
178 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
179 }
180
181 for (i = 0; i < b1_sectors; i++) {
182 bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
183 bank->sectors[num_sectors].size = mem_layout_str7bank1[i].sector_size;
184 bank->sectors[num_sectors].is_erased = -1;
185 /* the reset_init handler marks all the sectors unprotected,
186 * matching hardware after reset; keep the driver in sync
187 */
188 bank->sectors[num_sectors].is_protected = 0;
189 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank1[i].sector_bit;
190 }
191
192 return ERROR_OK;
193 }
194
195 /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
196 */
197 FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command)
198 {
199 struct str7x_flash_bank *str7x_info;
200
201 if (CMD_ARGC < 7)
202 return ERROR_COMMAND_SYNTAX_ERROR;
203
204 str7x_info = malloc(sizeof(struct str7x_flash_bank));
205 bank->driver_priv = str7x_info;
206
207 /* set default bits for str71x flash */
208 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA1 | FLASH_BSYA0);
209 str7x_info->disable_bit = (1 << 1);
210
211 if (strcmp(CMD_ARGV[6], "STR71x") == 0)
212 str7x_info->register_base = 0x40100000;
213 else if (strcmp(CMD_ARGV[6], "STR73x") == 0) {
214 str7x_info->register_base = 0x80100000;
215 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA0);
216 } else if (strcmp(CMD_ARGV[6], "STR75x") == 0) {
217 str7x_info->register_base = 0x20100000;
218 str7x_info->disable_bit = (1 << 0);
219 } else {
220 LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV[6]);
221 free(str7x_info);
222 return ERROR_FLASH_BANK_INVALID;
223 }
224
225 str7x_build_block_list(bank);
226
227 return ERROR_OK;
228 }
229
230 /* wait for flash to become idle or report errors.
231
232 FIX!!! what's the maximum timeout??? The documentation doesn't
233 state any maximum time.... by inspection it seems > 1000ms is to be
234 expected.
235
236 10000ms is long enough that it should cover anything, yet not
237 quite be equivalent to an infinite loop.
238
239 */
240 static int str7x_waitbusy(struct flash_bank *bank)
241 {
242 int err;
243 int i;
244 struct target *target = bank->target;
245 struct str7x_flash_bank *str7x_info = bank->driver_priv;
246
247 for (i = 0 ; i < 10000; i++) {
248 uint32_t retval;
249 err = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
250 if (err != ERROR_OK)
251 return err;
252
253 if ((retval & str7x_info->busy_bits) == 0)
254 return ERROR_OK;
255
256 alive_sleep(1);
257 }
258 LOG_ERROR("Timed out waiting for str7x flash");
259 return ERROR_FAIL;
260 }
261
262
263 static int str7x_result(struct flash_bank *bank)
264 {
265 struct target *target = bank->target;
266 uint32_t flash_flags;
267
268 int retval;
269 retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &flash_flags);
270 if (retval != ERROR_OK)
271 return retval;
272
273 if (flash_flags & FLASH_WPF) {
274 LOG_ERROR("str7x hw write protection set");
275 retval = ERROR_FAIL;
276 }
277 if (flash_flags & FLASH_RESER) {
278 LOG_ERROR("str7x suspended program erase not resumed");
279 retval = ERROR_FAIL;
280 }
281 if (flash_flags & FLASH_10ER) {
282 LOG_ERROR("str7x trying to set bit to 1 when it is already 0");
283 retval = ERROR_FAIL;
284 }
285 if (flash_flags & FLASH_PGER) {
286 LOG_ERROR("str7x program error");
287 retval = ERROR_FAIL;
288 }
289 if (flash_flags & FLASH_ERER) {
290 LOG_ERROR("str7x erase error");
291 retval = ERROR_FAIL;
292 }
293 if (retval == ERROR_OK) {
294 if (flash_flags & FLASH_ERR) {
295 /* this should always be set if one of the others are set... */
296 LOG_ERROR("str7x write operation failed / bad setup");
297 retval = ERROR_FAIL;
298 }
299 }
300
301 return retval;
302 }
303
304 static int str7x_protect_check(struct flash_bank *bank)
305 {
306 struct str7x_flash_bank *str7x_info = bank->driver_priv;
307 struct target *target = bank->target;
308
309 int i;
310 uint32_t flash_flags;
311
312 if (bank->target->state != TARGET_HALTED) {
313 LOG_ERROR("Target not halted");
314 return ERROR_TARGET_NOT_HALTED;
315 }
316
317 int retval;
318 retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &flash_flags);
319 if (retval != ERROR_OK)
320 return retval;
321
322 for (i = 0; i < bank->num_sectors; i++) {
323 if (flash_flags & str7x_info->sector_bits[i])
324 bank->sectors[i].is_protected = 0;
325 else
326 bank->sectors[i].is_protected = 1;
327 }
328
329 return ERROR_OK;
330 }
331
332 static int str7x_erase(struct flash_bank *bank, int first, int last)
333 {
334 struct str7x_flash_bank *str7x_info = bank->driver_priv;
335 struct target *target = bank->target;
336
337 int i;
338 uint32_t cmd;
339 uint32_t sectors = 0;
340 int err;
341
342 if (bank->target->state != TARGET_HALTED) {
343 LOG_ERROR("Target not halted");
344 return ERROR_TARGET_NOT_HALTED;
345 }
346
347 for (i = first; i <= last; i++)
348 sectors |= str7x_info->sector_bits[i];
349
350 LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
351
352 /* clear FLASH_ER register */
353 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
354 if (err != ERROR_OK)
355 return err;
356
357 cmd = FLASH_SER;
358 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
359 if (err != ERROR_OK)
360 return err;
361
362 cmd = sectors;
363 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
364 if (err != ERROR_OK)
365 return err;
366
367 cmd = FLASH_SER | FLASH_WMS;
368 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
369 if (err != ERROR_OK)
370 return err;
371
372 err = str7x_waitbusy(bank);
373 if (err != ERROR_OK)
374 return err;
375
376 err = str7x_result(bank);
377 if (err != ERROR_OK)
378 return err;
379
380 for (i = first; i <= last; i++)
381 bank->sectors[i].is_erased = 1;
382
383 return ERROR_OK;
384 }
385
386 static int str7x_protect(struct flash_bank *bank, int set, int first, int last)
387 {
388 struct str7x_flash_bank *str7x_info = bank->driver_priv;
389 struct target *target = bank->target;
390 int i;
391 uint32_t cmd;
392 uint32_t protect_blocks;
393
394 if (bank->target->state != TARGET_HALTED) {
395 LOG_ERROR("Target not halted");
396 return ERROR_TARGET_NOT_HALTED;
397 }
398
399 protect_blocks = 0xFFFFFFFF;
400
401 if (set) {
402 for (i = first; i <= last; i++)
403 protect_blocks &= ~(str7x_info->sector_bits[i]);
404 }
405
406 /* clear FLASH_ER register */
407 int err;
408 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
409 if (err != ERROR_OK)
410 return err;
411
412 cmd = FLASH_SPR;
413 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
414 if (err != ERROR_OK)
415 return err;
416
417 cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
418 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
419 if (err != ERROR_OK)
420 return err;
421
422 cmd = protect_blocks;
423 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
424 if (err != ERROR_OK)
425 return err;
426
427 cmd = FLASH_SPR | FLASH_WMS;
428 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
429 if (err != ERROR_OK)
430 return err;
431
432 err = str7x_waitbusy(bank);
433 if (err != ERROR_OK)
434 return err;
435
436 err = str7x_result(bank);
437 if (err != ERROR_OK)
438 return err;
439
440 return ERROR_OK;
441 }
442
443 static int str7x_write_block(struct flash_bank *bank, const uint8_t *buffer,
444 uint32_t offset, uint32_t count)
445 {
446 struct str7x_flash_bank *str7x_info = bank->driver_priv;
447 struct target *target = bank->target;
448 uint32_t buffer_size = 32768;
449 struct working_area *write_algorithm;
450 struct working_area *source;
451 uint32_t address = bank->base + offset;
452 struct reg_param reg_params[6];
453 struct arm_algorithm arm_algo;
454 int retval = ERROR_OK;
455
456 /* see contib/loaders/flash/str7x.s for src */
457
458 static const uint32_t str7x_flash_write_code[] = {
459 /* write: */
460 0xe3a04201, /* mov r4, #0x10000000 */
461 0xe5824000, /* str r4, [r2, #0x0] */
462 0xe5821010, /* str r1, [r2, #0x10] */
463 0xe4904004, /* ldr r4, [r0], #4 */
464 0xe5824008, /* str r4, [r2, #0x8] */
465 0xe4904004, /* ldr r4, [r0], #4 */
466 0xe582400c, /* str r4, [r2, #0xc] */
467 0xe3a04209, /* mov r4, #0x90000000 */
468 0xe5824000, /* str r4, [r2, #0x0] */
469 /* busy: */
470 0xe5924000, /* ldr r4, [r2, #0x0] */
471 0xe1140005, /* tst r4, r5 */
472 0x1afffffc, /* bne busy */
473 0xe5924014, /* ldr r4, [r2, #0x14] */
474 0xe31400ff, /* tst r4, #0xff */
475 0x03140c01, /* tsteq r4, #0x100 */
476 0x1a000002, /* bne exit */
477 0xe2811008, /* add r1, r1, #0x8 */
478 0xe2533001, /* subs r3, r3, #1 */
479 0x1affffec, /* bne write */
480 /* exit: */
481 0xeafffffe, /* b exit */
482 };
483
484 /* flash write code */
485 if (target_alloc_working_area_try(target, sizeof(str7x_flash_write_code),
486 &write_algorithm) != ERROR_OK) {
487 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
488 }
489
490 uint8_t code[sizeof(str7x_flash_write_code)];
491 target_buffer_set_u32_array(target, code, ARRAY_SIZE(str7x_flash_write_code),
492 str7x_flash_write_code);
493 target_write_buffer(target, write_algorithm->address, sizeof(code), code);
494
495 /* memory buffer */
496 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
497 buffer_size /= 2;
498 if (buffer_size <= 256) {
499 /* we already allocated the writing code, but failed to get a
500 * buffer, free the algorithm */
501 target_free_working_area(target, write_algorithm);
502
503 LOG_WARNING("no large enough working area available, can't do block memory writes");
504 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
505 }
506 }
507
508 arm_algo.common_magic = ARM_COMMON_MAGIC;
509 arm_algo.core_mode = ARM_MODE_SVC;
510 arm_algo.core_state = ARM_STATE_ARM;
511
512 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
513 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
514 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
515 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
516 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
517 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
518
519 while (count > 0) {
520 uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
521
522 target_write_buffer(target, source->address, thisrun_count * 8, buffer);
523
524 buf_set_u32(reg_params[0].value, 0, 32, source->address);
525 buf_set_u32(reg_params[1].value, 0, 32, address);
526 buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
527 buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
528 buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
529
530 retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
531 write_algorithm->address,
532 write_algorithm->address + (sizeof(str7x_flash_write_code) - 4),
533 10000, &arm_algo);
534 if (retval != ERROR_OK)
535 break;
536
537 if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00) {
538 retval = str7x_result(bank);
539 break;
540 }
541
542 buffer += thisrun_count * 8;
543 address += thisrun_count * 8;
544 count -= thisrun_count;
545 }
546
547 target_free_working_area(target, source);
548 target_free_working_area(target, write_algorithm);
549
550 destroy_reg_param(&reg_params[0]);
551 destroy_reg_param(&reg_params[1]);
552 destroy_reg_param(&reg_params[2]);
553 destroy_reg_param(&reg_params[3]);
554 destroy_reg_param(&reg_params[4]);
555 destroy_reg_param(&reg_params[5]);
556
557 return retval;
558 }
559
560 static int str7x_write(struct flash_bank *bank, const uint8_t *buffer,
561 uint32_t offset, uint32_t count)
562 {
563 struct target *target = bank->target;
564 uint32_t dwords_remaining = (count / 8);
565 uint32_t bytes_remaining = (count & 0x00000007);
566 uint32_t address = bank->base + offset;
567 uint32_t bytes_written = 0;
568 uint32_t cmd;
569 int retval;
570 uint32_t check_address = offset;
571 int i;
572
573 if (bank->target->state != TARGET_HALTED) {
574 LOG_ERROR("Target not halted");
575 return ERROR_TARGET_NOT_HALTED;
576 }
577
578 if (offset & 0x7) {
579 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset);
580 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
581 }
582
583 for (i = 0; i < bank->num_sectors; i++) {
584 uint32_t sec_start = bank->sectors[i].offset;
585 uint32_t sec_end = sec_start + bank->sectors[i].size;
586
587 /* check if destination falls within the current sector */
588 if ((check_address >= sec_start) && (check_address < sec_end)) {
589 /* check if destination ends in the current sector */
590 if (offset + count < sec_end)
591 check_address = offset + count;
592 else
593 check_address = sec_end;
594 }
595 }
596
597 if (check_address != offset + count)
598 return ERROR_FLASH_DST_OUT_OF_BANK;
599
600 /* clear FLASH_ER register */
601 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
602
603 /* multiple dwords (8-byte) to be programmed? */
604 if (dwords_remaining > 0) {
605 /* try using a block write */
606 retval = str7x_write_block(bank, buffer, offset, dwords_remaining);
607 if (retval != ERROR_OK) {
608 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
609 /* if block write failed (no sufficient working area),
610 * we use normal (slow) single dword accesses */
611 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
612 } else {
613 return retval;
614 }
615 } else {
616 buffer += dwords_remaining * 8;
617 address += dwords_remaining * 8;
618 dwords_remaining = 0;
619 }
620 }
621
622 while (dwords_remaining > 0) {
623 /* command */
624 cmd = FLASH_DWPG;
625 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
626
627 /* address */
628 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
629
630 /* data word 1 */
631 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
632 4, 1, buffer + bytes_written);
633 bytes_written += 4;
634
635 /* data word 2 */
636 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
637 4, 1, buffer + bytes_written);
638 bytes_written += 4;
639
640 /* start programming cycle */
641 cmd = FLASH_DWPG | FLASH_WMS;
642 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
643
644 int err;
645 err = str7x_waitbusy(bank);
646 if (err != ERROR_OK)
647 return err;
648
649 err = str7x_result(bank);
650 if (err != ERROR_OK)
651 return err;
652
653 dwords_remaining--;
654 address += 8;
655 }
656
657 if (bytes_remaining) {
658 uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
659
660 /* copy the last remaining bytes into the write buffer */
661 memcpy(last_dword, buffer+bytes_written, bytes_remaining);
662
663 /* command */
664 cmd = FLASH_DWPG;
665 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
666
667 /* address */
668 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
669
670 /* data word 1 */
671 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
672 4, 1, last_dword);
673
674 /* data word 2 */
675 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
676 4, 1, last_dword + 4);
677
678 /* start programming cycle */
679 cmd = FLASH_DWPG | FLASH_WMS;
680 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
681
682 int err;
683 err = str7x_waitbusy(bank);
684 if (err != ERROR_OK)
685 return err;
686
687 err = str7x_result(bank);
688 if (err != ERROR_OK)
689 return err;
690 }
691
692 return ERROR_OK;
693 }
694
695 static int str7x_probe(struct flash_bank *bank)
696 {
697 return ERROR_OK;
698 }
699
700 #if 0
701 COMMAND_HANDLER(str7x_handle_part_id_command)
702 {
703 return ERROR_OK;
704 }
705 #endif
706
707 static int get_str7x_info(struct flash_bank *bank, char *buf, int buf_size)
708 {
709 /* Setting the write protection on a sector is a permanent change but it
710 * can be disabled temporarily. FLASH_NVWPAR reflects the permanent
711 * protection state of the sectors, not the temporary.
712 */
713 snprintf(buf, buf_size, "STR7x flash protection info is only valid after a power cycle, "
714 "clearing the protection is only temporary and may not be reflected in the current "
715 "info returned.");
716 return ERROR_OK;
717 }
718
719 COMMAND_HANDLER(str7x_handle_disable_jtag_command)
720 {
721 struct target *target = NULL;
722 struct str7x_flash_bank *str7x_info = NULL;
723
724 uint32_t flash_cmd;
725 uint16_t ProtectionLevel = 0;
726 uint16_t ProtectionRegs;
727
728 if (CMD_ARGC < 1)
729 return ERROR_COMMAND_SYNTAX_ERROR;
730
731 struct flash_bank *bank;
732 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
733 if (ERROR_OK != retval)
734 return retval;
735
736 str7x_info = bank->driver_priv;
737
738 target = bank->target;
739
740 if (target->state != TARGET_HALTED) {
741 LOG_ERROR("Target not halted");
742 return ERROR_TARGET_NOT_HALTED;
743 }
744
745 /* first we get protection status */
746 uint32_t reg;
747 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &reg);
748
749 if (!(reg & str7x_info->disable_bit))
750 ProtectionLevel = 1;
751
752 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &reg);
753 ProtectionRegs = ~(reg >> 16);
754
755 while (((ProtectionRegs) != 0) && (ProtectionLevel < 16)) {
756 ProtectionRegs >>= 1;
757 ProtectionLevel++;
758 }
759
760 if (ProtectionLevel == 0) {
761 flash_cmd = FLASH_SPR;
762 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
763 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
764 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), 0xFFFFFFFD);
765 flash_cmd = FLASH_SPR | FLASH_WMS;
766 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
767 } else {
768 flash_cmd = FLASH_SPR;
769 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
770 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
771 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0),
772 ~(1 << (15 + ProtectionLevel)));
773 flash_cmd = FLASH_SPR | FLASH_WMS;
774 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
775 }
776
777 return ERROR_OK;
778 }
779
780 static const struct command_registration str7x_exec_command_handlers[] = {
781 {
782 .name = "disable_jtag",
783 .usage = "<bank>",
784 .handler = str7x_handle_disable_jtag_command,
785 .mode = COMMAND_EXEC,
786 .help = "disable jtag access",
787 },
788 COMMAND_REGISTRATION_DONE
789 };
790
791 static const struct command_registration str7x_command_handlers[] = {
792 {
793 .name = "str7x",
794 .mode = COMMAND_ANY,
795 .help = "str7x flash command group",
796 .usage = "",
797 .chain = str7x_exec_command_handlers,
798 },
799 COMMAND_REGISTRATION_DONE
800 };
801
802 struct flash_driver str7x_flash = {
803 .name = "str7x",
804 .commands = str7x_command_handlers,
805 .flash_bank_command = str7x_flash_bank_command,
806 .erase = str7x_erase,
807 .protect = str7x_protect,
808 .write = str7x_write,
809 .read = default_flash_read,
810 .probe = str7x_probe,
811 .auto_probe = str7x_probe,
812 .erase_check = default_flash_blank_check,
813 .protect_check = str7x_protect_check,
814 .info = get_str7x_info,
815 };
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