Fix usage of timeval_ms()
[openocd.git] / src / flash / nor / stmsmi.c
1 /***************************************************************************
2 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
17
18 /* STM Serial Memory Interface (SMI) controller is a SPI bus controller
19 * specifically designed for SPI memories.
20 * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
21 * Two working modes are available:
22 * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
23 * on the bus.
24 * - HW mode: the SPI but is under SMI control. Memory content is directly
25 * accessible in CPU memory space. CPU can read, write and execute memory
26 * content. */
27
28 /* ATTENTION:
29 * To have flash memory mapped in CPU memory space, the SMI controller
30 * have to be in "HW mode". This requires following constraints:
31 * 1) The command "reset init" have to initialize SMI controller and put
32 * it in HW mode;
33 * 2) every command in this file have to return to prompt in HW mode. */
34
35 #ifdef HAVE_CONFIG_H
36 #include "config.h"
37 #endif
38
39 #include "imp.h"
40 #include "spi.h"
41 #include <jtag/jtag.h>
42 #include <helper/time_support.h>
43
44 #define SMI_READ_REG(a) (_SMI_READ_REG(a))
45 #define _SMI_READ_REG(a) \
46 { \
47 int __a; \
48 uint32_t __v; \
49 \
50 __a = target_read_u32(target, io_base + (a), &__v); \
51 if (__a != ERROR_OK) \
52 return __a; \
53 __v; \
54 }
55
56 #define SMI_WRITE_REG(a, v) \
57 { \
58 int __r; \
59 \
60 __r = target_write_u32(target, io_base + (a), (v)); \
61 if (__r != ERROR_OK) \
62 return __r; \
63 }
64
65 #define SMI_POLL_TFF(timeout) \
66 { \
67 int __r; \
68 \
69 __r = poll_tff(target, io_base, timeout); \
70 if (__r != ERROR_OK) \
71 return __r; \
72 }
73
74 #define SMI_SET_SW_MODE() SMI_WRITE_REG(SMI_CR1, \
75 SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
76 #define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
77 (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
78 #define SMI_SET_HW_MODE() SMI_WRITE_REG(SMI_CR1, \
79 SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
80 #define SMI_CLEAR_TFF() SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
81
82 #define SMI_BANK_SIZE (0x01000000)
83
84 #define SMI_CR1 (0x00) /* Control register 1 */
85 #define SMI_CR2 (0x04) /* Control register 2 */
86 #define SMI_SR (0x08) /* Status register */
87 #define SMI_TR (0x0c) /* TX */
88 #define SMI_RR (0x10) /* RX */
89
90 /* fields in SMI_CR1 */
91 #define SMI_SW_MODE 0x10000000 /* set to enable SW Mode */
92 #define SMI_WB_MODE 0x20000000 /* Write Burst Mode */
93
94 /* fields in SMI_CR2 */
95 #define SMI_TX_LEN_1 0x00000001 /* data length = 1 byte */
96 #define SMI_TX_LEN_4 0x00000004 /* data length = 4 byte */
97 #define SMI_RX_LEN_3 0x00000030 /* data length = 3 byte */
98 #define SMI_SEND 0x00000080 /* Send data */
99 #define SMI_RSR 0x00000400 /* reads status reg */
100 #define SMI_WE 0x00000800 /* Write Enable */
101 #define SMI_SEL_BANK0 0x00000000 /* Select Bank0 */
102 #define SMI_SEL_BANK1 0x00001000 /* Select Bank1 */
103 #define SMI_SEL_BANK2 0x00002000 /* Select Bank2 */
104 #define SMI_SEL_BANK3 0x00003000 /* Select Bank3 */
105
106 /* fields in SMI_SR */
107 #define SMI_TFF 0x00000100 /* Transfer Finished Flag */
108
109 /* Commands */
110 #define SMI_READ_ID 0x0000009F /* Read Flash Identification */
111
112 /* Timeout in ms */
113 #define SMI_CMD_TIMEOUT (100)
114 #define SMI_PROBE_TIMEOUT (100)
115 #define SMI_MAX_TIMEOUT (3000)
116
117 struct stmsmi_flash_bank {
118 int probed;
119 uint32_t io_base;
120 uint32_t bank_num;
121 const struct flash_device *dev;
122 };
123
124 struct stmsmi_target {
125 char *name;
126 uint32_t tap_idcode;
127 uint32_t smi_base;
128 uint32_t io_base;
129 };
130
131 static const struct stmsmi_target target_devices[] = {
132 /* name, tap_idcode, smi_base, io_base */
133 { "SPEAr3xx/6xx", 0x07926041, 0xf8000000, 0xfc000000 },
134 { "STR75x", 0x4f1f0041, 0x80000000, 0x90000000 },
135 { NULL, 0, 0, 0 }
136 };
137
138 FLASH_BANK_COMMAND_HANDLER(stmsmi_flash_bank_command)
139 {
140 struct stmsmi_flash_bank *stmsmi_info;
141
142 LOG_DEBUG("%s", __func__);
143
144 if (CMD_ARGC < 6)
145 return ERROR_COMMAND_SYNTAX_ERROR;
146
147 stmsmi_info = malloc(sizeof(struct stmsmi_flash_bank));
148 if (stmsmi_info == NULL) {
149 LOG_ERROR("not enough memory");
150 return ERROR_FAIL;
151 }
152
153 bank->driver_priv = stmsmi_info;
154 stmsmi_info->probed = 0;
155
156 return ERROR_OK;
157 }
158
159 /* Poll transmit finished flag */
160 /* timeout in ms */
161 static int poll_tff(struct target *target, uint32_t io_base, int timeout)
162 {
163 int64_t endtime;
164
165 if (SMI_READ_REG(SMI_SR) & SMI_TFF)
166 return ERROR_OK;
167
168 endtime = timeval_ms() + timeout;
169 do {
170 alive_sleep(1);
171 if (SMI_READ_REG(SMI_SR) & SMI_TFF)
172 return ERROR_OK;
173 } while (timeval_ms() < endtime);
174
175 LOG_ERROR("Timeout while polling TFF");
176 return ERROR_FLASH_OPERATION_FAILED;
177 }
178
179 /* Read the status register of the external SPI flash chip.
180 * The operation is triggered by setting SMI_RSR bit.
181 * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
182 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
183 {
184 struct target *target = bank->target;
185 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
186 uint32_t io_base = stmsmi_info->io_base;
187
188 /* clear transmit finished flag */
189 SMI_CLEAR_TFF();
190
191 /* Read status */
192 SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_RSR);
193
194 /* Poll transmit finished flag */
195 SMI_POLL_TFF(SMI_CMD_TIMEOUT);
196
197 /* clear transmit finished flag */
198 SMI_CLEAR_TFF();
199
200 *status = SMI_READ_REG(SMI_SR) & 0x0000ffff;
201
202 /* clean-up SMI_CR2 */
203 SMI_WRITE_REG(SMI_CR2, 0); /* AB: Required ? */
204
205 return ERROR_OK;
206 }
207
208 /* check for WIP (write in progress) bit in status register */
209 /* timeout in ms */
210 static int wait_till_ready(struct flash_bank *bank, int timeout)
211 {
212 uint32_t status;
213 int retval;
214 int64_t endtime;
215
216 endtime = timeval_ms() + timeout;
217 do {
218 /* read flash status register */
219 retval = read_status_reg(bank, &status);
220 if (retval != ERROR_OK)
221 return retval;
222
223 if ((status & SPIFLASH_BSY_BIT) == 0)
224 return ERROR_OK;
225 alive_sleep(1);
226 } while (timeval_ms() < endtime);
227
228 LOG_ERROR("timeout");
229 return ERROR_FAIL;
230 }
231
232 /* Send "write enable" command to SPI flash chip.
233 * The operation is triggered by setting SMI_WE bit, and SMI sends
234 * the proper SPI command (0x06) */
235 static int smi_write_enable(struct flash_bank *bank)
236 {
237 struct target *target = bank->target;
238 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
239 uint32_t io_base = stmsmi_info->io_base;
240 uint32_t status;
241 int retval;
242
243 /* Enter in HW mode */
244 SMI_SET_HW_MODE(); /* AB: is this correct ?*/
245
246 /* clear transmit finished flag */
247 SMI_CLEAR_TFF();
248
249 /* Send write enable command */
250 SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_WE);
251
252 /* Poll transmit finished flag */
253 SMI_POLL_TFF(SMI_CMD_TIMEOUT);
254
255 /* read flash status register */
256 retval = read_status_reg(bank, &status);
257 if (retval != ERROR_OK)
258 return retval;
259
260 /* Check write enabled */
261 if ((status & SPIFLASH_WE_BIT) == 0) {
262 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
263 return ERROR_FAIL;
264 }
265
266 return ERROR_OK;
267 }
268
269 static uint32_t erase_command(struct stmsmi_flash_bank *stmsmi_info,
270 uint32_t offset)
271 {
272 union {
273 uint32_t command;
274 uint8_t x[4];
275 } cmd;
276
277 cmd.x[0] = stmsmi_info->dev->erase_cmd;
278 cmd.x[1] = offset >> 16;
279 cmd.x[2] = offset >> 8;
280 cmd.x[3] = offset;
281
282 return cmd.command;
283 }
284
285 static int smi_erase_sector(struct flash_bank *bank, int sector)
286 {
287 struct target *target = bank->target;
288 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
289 uint32_t io_base = stmsmi_info->io_base;
290 uint32_t cmd;
291 int retval;
292
293 retval = smi_write_enable(bank);
294 if (retval != ERROR_OK)
295 return retval;
296
297 /* Switch to SW mode to send sector erase command */
298 SMI_SET_SW_MODE();
299
300 /* clear transmit finished flag */
301 SMI_CLEAR_TFF();
302
303 /* send SPI command "block erase" */
304 cmd = erase_command(stmsmi_info, bank->sectors[sector].offset);
305 SMI_WRITE_REG(SMI_TR, cmd);
306 SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_SEND | SMI_TX_LEN_4);
307
308 /* Poll transmit finished flag */
309 SMI_POLL_TFF(SMI_CMD_TIMEOUT);
310
311 /* poll WIP for end of self timed Sector Erase cycle */
312 retval = wait_till_ready(bank, SMI_MAX_TIMEOUT);
313 if (retval != ERROR_OK)
314 return retval;
315
316 return ERROR_OK;
317 }
318
319 static int stmsmi_erase(struct flash_bank *bank, int first, int last)
320 {
321 struct target *target = bank->target;
322 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
323 uint32_t io_base = stmsmi_info->io_base;
324 int retval = ERROR_OK;
325 int sector;
326
327 LOG_DEBUG("%s: from sector %d to sector %d", __func__, first, last);
328
329 if (target->state != TARGET_HALTED) {
330 LOG_ERROR("Target not halted");
331 return ERROR_TARGET_NOT_HALTED;
332 }
333
334 if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
335 LOG_ERROR("Flash sector invalid");
336 return ERROR_FLASH_SECTOR_INVALID;
337 }
338
339 if (!(stmsmi_info->probed)) {
340 LOG_ERROR("Flash bank not probed");
341 return ERROR_FLASH_BANK_NOT_PROBED;
342 }
343
344 for (sector = first; sector <= last; sector++) {
345 if (bank->sectors[sector].is_protected) {
346 LOG_ERROR("Flash sector %d protected", sector);
347 return ERROR_FAIL;
348 }
349 }
350
351 for (sector = first; sector <= last; sector++) {
352 retval = smi_erase_sector(bank, sector);
353 if (retval != ERROR_OK)
354 break;
355 keep_alive();
356 }
357
358 /* Switch to HW mode before return to prompt */
359 SMI_SET_HW_MODE();
360 return retval;
361 }
362
363 static int stmsmi_protect(struct flash_bank *bank, int set,
364 int first, int last)
365 {
366 int sector;
367
368 for (sector = first; sector <= last; sector++)
369 bank->sectors[sector].is_protected = set;
370 return ERROR_OK;
371 }
372
373 static int smi_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
374 uint32_t address, uint32_t len)
375 {
376 struct target *target = bank->target;
377 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
378 uint32_t io_base = stmsmi_info->io_base;
379 int retval;
380
381 LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
382 __func__, address, len);
383
384 retval = smi_write_enable(bank);
385 if (retval != ERROR_OK)
386 return retval;
387
388 /* HW mode, write burst mode */
389 SMI_SET_HWWB_MODE();
390
391 retval = target_write_buffer(target, address, len, buffer);
392 if (retval != ERROR_OK)
393 return retval;
394
395 return ERROR_OK;
396 }
397
398 static int stmsmi_write(struct flash_bank *bank, const uint8_t *buffer,
399 uint32_t offset, uint32_t count)
400 {
401 struct target *target = bank->target;
402 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
403 uint32_t io_base = stmsmi_info->io_base;
404 uint32_t cur_count, page_size, page_offset;
405 int sector;
406 int retval = ERROR_OK;
407
408 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
409 __func__, offset, count);
410
411 if (target->state != TARGET_HALTED) {
412 LOG_ERROR("Target not halted");
413 return ERROR_TARGET_NOT_HALTED;
414 }
415
416 if (offset + count > stmsmi_info->dev->size_in_bytes) {
417 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
418 count = stmsmi_info->dev->size_in_bytes - offset;
419 }
420
421 /* Check sector protection */
422 for (sector = 0; sector < bank->num_sectors; sector++) {
423 /* Start offset in or before this sector? */
424 /* End offset in or behind this sector? */
425 if ((offset <
426 (bank->sectors[sector].offset + bank->sectors[sector].size))
427 && ((offset + count - 1) >= bank->sectors[sector].offset)
428 && bank->sectors[sector].is_protected) {
429 LOG_ERROR("Flash sector %d protected", sector);
430 return ERROR_FAIL;
431 }
432 }
433
434 page_size = stmsmi_info->dev->pagesize;
435
436 /* unaligned buffer head */
437 if (count > 0 && (offset & 3) != 0) {
438 cur_count = 4 - (offset & 3);
439 if (cur_count > count)
440 cur_count = count;
441 retval = smi_write_buffer(bank, buffer, bank->base + offset,
442 cur_count);
443 if (retval != ERROR_OK)
444 goto err;
445 offset += cur_count;
446 buffer += cur_count;
447 count -= cur_count;
448 }
449
450 page_offset = offset % page_size;
451 /* central part, aligned words */
452 while (count >= 4) {
453 /* clip block at page boundary */
454 if (page_offset + count > page_size)
455 cur_count = page_size - page_offset;
456 else
457 cur_count = count & ~3;
458
459 retval = smi_write_buffer(bank, buffer, bank->base + offset,
460 cur_count);
461 if (retval != ERROR_OK)
462 goto err;
463
464 page_offset = 0;
465 buffer += cur_count;
466 offset += cur_count;
467 count -= cur_count;
468
469 keep_alive();
470 }
471
472 /* buffer tail */
473 if (count > 0)
474 retval = smi_write_buffer(bank, buffer, bank->base + offset, count);
475
476 err:
477 /* Switch to HW mode before return to prompt */
478 SMI_SET_HW_MODE();
479 return retval;
480 }
481
482 /* Return ID of flash device */
483 /* On exit, SW mode is kept */
484 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
485 {
486 struct target *target = bank->target;
487 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
488 uint32_t io_base = stmsmi_info->io_base;
489 int retval;
490
491 if (target->state != TARGET_HALTED) {
492 LOG_ERROR("Target not halted");
493 return ERROR_TARGET_NOT_HALTED;
494 }
495
496 /* poll WIP */
497 retval = wait_till_ready(bank, SMI_PROBE_TIMEOUT);
498 if (retval != ERROR_OK)
499 return retval;
500
501 /* enter in SW mode */
502 SMI_SET_SW_MODE();
503
504 /* clear transmit finished flag */
505 SMI_CLEAR_TFF();
506
507 /* Send SPI command "read ID" */
508 SMI_WRITE_REG(SMI_TR, SMI_READ_ID);
509 SMI_WRITE_REG(SMI_CR2,
510 stmsmi_info->bank_num | SMI_SEND | SMI_RX_LEN_3 | SMI_TX_LEN_1);
511
512 /* Poll transmit finished flag */
513 SMI_POLL_TFF(SMI_CMD_TIMEOUT);
514
515 /* clear transmit finished flag */
516 SMI_CLEAR_TFF();
517
518 /* read ID from Receive Register */
519 *id = SMI_READ_REG(SMI_RR) & 0x00ffffff;
520 return ERROR_OK;
521 }
522
523 static int stmsmi_probe(struct flash_bank *bank)
524 {
525 struct target *target = bank->target;
526 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
527 uint32_t io_base;
528 struct flash_sector *sectors;
529 uint32_t id = 0; /* silence uninitialized warning */
530 const struct stmsmi_target *target_device;
531 int retval;
532
533 if (stmsmi_info->probed)
534 free(bank->sectors);
535 stmsmi_info->probed = 0;
536
537 for (target_device = target_devices ; target_device->name ; ++target_device)
538 if (target_device->tap_idcode == target->tap->idcode)
539 break;
540 if (!target_device->name) {
541 LOG_ERROR("Device ID 0x%" PRIx32 " is not known as SMI capable",
542 target->tap->idcode);
543 return ERROR_FAIL;
544 }
545
546 switch (bank->base - target_device->smi_base) {
547 case 0:
548 stmsmi_info->bank_num = SMI_SEL_BANK0;
549 break;
550 case SMI_BANK_SIZE:
551 stmsmi_info->bank_num = SMI_SEL_BANK1;
552 break;
553 case 2*SMI_BANK_SIZE:
554 stmsmi_info->bank_num = SMI_SEL_BANK2;
555 break;
556 case 3*SMI_BANK_SIZE:
557 stmsmi_info->bank_num = SMI_SEL_BANK3;
558 break;
559 default:
560 LOG_ERROR("Invalid SMI base address 0x%" PRIx32, bank->base);
561 return ERROR_FAIL;
562 }
563 io_base = target_device->io_base;
564 stmsmi_info->io_base = io_base;
565
566 LOG_DEBUG("Valid SMI on device %s at address 0x%" PRIx32,
567 target_device->name, bank->base);
568
569 /* read and decode flash ID; returns in SW mode */
570 retval = read_flash_id(bank, &id);
571 SMI_SET_HW_MODE();
572 if (retval != ERROR_OK)
573 return retval;
574
575 stmsmi_info->dev = NULL;
576 for (const struct flash_device *p = flash_devices; p->name ; p++)
577 if (p->device_id == id) {
578 stmsmi_info->dev = p;
579 break;
580 }
581
582 if (!stmsmi_info->dev) {
583 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
584 return ERROR_FAIL;
585 }
586
587 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
588 stmsmi_info->dev->name, stmsmi_info->dev->device_id);
589
590 /* Set correct size value */
591 bank->size = stmsmi_info->dev->size_in_bytes;
592
593 /* create and fill sectors array */
594 bank->num_sectors =
595 stmsmi_info->dev->size_in_bytes / stmsmi_info->dev->sectorsize;
596 sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
597 if (sectors == NULL) {
598 LOG_ERROR("not enough memory");
599 return ERROR_FAIL;
600 }
601
602 for (int sector = 0; sector < bank->num_sectors; sector++) {
603 sectors[sector].offset = sector * stmsmi_info->dev->sectorsize;
604 sectors[sector].size = stmsmi_info->dev->sectorsize;
605 sectors[sector].is_erased = -1;
606 sectors[sector].is_protected = 1;
607 }
608
609 bank->sectors = sectors;
610 stmsmi_info->probed = 1;
611 return ERROR_OK;
612 }
613
614 static int stmsmi_auto_probe(struct flash_bank *bank)
615 {
616 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
617 if (stmsmi_info->probed)
618 return ERROR_OK;
619 return stmsmi_probe(bank);
620 }
621
622 static int stmsmi_protect_check(struct flash_bank *bank)
623 {
624 /* Nothing to do. Protection is only handled in SW. */
625 return ERROR_OK;
626 }
627
628 static int get_stmsmi_info(struct flash_bank *bank, char *buf, int buf_size)
629 {
630 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
631
632 if (!(stmsmi_info->probed)) {
633 snprintf(buf, buf_size,
634 "\nSMI flash bank not probed yet\n");
635 return ERROR_OK;
636 }
637
638 snprintf(buf, buf_size, "\nSMI flash information:\n"
639 " Device \'%s\' (ID 0x%08" PRIx32 ")\n",
640 stmsmi_info->dev->name, stmsmi_info->dev->device_id);
641
642 return ERROR_OK;
643 }
644
645 struct flash_driver stmsmi_flash = {
646 .name = "stmsmi",
647 .flash_bank_command = stmsmi_flash_bank_command,
648 .erase = stmsmi_erase,
649 .protect = stmsmi_protect,
650 .write = stmsmi_write,
651 .read = default_flash_read,
652 .probe = stmsmi_probe,
653 .auto_probe = stmsmi_auto_probe,
654 .erase_check = default_flash_blank_check,
655 .protect_check = stmsmi_protect_check,
656 .info = get_stmsmi_info,
657 };