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3c49b8be1b3a587e52cfcd4cf86ba8e0c7b52747
[openocd.git] / src / flash / nor / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include <helper/binarybuffer.h>
29 #include <target/algorithm.h>
30 #include <target/armv7m.h>
31
32
33 /* stm32x register locations */
34
35 #define STM32_FLASH_ACR 0x40022000
36 #define STM32_FLASH_KEYR 0x40022004
37 #define STM32_FLASH_OPTKEYR 0x40022008
38 #define STM32_FLASH_SR 0x4002200C
39 #define STM32_FLASH_CR 0x40022010
40 #define STM32_FLASH_AR 0x40022014
41 #define STM32_FLASH_OBR 0x4002201C
42 #define STM32_FLASH_WRPR 0x40022020
43
44 /* option byte location */
45
46 #define STM32_OB_RDP 0x1FFFF800
47 #define STM32_OB_USER 0x1FFFF802
48 #define STM32_OB_DATA0 0x1FFFF804
49 #define STM32_OB_DATA1 0x1FFFF806
50 #define STM32_OB_WRP0 0x1FFFF808
51 #define STM32_OB_WRP1 0x1FFFF80A
52 #define STM32_OB_WRP2 0x1FFFF80C
53 #define STM32_OB_WRP3 0x1FFFF80E
54
55 /* FLASH_CR register bits */
56
57 #define FLASH_PG (1 << 0)
58 #define FLASH_PER (1 << 1)
59 #define FLASH_MER (1 << 2)
60 #define FLASH_OPTPG (1 << 4)
61 #define FLASH_OPTER (1 << 5)
62 #define FLASH_STRT (1 << 6)
63 #define FLASH_LOCK (1 << 7)
64 #define FLASH_OPTWRE (1 << 9)
65
66 /* FLASH_SR register bits */
67
68 #define FLASH_BSY (1 << 0)
69 #define FLASH_PGERR (1 << 2)
70 #define FLASH_WRPRTERR (1 << 4)
71 #define FLASH_EOP (1 << 5)
72
73 /* STM32_FLASH_OBR bit definitions (reading) */
74
75 #define OPT_ERROR 0
76 #define OPT_READOUT 1
77 #define OPT_RDWDGSW 2
78 #define OPT_RDRSTSTOP 3
79 #define OPT_RDRSTSTDBY 4
80
81 /* register unlock keys */
82
83 #define KEY1 0x45670123
84 #define KEY2 0xCDEF89AB
85
86
87 struct stm32x_options
88 {
89 uint16_t RDP;
90 uint16_t user_options;
91 uint16_t protection[4];
92 };
93
94 struct stm32x_flash_bank
95 {
96 struct stm32x_options option_bytes;
97 struct working_area *write_algorithm;
98 int ppage_size;
99 int probed;
100 };
101
102 struct stm32x_mem_layout {
103 uint32_t sector_start;
104 uint32_t sector_size;
105 };
106
107 static int stm32x_mass_erase(struct flash_bank *bank);
108
109 /* flash bank stm32x <base> <size> 0 0 <target#>
110 */
111 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
112 {
113 struct stm32x_flash_bank *stm32x_info;
114
115 if (CMD_ARGC < 6)
116 {
117 LOG_WARNING("incomplete flash_bank stm32x configuration");
118 return ERROR_FLASH_BANK_INVALID;
119 }
120
121 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
122 bank->driver_priv = stm32x_info;
123
124 stm32x_info->write_algorithm = NULL;
125 stm32x_info->probed = 0;
126
127 return ERROR_OK;
128 }
129
130 static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
131 {
132 struct target *target = bank->target;
133 return target_read_u32(target, STM32_FLASH_SR, status);
134 }
135
136 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
137 {
138 struct target *target = bank->target;
139 uint32_t status;
140 int retval = ERROR_OK;
141
142 /* wait for busy to clear */
143 for (;;)
144 {
145 retval = stm32x_get_flash_status(bank, &status);
146 if (retval != ERROR_OK)
147 return retval;
148 LOG_DEBUG("status: 0x%" PRIx32 "", status);
149 if ((status & FLASH_BSY) == 0)
150 break;
151 if (timeout-- <= 0)
152 {
153 LOG_ERROR("timed out waiting for flash");
154 return ERROR_FAIL;
155 }
156 alive_sleep(1);
157 }
158
159 if (status & FLASH_WRPRTERR)
160 {
161 LOG_ERROR("stm32x device protected");
162 retval = ERROR_FAIL;
163 }
164
165 if (status & FLASH_PGERR)
166 {
167 LOG_ERROR("stm32x device programming failed");
168 retval = ERROR_FAIL;
169 }
170
171 /* Clear but report errors */
172 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
173 {
174 /* If this operation fails, we ignore it and report the original
175 * retval
176 */
177 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
178 }
179 return retval;
180 }
181
182 static int stm32x_read_options(struct flash_bank *bank)
183 {
184 uint32_t optiondata;
185 struct stm32x_flash_bank *stm32x_info = NULL;
186 struct target *target = bank->target;
187
188 stm32x_info = bank->driver_priv;
189
190 /* read current option bytes */
191 int retval = target_read_u32(target, STM32_FLASH_OBR, &optiondata);
192 if (retval != ERROR_OK)
193 return retval;
194
195 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
196 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
197
198 if (optiondata & (1 << OPT_READOUT))
199 LOG_INFO("Device Security Bit Set");
200
201 /* each bit refers to a 4bank protection */
202 retval = target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
203 if (retval != ERROR_OK)
204 return retval;
205
206 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
207 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
208 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
209 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
210
211 return ERROR_OK;
212 }
213
214 static int stm32x_erase_options(struct flash_bank *bank)
215 {
216 struct stm32x_flash_bank *stm32x_info = NULL;
217 struct target *target = bank->target;
218
219 stm32x_info = bank->driver_priv;
220
221 /* read current options */
222 stm32x_read_options(bank);
223
224 /* unlock flash registers */
225 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
226 if (retval != ERROR_OK)
227 return retval;
228
229 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
230 if (retval != ERROR_OK)
231 return retval;
232
233 /* unlock option flash registers */
234 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
235 if (retval != ERROR_OK)
236 return retval;
237 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
238 if (retval != ERROR_OK)
239 return retval;
240
241 /* erase option bytes */
242 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
243 if (retval != ERROR_OK)
244 return retval;
245 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
246 if (retval != ERROR_OK)
247 return retval;
248
249 retval = stm32x_wait_status_busy(bank, 10);
250 if (retval != ERROR_OK)
251 return retval;
252
253 /* clear readout protection and complementary option bytes
254 * this will also force a device unlock if set */
255 stm32x_info->option_bytes.RDP = 0x5AA5;
256
257 return ERROR_OK;
258 }
259
260 static int stm32x_write_options(struct flash_bank *bank)
261 {
262 struct stm32x_flash_bank *stm32x_info = NULL;
263 struct target *target = bank->target;
264
265 stm32x_info = bank->driver_priv;
266
267 /* unlock flash registers */
268 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
269 if (retval != ERROR_OK)
270 return retval;
271 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
272 if (retval != ERROR_OK)
273 return retval;
274
275 /* unlock option flash registers */
276 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
277 if (retval != ERROR_OK)
278 return retval;
279 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
280 if (retval != ERROR_OK)
281 return retval;
282
283 /* program option bytes */
284 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
285 if (retval != ERROR_OK)
286 return retval;
287
288 /* write user option byte */
289 retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
290 if (retval != ERROR_OK)
291 return retval;
292
293 retval = stm32x_wait_status_busy(bank, 10);
294 if (retval != ERROR_OK)
295 return retval;
296
297 /* write protection byte 1 */
298 retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
299 if (retval != ERROR_OK)
300 return retval;
301
302 retval = stm32x_wait_status_busy(bank, 10);
303 if (retval != ERROR_OK)
304 return retval;
305
306 /* write protection byte 2 */
307 retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
308 if (retval != ERROR_OK)
309 return retval;
310
311 retval = stm32x_wait_status_busy(bank, 10);
312 if (retval != ERROR_OK)
313 return retval;
314
315 /* write protection byte 3 */
316 retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
317 if (retval != ERROR_OK)
318 return retval;
319
320 retval = stm32x_wait_status_busy(bank, 10);
321 if (retval != ERROR_OK)
322 return retval;
323
324 /* write protection byte 4 */
325 retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
326 if (retval != ERROR_OK)
327 return retval;
328
329 retval = stm32x_wait_status_busy(bank, 10);
330 if (retval != ERROR_OK)
331 return retval;
332
333 /* write readout protection bit */
334 retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
335 if (retval != ERROR_OK)
336 return retval;
337
338 retval = stm32x_wait_status_busy(bank, 10);
339 if (retval != ERROR_OK)
340 return retval;
341
342 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
343 if (retval != ERROR_OK)
344 return retval;
345
346 return ERROR_OK;
347 }
348
349 static int stm32x_protect_check(struct flash_bank *bank)
350 {
351 struct target *target = bank->target;
352 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
353
354 uint32_t protection;
355 int i, s;
356 int num_bits;
357 int set;
358
359 if (target->state != TARGET_HALTED)
360 {
361 LOG_ERROR("Target not halted");
362 return ERROR_TARGET_NOT_HALTED;
363 }
364
365 /* medium density - each bit refers to a 4bank protection
366 * high density - each bit refers to a 2bank protection */
367 int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
368 if (retval != ERROR_OK)
369 return retval;
370
371 /* medium density - each protection bit is for 4 * 1K pages
372 * high density - each protection bit is for 2 * 2K pages */
373 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
374
375 if (stm32x_info->ppage_size == 2)
376 {
377 /* high density flash/connectivity line protection */
378
379 set = 1;
380
381 if (protection & (1 << 31))
382 set = 0;
383
384 /* bit 31 controls sector 62 - 255 protection for high density
385 * bit 31 controls sector 62 - 127 protection for connectivity line */
386 for (s = 62; s < bank->num_sectors; s++)
387 {
388 bank->sectors[s].is_protected = set;
389 }
390
391 if (bank->num_sectors > 61)
392 num_bits = 31;
393
394 for (i = 0; i < num_bits; i++)
395 {
396 set = 1;
397
398 if (protection & (1 << i))
399 set = 0;
400
401 for (s = 0; s < stm32x_info->ppage_size; s++)
402 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
403 }
404 }
405 else
406 {
407 /* low/medium density flash protection */
408 for (i = 0; i < num_bits; i++)
409 {
410 set = 1;
411
412 if (protection & (1 << i))
413 set = 0;
414
415 for (s = 0; s < stm32x_info->ppage_size; s++)
416 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
417 }
418 }
419
420 return ERROR_OK;
421 }
422
423 static int stm32x_erase(struct flash_bank *bank, int first, int last)
424 {
425 struct target *target = bank->target;
426 int i;
427
428 if (bank->target->state != TARGET_HALTED)
429 {
430 LOG_ERROR("Target not halted");
431 return ERROR_TARGET_NOT_HALTED;
432 }
433
434 if ((first == 0) && (last == (bank->num_sectors - 1)))
435 {
436 return stm32x_mass_erase(bank);
437 }
438
439 /* unlock flash registers */
440 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
441 if (retval != ERROR_OK)
442 return retval;
443 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
444 if (retval != ERROR_OK)
445 return retval;
446
447 for (i = first; i <= last; i++)
448 {
449 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
450 if (retval != ERROR_OK)
451 return retval;
452 retval = target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
453 if (retval != ERROR_OK)
454 return retval;
455 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
456 if (retval != ERROR_OK)
457 return retval;
458
459 retval = stm32x_wait_status_busy(bank, 100);
460 if (retval != ERROR_OK)
461 return retval;
462
463 bank->sectors[i].is_erased = 1;
464 }
465
466 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
467 if (retval != ERROR_OK)
468 return retval;
469
470 return ERROR_OK;
471 }
472
473 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
474 {
475 struct stm32x_flash_bank *stm32x_info = NULL;
476 struct target *target = bank->target;
477 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
478 int i, reg, bit;
479 int status;
480 uint32_t protection;
481
482 stm32x_info = bank->driver_priv;
483
484 if (target->state != TARGET_HALTED)
485 {
486 LOG_ERROR("Target not halted");
487 return ERROR_TARGET_NOT_HALTED;
488 }
489
490 if ((first % stm32x_info->ppage_size) != 0)
491 {
492 LOG_WARNING("aligned start protect sector to a %d sector boundary",
493 stm32x_info->ppage_size);
494 first = first - (first % stm32x_info->ppage_size);
495 }
496 if (((last + 1) % stm32x_info->ppage_size) != 0)
497 {
498 LOG_WARNING("aligned end protect sector to a %d sector boundary",
499 stm32x_info->ppage_size);
500 last++;
501 last = last - (last % stm32x_info->ppage_size);
502 last--;
503 }
504
505 /* medium density - each bit refers to a 4bank protection
506 * high density - each bit refers to a 2bank protection */
507 int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
508 if (retval != ERROR_OK)
509 return retval;
510
511 prot_reg[0] = (uint16_t)protection;
512 prot_reg[1] = (uint16_t)(protection >> 8);
513 prot_reg[2] = (uint16_t)(protection >> 16);
514 prot_reg[3] = (uint16_t)(protection >> 24);
515
516 if (stm32x_info->ppage_size == 2)
517 {
518 /* high density flash */
519
520 /* bit 7 controls sector 62 - 255 protection */
521 if (last > 61)
522 {
523 if (set)
524 prot_reg[3] &= ~(1 << 7);
525 else
526 prot_reg[3] |= (1 << 7);
527 }
528
529 if (first > 61)
530 first = 62;
531 if (last > 61)
532 last = 61;
533
534 for (i = first; i <= last; i++)
535 {
536 reg = (i / stm32x_info->ppage_size) / 8;
537 bit = (i / stm32x_info->ppage_size) - (reg * 8);
538
539 if (set)
540 prot_reg[reg] &= ~(1 << bit);
541 else
542 prot_reg[reg] |= (1 << bit);
543 }
544 }
545 else
546 {
547 /* medium density flash */
548 for (i = first; i <= last; i++)
549 {
550 reg = (i / stm32x_info->ppage_size) / 8;
551 bit = (i / stm32x_info->ppage_size) - (reg * 8);
552
553 if (set)
554 prot_reg[reg] &= ~(1 << bit);
555 else
556 prot_reg[reg] |= (1 << bit);
557 }
558 }
559
560 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
561 return status;
562
563 stm32x_info->option_bytes.protection[0] = prot_reg[0];
564 stm32x_info->option_bytes.protection[1] = prot_reg[1];
565 stm32x_info->option_bytes.protection[2] = prot_reg[2];
566 stm32x_info->option_bytes.protection[3] = prot_reg[3];
567
568 return stm32x_write_options(bank);
569 }
570
571 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
572 uint32_t offset, uint32_t count)
573 {
574 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
575 struct target *target = bank->target;
576 uint32_t buffer_size = 16384;
577 struct working_area *source;
578 uint32_t address = bank->base + offset;
579 struct reg_param reg_params[4];
580 struct armv7m_algorithm armv7m_info;
581 int retval = ERROR_OK;
582
583 /* see contib/loaders/flash/stm32x.s for src */
584
585 static const uint8_t stm32x_flash_write_code[] = {
586 /* #define STM32_FLASH_CR_OFFSET 0x10 */
587 /* #define STM32_FLASH_SR_OFFSET 0x0C */
588 /* write: */
589 0xdf, 0xf8, 0x20, 0x40, /* ldr r4, STM32_FLASH_BASE */
590 /* write_half_word: */
591 0x01, 0x23, /* movs r3, #0x01 */
592 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
593 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
594 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
595 /* busy: */
596 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
597 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
598 0xfb, 0xd0, /* beq busy */
599 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
600 0x01, 0xd1, /* bne exit */
601 0x01, 0x3a, /* subs r2, r2, #0x01 */
602 0xf0, 0xd1, /* bne write_half_word */
603 /* exit: */
604 0x00, 0xbe, /* bkpt #0x00 */
605 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
606 };
607
608 /* flash write code */
609 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
610 &stm32x_info->write_algorithm) != ERROR_OK)
611 {
612 LOG_WARNING("no working area available, can't do block memory writes");
613 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
614 };
615
616 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
617 sizeof(stm32x_flash_write_code),
618 (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
619 return retval;
620
621 /* memory buffer */
622 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
623 {
624 buffer_size /= 2;
625 if (buffer_size <= 256)
626 {
627 /* if we already allocated the writing code, but failed to get a
628 * buffer, free the algorithm */
629 if (stm32x_info->write_algorithm)
630 target_free_working_area(target, stm32x_info->write_algorithm);
631
632 LOG_WARNING("no large enough working area available, can't do block memory writes");
633 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
634 }
635 };
636
637 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
638 armv7m_info.core_mode = ARMV7M_MODE_ANY;
639
640 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
641 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
642 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
643 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
644
645 while (count > 0)
646 {
647 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
648 (buffer_size / 2) : count;
649
650 if ((retval = target_write_buffer(target, source->address,
651 thisrun_count * 2, buffer)) != ERROR_OK)
652 break;
653
654 buf_set_u32(reg_params[0].value, 0, 32, source->address);
655 buf_set_u32(reg_params[1].value, 0, 32, address);
656 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
657
658 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
659 stm32x_info->write_algorithm->address,
660 0,
661 10000, &armv7m_info)) != ERROR_OK)
662 {
663 LOG_ERROR("error executing stm32x flash write algorithm");
664 break;
665 }
666
667 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
668 {
669 LOG_ERROR("flash memory not erased before writing");
670 /* Clear but report errors */
671 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
672 retval = ERROR_FAIL;
673 break;
674 }
675
676 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
677 {
678 LOG_ERROR("flash memory write protected");
679 /* Clear but report errors */
680 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
681 retval = ERROR_FAIL;
682 break;
683 }
684
685 buffer += thisrun_count * 2;
686 address += thisrun_count * 2;
687 count -= thisrun_count;
688 }
689
690 target_free_working_area(target, source);
691 target_free_working_area(target, stm32x_info->write_algorithm);
692
693 destroy_reg_param(&reg_params[0]);
694 destroy_reg_param(&reg_params[1]);
695 destroy_reg_param(&reg_params[2]);
696 destroy_reg_param(&reg_params[3]);
697
698 return retval;
699 }
700
701 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
702 uint32_t offset, uint32_t count)
703 {
704 struct target *target = bank->target;
705 uint32_t words_remaining = (count / 2);
706 uint32_t bytes_remaining = (count & 0x00000001);
707 uint32_t address = bank->base + offset;
708 uint32_t bytes_written = 0;
709 int retval;
710
711 if (bank->target->state != TARGET_HALTED)
712 {
713 LOG_ERROR("Target not halted");
714 return ERROR_TARGET_NOT_HALTED;
715 }
716
717 if (offset & 0x1)
718 {
719 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
720 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
721 }
722
723 /* unlock flash registers */
724 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
725 if (retval != ERROR_OK)
726 return retval;
727 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
728 if (retval != ERROR_OK)
729 return retval;
730
731 /* multiple half words (2-byte) to be programmed? */
732 if (words_remaining > 0)
733 {
734 /* try using a block write */
735 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
736 {
737 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
738 {
739 /* if block write failed (no sufficient working area),
740 * we use normal (slow) single dword accesses */
741 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
742 }
743 }
744 else
745 {
746 buffer += words_remaining * 2;
747 address += words_remaining * 2;
748 words_remaining = 0;
749 }
750 }
751
752 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
753 return retval;
754
755 while (words_remaining > 0)
756 {
757 uint16_t value;
758 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
759
760 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
761 if (retval != ERROR_OK)
762 return retval;
763 retval = target_write_u16(target, address, value);
764 if (retval != ERROR_OK)
765 return retval;
766
767 retval = stm32x_wait_status_busy(bank, 5);
768 if (retval != ERROR_OK)
769 return retval;
770
771 bytes_written += 2;
772 words_remaining--;
773 address += 2;
774 }
775
776 if (bytes_remaining)
777 {
778 uint16_t value = 0xffff;
779 memcpy(&value, buffer + bytes_written, bytes_remaining);
780
781 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
782 if (retval != ERROR_OK)
783 return retval;
784 retval = target_write_u16(target, address, value);
785 if (retval != ERROR_OK)
786 return retval;
787
788 retval = stm32x_wait_status_busy(bank, 5);
789 if (retval != ERROR_OK)
790 return retval;
791 }
792
793 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
794 }
795
796 static int stm32x_probe(struct flash_bank *bank)
797 {
798 struct target *target = bank->target;
799 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
800 int i;
801 uint16_t num_pages;
802 uint32_t device_id;
803 int page_size;
804
805 stm32x_info->probed = 0;
806
807 /* read stm32 device id register */
808 int retval = target_read_u32(target, 0xE0042000, &device_id);
809 if (retval != ERROR_OK)
810 return retval;
811 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
812
813 /* get flash size from target. */
814 retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
815 if (retval != ERROR_OK)
816 {
817 LOG_WARNING("failed reading flash size, default to max target family");
818 /* failed reading flash size, default to max target family */
819 num_pages = 0xffff;
820 }
821
822 if ((device_id & 0x7ff) == 0x410)
823 {
824 /* medium density - we have 1k pages
825 * 4 pages for a protection area */
826 page_size = 1024;
827 stm32x_info->ppage_size = 4;
828
829 /* check for early silicon */
830 if (num_pages == 0xffff)
831 {
832 /* number of sectors incorrect on revA */
833 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
834 num_pages = 128;
835 }
836 }
837 else if ((device_id & 0x7ff) == 0x412)
838 {
839 /* low density - we have 1k pages
840 * 4 pages for a protection area */
841 page_size = 1024;
842 stm32x_info->ppage_size = 4;
843
844 /* check for early silicon */
845 if (num_pages == 0xffff)
846 {
847 /* number of sectors incorrect on revA */
848 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
849 num_pages = 32;
850 }
851 }
852 else if ((device_id & 0x7ff) == 0x414)
853 {
854 /* high density - we have 2k pages
855 * 2 pages for a protection area */
856 page_size = 2048;
857 stm32x_info->ppage_size = 2;
858
859 /* check for early silicon */
860 if (num_pages == 0xffff)
861 {
862 /* number of sectors incorrect on revZ */
863 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
864 num_pages = 512;
865 }
866 }
867 else if ((device_id & 0x7ff) == 0x418)
868 {
869 /* connectivity line density - we have 2k pages
870 * 2 pages for a protection area */
871 page_size = 2048;
872 stm32x_info->ppage_size = 2;
873
874 /* check for early silicon */
875 if (num_pages == 0xffff)
876 {
877 /* number of sectors incorrect on revZ */
878 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
879 num_pages = 256;
880 }
881 }
882 else if ((device_id & 0x7ff) == 0x420)
883 {
884 /* value line density - we have 1k pages
885 * 4 pages for a protection area */
886 page_size = 1024;
887 stm32x_info->ppage_size = 4;
888
889 /* check for early silicon */
890 if (num_pages == 0xffff)
891 {
892 /* number of sectors may be incorrrect on early silicon */
893 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
894 num_pages = 128;
895 }
896 }
897 else
898 {
899 LOG_WARNING("Cannot identify target as a STM32 family.");
900 return ERROR_FAIL;
901 }
902
903 LOG_INFO("flash size = %dkbytes", num_pages);
904
905 /* calculate numbers of pages */
906 num_pages /= (page_size / 1024);
907
908 if (bank->sectors)
909 {
910 free(bank->sectors);
911 bank->sectors = NULL;
912 }
913
914 bank->base = 0x08000000;
915 bank->size = (num_pages * page_size);
916 bank->num_sectors = num_pages;
917 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
918
919 for (i = 0; i < num_pages; i++)
920 {
921 bank->sectors[i].offset = i * page_size;
922 bank->sectors[i].size = page_size;
923 bank->sectors[i].is_erased = -1;
924 bank->sectors[i].is_protected = 1;
925 }
926
927 stm32x_info->probed = 1;
928
929 return ERROR_OK;
930 }
931
932 static int stm32x_auto_probe(struct flash_bank *bank)
933 {
934 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
935 if (stm32x_info->probed)
936 return ERROR_OK;
937 return stm32x_probe(bank);
938 }
939
940 #if 0
941 COMMAND_HANDLER(stm32x_handle_part_id_command)
942 {
943 return ERROR_OK;
944 }
945 #endif
946
947 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
948 {
949 struct target *target = bank->target;
950 uint32_t device_id;
951 int printed;
952
953 /* read stm32 device id register */
954 int retval = target_read_u32(target, 0xE0042000, &device_id);
955 if (retval != ERROR_OK)
956 return retval;
957
958 if ((device_id & 0x7ff) == 0x410)
959 {
960 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
961 buf += printed;
962 buf_size -= printed;
963
964 switch (device_id >> 16)
965 {
966 case 0x0000:
967 snprintf(buf, buf_size, "A");
968 break;
969
970 case 0x2000:
971 snprintf(buf, buf_size, "B");
972 break;
973
974 case 0x2001:
975 snprintf(buf, buf_size, "Z");
976 break;
977
978 case 0x2003:
979 snprintf(buf, buf_size, "Y");
980 break;
981
982 default:
983 snprintf(buf, buf_size, "unknown");
984 break;
985 }
986 }
987 else if ((device_id & 0x7ff) == 0x412)
988 {
989 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
990 buf += printed;
991 buf_size -= printed;
992
993 switch (device_id >> 16)
994 {
995 case 0x1000:
996 snprintf(buf, buf_size, "A");
997 break;
998
999 default:
1000 snprintf(buf, buf_size, "unknown");
1001 break;
1002 }
1003 }
1004 else if ((device_id & 0x7ff) == 0x414)
1005 {
1006 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1007 buf += printed;
1008 buf_size -= printed;
1009
1010 switch (device_id >> 16)
1011 {
1012 case 0x1000:
1013 snprintf(buf, buf_size, "A");
1014 break;
1015
1016 case 0x1001:
1017 snprintf(buf, buf_size, "Z");
1018 break;
1019
1020 default:
1021 snprintf(buf, buf_size, "unknown");
1022 break;
1023 }
1024 }
1025 else if ((device_id & 0x7ff) == 0x418)
1026 {
1027 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1028 buf += printed;
1029 buf_size -= printed;
1030
1031 switch (device_id >> 16)
1032 {
1033 case 0x1000:
1034 snprintf(buf, buf_size, "A");
1035 break;
1036
1037 case 0x1001:
1038 snprintf(buf, buf_size, "Z");
1039 break;
1040
1041 default:
1042 snprintf(buf, buf_size, "unknown");
1043 break;
1044 }
1045 }
1046 else if ((device_id & 0x7ff) == 0x420)
1047 {
1048 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1049 buf += printed;
1050 buf_size -= printed;
1051
1052 switch (device_id >> 16)
1053 {
1054 case 0x1000:
1055 snprintf(buf, buf_size, "A");
1056 break;
1057
1058 case 0x1001:
1059 snprintf(buf, buf_size, "Z");
1060 break;
1061
1062 default:
1063 snprintf(buf, buf_size, "unknown");
1064 break;
1065 }
1066 }
1067 else
1068 {
1069 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1070 return ERROR_FAIL;
1071 }
1072
1073 return ERROR_OK;
1074 }
1075
1076 COMMAND_HANDLER(stm32x_handle_lock_command)
1077 {
1078 struct target *target = NULL;
1079 struct stm32x_flash_bank *stm32x_info = NULL;
1080
1081 if (CMD_ARGC < 1)
1082 {
1083 command_print(CMD_CTX, "stm32x lock <bank>");
1084 return ERROR_OK;
1085 }
1086
1087 struct flash_bank *bank;
1088 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1089 if (ERROR_OK != retval)
1090 return retval;
1091
1092 stm32x_info = bank->driver_priv;
1093
1094 target = bank->target;
1095
1096 if (target->state != TARGET_HALTED)
1097 {
1098 LOG_ERROR("Target not halted");
1099 return ERROR_TARGET_NOT_HALTED;
1100 }
1101
1102 if (stm32x_erase_options(bank) != ERROR_OK)
1103 {
1104 command_print(CMD_CTX, "stm32x failed to erase options");
1105 return ERROR_OK;
1106 }
1107
1108 /* set readout protection */
1109 stm32x_info->option_bytes.RDP = 0;
1110
1111 if (stm32x_write_options(bank) != ERROR_OK)
1112 {
1113 command_print(CMD_CTX, "stm32x failed to lock device");
1114 return ERROR_OK;
1115 }
1116
1117 command_print(CMD_CTX, "stm32x locked");
1118
1119 return ERROR_OK;
1120 }
1121
1122 COMMAND_HANDLER(stm32x_handle_unlock_command)
1123 {
1124 struct target *target = NULL;
1125 struct stm32x_flash_bank *stm32x_info = NULL;
1126
1127 if (CMD_ARGC < 1)
1128 {
1129 command_print(CMD_CTX, "stm32x unlock <bank>");
1130 return ERROR_OK;
1131 }
1132
1133 struct flash_bank *bank;
1134 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1135 if (ERROR_OK != retval)
1136 return retval;
1137
1138 stm32x_info = bank->driver_priv;
1139
1140 target = bank->target;
1141
1142 if (target->state != TARGET_HALTED)
1143 {
1144 LOG_ERROR("Target not halted");
1145 return ERROR_TARGET_NOT_HALTED;
1146 }
1147
1148 if (stm32x_erase_options(bank) != ERROR_OK)
1149 {
1150 command_print(CMD_CTX, "stm32x failed to unlock device");
1151 return ERROR_OK;
1152 }
1153
1154 if (stm32x_write_options(bank) != ERROR_OK)
1155 {
1156 command_print(CMD_CTX, "stm32x failed to lock device");
1157 return ERROR_OK;
1158 }
1159
1160 command_print(CMD_CTX, "stm32x unlocked.\n"
1161 "INFO: a reset or power cycle is required "
1162 "for the new settings to take effect.");
1163
1164 return ERROR_OK;
1165 }
1166
1167 COMMAND_HANDLER(stm32x_handle_options_read_command)
1168 {
1169 uint32_t optionbyte;
1170 struct target *target = NULL;
1171 struct stm32x_flash_bank *stm32x_info = NULL;
1172
1173 if (CMD_ARGC < 1)
1174 {
1175 command_print(CMD_CTX, "stm32x options_read <bank>");
1176 return ERROR_OK;
1177 }
1178
1179 struct flash_bank *bank;
1180 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1181 if (ERROR_OK != retval)
1182 return retval;
1183
1184 stm32x_info = bank->driver_priv;
1185
1186 target = bank->target;
1187
1188 if (target->state != TARGET_HALTED)
1189 {
1190 LOG_ERROR("Target not halted");
1191 return ERROR_TARGET_NOT_HALTED;
1192 }
1193
1194 retval = target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1195 if (retval != ERROR_OK)
1196 return retval;
1197 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1198
1199 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1200 command_print(CMD_CTX, "Option Byte Complement Error");
1201
1202 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1203 command_print(CMD_CTX, "Readout Protection On");
1204 else
1205 command_print(CMD_CTX, "Readout Protection Off");
1206
1207 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1208 command_print(CMD_CTX, "Software Watchdog");
1209 else
1210 command_print(CMD_CTX, "Hardware Watchdog");
1211
1212 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1213 command_print(CMD_CTX, "Stop: No reset generated");
1214 else
1215 command_print(CMD_CTX, "Stop: Reset generated");
1216
1217 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1218 command_print(CMD_CTX, "Standby: No reset generated");
1219 else
1220 command_print(CMD_CTX, "Standby: Reset generated");
1221
1222 return ERROR_OK;
1223 }
1224
1225 COMMAND_HANDLER(stm32x_handle_options_write_command)
1226 {
1227 struct target *target = NULL;
1228 struct stm32x_flash_bank *stm32x_info = NULL;
1229 uint16_t optionbyte = 0xF8;
1230
1231 if (CMD_ARGC < 4)
1232 {
1233 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1234 return ERROR_OK;
1235 }
1236
1237 struct flash_bank *bank;
1238 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1239 if (ERROR_OK != retval)
1240 return retval;
1241
1242 stm32x_info = bank->driver_priv;
1243
1244 target = bank->target;
1245
1246 if (target->state != TARGET_HALTED)
1247 {
1248 LOG_ERROR("Target not halted");
1249 return ERROR_TARGET_NOT_HALTED;
1250 }
1251
1252 /* REVISIT: ignores some options which we will display...
1253 * and doesn't insist on the specified syntax.
1254 */
1255
1256 /* OPT_RDWDGSW */
1257 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1258 {
1259 optionbyte |= (1 << 0);
1260 }
1261 else /* REVISIT must be "HWWDG" then ... */
1262 {
1263 optionbyte &= ~(1 << 0);
1264 }
1265
1266 /* OPT_RDRSTSTDBY */
1267 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1268 {
1269 optionbyte |= (1 << 1);
1270 }
1271 else /* REVISIT must be "RSTSTNDBY" then ... */
1272 {
1273 optionbyte &= ~(1 << 1);
1274 }
1275
1276 /* OPT_RDRSTSTOP */
1277 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1278 {
1279 optionbyte |= (1 << 2);
1280 }
1281 else /* REVISIT must be "RSTSTOP" then ... */
1282 {
1283 optionbyte &= ~(1 << 2);
1284 }
1285
1286 if (stm32x_erase_options(bank) != ERROR_OK)
1287 {
1288 command_print(CMD_CTX, "stm32x failed to erase options");
1289 return ERROR_OK;
1290 }
1291
1292 stm32x_info->option_bytes.user_options = optionbyte;
1293
1294 if (stm32x_write_options(bank) != ERROR_OK)
1295 {
1296 command_print(CMD_CTX, "stm32x failed to write options");
1297 return ERROR_OK;
1298 }
1299
1300 command_print(CMD_CTX, "stm32x write options complete.\n"
1301 "INFO: a reset or power cycle is required "
1302 "for the new settings to take effect.");
1303
1304 return ERROR_OK;
1305 }
1306
1307 static int stm32x_mass_erase(struct flash_bank *bank)
1308 {
1309 struct target *target = bank->target;
1310
1311 if (target->state != TARGET_HALTED)
1312 {
1313 LOG_ERROR("Target not halted");
1314 return ERROR_TARGET_NOT_HALTED;
1315 }
1316
1317 /* unlock option flash registers */
1318 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1319 if (retval != ERROR_OK)
1320 return retval;
1321 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1322 if (retval != ERROR_OK)
1323 return retval;
1324
1325 /* mass erase flash memory */
1326 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1327 if (retval != ERROR_OK)
1328 return retval;
1329 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1330 if (retval != ERROR_OK)
1331 return retval;
1332
1333 retval = stm32x_wait_status_busy(bank, 100);
1334 if (retval != ERROR_OK)
1335 return retval;
1336
1337 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1338 if (retval != ERROR_OK)
1339 return retval;
1340
1341 return ERROR_OK;
1342 }
1343
1344 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1345 {
1346 int i;
1347
1348 if (CMD_ARGC < 1)
1349 {
1350 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1351 return ERROR_OK;
1352 }
1353
1354 struct flash_bank *bank;
1355 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1356 if (ERROR_OK != retval)
1357 return retval;
1358
1359 retval = stm32x_mass_erase(bank);
1360 if (retval == ERROR_OK)
1361 {
1362 /* set all sectors as erased */
1363 for (i = 0; i < bank->num_sectors; i++)
1364 {
1365 bank->sectors[i].is_erased = 1;
1366 }
1367
1368 command_print(CMD_CTX, "stm32x mass erase complete");
1369 }
1370 else
1371 {
1372 command_print(CMD_CTX, "stm32x mass erase failed");
1373 }
1374
1375 return retval;
1376 }
1377
1378 static const struct command_registration stm32x_exec_command_handlers[] = {
1379 {
1380 .name = "lock",
1381 .handler = stm32x_handle_lock_command,
1382 .mode = COMMAND_EXEC,
1383 .usage = "bank_id",
1384 .help = "Lock entire flash device.",
1385 },
1386 {
1387 .name = "unlock",
1388 .handler = stm32x_handle_unlock_command,
1389 .mode = COMMAND_EXEC,
1390 .usage = "bank_id",
1391 .help = "Unlock entire protected flash device.",
1392 },
1393 {
1394 .name = "mass_erase",
1395 .handler = stm32x_handle_mass_erase_command,
1396 .mode = COMMAND_EXEC,
1397 .usage = "bank_id",
1398 .help = "Erase entire flash device.",
1399 },
1400 {
1401 .name = "options_read",
1402 .handler = stm32x_handle_options_read_command,
1403 .mode = COMMAND_EXEC,
1404 .usage = "bank_id",
1405 .help = "Read and display device option byte.",
1406 },
1407 {
1408 .name = "options_write",
1409 .handler = stm32x_handle_options_write_command,
1410 .mode = COMMAND_EXEC,
1411 .usage = "bank_id ('SWWDG'|'HWWDG') "
1412 "('RSTSTNDBY'|'NORSTSTNDBY') "
1413 "('RSTSTOP'|'NORSTSTOP')",
1414 .help = "Replace bits in device option byte.",
1415 },
1416 COMMAND_REGISTRATION_DONE
1417 };
1418
1419 static const struct command_registration stm32x_command_handlers[] = {
1420 {
1421 .name = "stm32x",
1422 .mode = COMMAND_ANY,
1423 .help = "stm32x flash command group",
1424 .chain = stm32x_exec_command_handlers,
1425 },
1426 COMMAND_REGISTRATION_DONE
1427 };
1428
1429 struct flash_driver stm32x_flash = {
1430 .name = "stm32x",
1431 .commands = stm32x_command_handlers,
1432 .flash_bank_command = stm32x_flash_bank_command,
1433 .erase = stm32x_erase,
1434 .protect = stm32x_protect,
1435 .write = stm32x_write,
1436 .read = default_flash_read,
1437 .probe = stm32x_probe,
1438 .auto_probe = stm32x_auto_probe,
1439 .erase_check = default_flash_mem_blank_check,
1440 .protect_check = stm32x_protect_check,
1441 .info = get_stm32x_info,
1442 };
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