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armv7m: use ARM_MODE_THREAD core mode for algoorithm's
[openocd.git] / src / flash / nor / stm32lx.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35 #include <target/cortex_m.h>
36
37 /* stm32lx flash register locations */
38
39 #define FLASH_BASE 0x40023C00
40 #define FLASH_ACR 0x40023C00
41 #define FLASH_PECR 0x40023C04
42 #define FLASH_PDKEYR 0x40023C08
43 #define FLASH_PEKEYR 0x40023C0C
44 #define FLASH_PRGKEYR 0x40023C10
45 #define FLASH_OPTKEYR 0x40023C14
46 #define FLASH_SR 0x40023C18
47 #define FLASH_OBR 0x40023C1C
48 #define FLASH_WRPR 0x40023C20
49
50 /* FLASH_ACR bites */
51 #define FLASH_ACR__LATENCY (1<<0)
52 #define FLASH_ACR__PRFTEN (1<<1)
53 #define FLASH_ACR__ACC64 (1<<2)
54 #define FLASH_ACR__SLEEP_PD (1<<3)
55 #define FLASH_ACR__RUN_PD (1<<4)
56
57 /* FLASH_PECR bits */
58 #define FLASH_PECR__PELOCK (1<<0)
59 #define FLASH_PECR__PRGLOCK (1<<1)
60 #define FLASH_PECR__OPTLOCK (1<<2)
61 #define FLASH_PECR__PROG (1<<3)
62 #define FLASH_PECR__DATA (1<<4)
63 #define FLASH_PECR__FTDW (1<<8)
64 #define FLASH_PECR__ERASE (1<<9)
65 #define FLASH_PECR__FPRG (1<<10)
66 #define FLASH_PECR__EOPIE (1<<16)
67 #define FLASH_PECR__ERRIE (1<<17)
68 #define FLASH_PECR__OBL_LAUNCH (1<<18)
69
70 /* FLASH_SR bits */
71 #define FLASH_SR__BSY (1<<0)
72 #define FLASH_SR__EOP (1<<1)
73 #define FLASH_SR__ENDHV (1<<2)
74 #define FLASH_SR__READY (1<<3)
75 #define FLASH_SR__WRPERR (1<<8)
76 #define FLASH_SR__PGAERR (1<<9)
77 #define FLASH_SR__SIZERR (1<<10)
78 #define FLASH_SR__OPTVERR (1<<11)
79
80 /* Unlock keys */
81 #define PEKEY1 0x89ABCDEF
82 #define PEKEY2 0x02030405
83 #define PRGKEY1 0x8C9DAEBF
84 #define PRGKEY2 0x13141516
85 #define OPTKEY1 0xFBEAD9C8
86 #define OPTKEY2 0x24252627
87
88 /* other registers */
89 #define DBGMCU_IDCODE 0xE0042000
90 #define F_SIZE 0x1FF8004C
91
92 /* Constants */
93 #define FLASH_PAGE_SIZE 256
94 #define FLASH_SECTOR_SIZE 4096
95 #define FLASH_PAGES_PER_SECTOR 16
96 #define FLASH_BANK0_ADDRESS 0x08000000
97
98 /* stm32lx option byte register location */
99 #define OB_RDP 0x1FF80000
100 #define OB_USER 0x1FF80004
101 #define OB_WRP0_1 0x1FF80008
102 #define OB_WRP2_3 0x1FF8000C
103
104 /* OB_RDP values */
105 #define OB_RDP__LEVEL0 0xFF5500AA
106 #define OB_RDP__LEVEL1 0xFFFF0000
107
108 /* stm32lx RCC register locations */
109 #define RCC_CR 0x40023800
110 #define RCC_ICSCR 0x40023804
111 #define RCC_CFGR 0x40023808
112
113 /* RCC_ICSCR bits */
114 #define RCC_ICSCR__MSIRANGE_MASK (7<<13)
115
116 static int stm32lx_unlock_program_memory(struct flash_bank *bank);
117 static int stm32lx_lock_program_memory(struct flash_bank *bank);
118 static int stm32lx_enable_write_half_page(struct flash_bank *bank);
119 static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
120 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
121
122 struct stm32lx_flash_bank {
123 int probed;
124 };
125
126 /* flash bank stm32lx <base> <size> 0 0 <target#>
127 */
128 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
129 {
130 struct stm32lx_flash_bank *stm32lx_info;
131 if (CMD_ARGC < 6)
132 return ERROR_COMMAND_SYNTAX_ERROR;
133
134 /* Create the bank structure */
135 stm32lx_info = malloc(sizeof(struct stm32lx_flash_bank));
136
137 /* Check allocation */
138 if (stm32lx_info == NULL) {
139 LOG_ERROR("failed to allocate bank structure");
140 return ERROR_FAIL;
141 }
142
143 bank->driver_priv = stm32lx_info;
144
145 stm32lx_info->probed = 0;
146
147 return ERROR_OK;
148 }
149
150 static int stm32lx_protect_check(struct flash_bank *bank)
151 {
152 int retval;
153 struct target *target = bank->target;
154
155 uint32_t wrpr;
156
157 if (target->state != TARGET_HALTED) {
158 LOG_ERROR("Target not halted");
159 return ERROR_TARGET_NOT_HALTED;
160 }
161
162 /*
163 * Read the WRPR word, and check each bit (corresponding to each
164 * flash sector
165 */
166 retval = target_read_u32(target, FLASH_WRPR, &wrpr);
167 if (retval != ERROR_OK)
168 return retval;
169
170 for (int i = 0; i < 32; i++) {
171 if (wrpr & (1 << i))
172 bank->sectors[i].is_protected = 1;
173 else
174 bank->sectors[i].is_protected = 0;
175 }
176 return ERROR_OK;
177 }
178
179 static int stm32lx_erase(struct flash_bank *bank, int first, int last)
180 {
181 int retval;
182
183 /*
184 * It could be possible to do a mass erase if all sectors must be
185 * erased, but it is not implemented yet.
186 */
187
188 if (bank->target->state != TARGET_HALTED) {
189 LOG_ERROR("Target not halted");
190 return ERROR_TARGET_NOT_HALTED;
191 }
192
193 /*
194 * Loop over the selected sectors and erase them
195 */
196 for (int i = first; i <= last; i++) {
197 retval = stm32lx_erase_sector(bank, i);
198 if (retval != ERROR_OK)
199 return retval;
200 bank->sectors[i].is_erased = 1;
201 }
202 return ERROR_OK;
203 }
204
205 static int stm32lx_protect(struct flash_bank *bank, int set, int first,
206 int last)
207 {
208 LOG_WARNING("protection of the STM32L flash is not implemented");
209 return ERROR_OK;
210 }
211
212 static int stm32lx_write_half_pages(struct flash_bank *bank, uint8_t *buffer,
213 uint32_t offset, uint32_t count)
214 {
215 struct target *target = bank->target;
216 uint32_t buffer_size = 16384;
217 struct working_area *write_algorithm;
218 struct working_area *source;
219 uint32_t address = bank->base + offset;
220
221 struct reg_param reg_params[3];
222 struct armv7m_algorithm armv7m_info;
223
224 int retval = ERROR_OK;
225
226 /* see contib/loaders/flash/stm32lx.S for src */
227
228 static const uint8_t stm32lx_flash_write_code[] = {
229 /* write_word: */
230 0x00, 0x23, /* movs r3, #0 */
231 0x04, 0xe0, /* b test_done */
232
233 /* write_word: */
234 0x51, 0xf8, 0x04, 0xcb, /* ldr ip, [r1], #4 */
235 0x40, 0xf8, 0x04, 0xcb, /* str ip, [r0], #4 */
236 0x01, 0x33, /* adds r3, #1 */
237
238 /* test_done: */
239 0x93, 0x42, /* cmp r3, r2 */
240 0xf8, 0xd3, /* bcc write_word */
241 0x00, 0xbe, /* bkpt 0 */
242 };
243
244 /* Check if there is an even number of half pages (128bytes) */
245 if (count % 128) {
246 LOG_ERROR("there should be an even number "
247 "of half pages = 128 bytes (count = %" PRIi32 " bytes)", count);
248 return ERROR_FAIL;
249 }
250
251 /* flash write code */
252 if (target_alloc_working_area(target, sizeof(stm32lx_flash_write_code),
253 &write_algorithm) != ERROR_OK) {
254 LOG_DEBUG("no working area for block memory writes");
255 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
256 };
257
258 /* Write the flashing code */
259 retval = target_write_buffer(target,
260 write_algorithm->address,
261 sizeof(stm32lx_flash_write_code),
262 (uint8_t *)stm32lx_flash_write_code);
263 if (retval != ERROR_OK) {
264 target_free_working_area(target, write_algorithm);
265 return retval;
266 }
267
268 /* Allocate half pages memory */
269 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
270 if (buffer_size > 1024)
271 buffer_size -= 1024;
272 else
273 buffer_size /= 2;
274
275 if (buffer_size <= 256) {
276 /* we already allocated the writing code, but failed to get a
277 * buffer, free the algorithm */
278 target_free_working_area(target, write_algorithm);
279
280 LOG_WARNING("no large enough working area available, can't do block memory writes");
281 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
282 }
283 }
284
285 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
286 armv7m_info.core_mode = ARM_MODE_THREAD;
287 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
288 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
289 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
290
291 /* Enable half-page write */
292 retval = stm32lx_enable_write_half_page(bank);
293 if (retval != ERROR_OK) {
294 target_free_working_area(target, source);
295 target_free_working_area(target, write_algorithm);
296
297 destroy_reg_param(&reg_params[0]);
298 destroy_reg_param(&reg_params[1]);
299 destroy_reg_param(&reg_params[2]);
300 return retval;
301 }
302
303 struct armv7m_common *armv7m = target_to_armv7m(target);
304 if (armv7m == NULL) {
305
306 /* something is very wrong if armv7m is NULL */
307 LOG_ERROR("unable to get armv7m target");
308 return retval;
309 }
310
311 /* save any DEMCR flags and configure target to catch any Hard Faults */
312 uint32_t demcr_save = armv7m->demcr;
313 armv7m->demcr = VC_HARDERR;
314
315 /* Loop while there are bytes to write */
316 while (count > 0) {
317 uint32_t this_count;
318 this_count = (count > buffer_size) ? buffer_size : count;
319
320 /* Write the next half pages */
321 retval = target_write_buffer(target, source->address, this_count, buffer);
322 if (retval != ERROR_OK)
323 break;
324
325 /* 4: Store useful information in the registers */
326 /* the destination address of the copy (R0) */
327 buf_set_u32(reg_params[0].value, 0, 32, address);
328 /* The source address of the copy (R1) */
329 buf_set_u32(reg_params[1].value, 0, 32, source->address);
330 /* The length of the copy (R2) */
331 buf_set_u32(reg_params[2].value, 0, 32, this_count / 4);
332
333 /* 5: Execute the bunch of code */
334 retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params)
335 / sizeof(*reg_params), reg_params,
336 write_algorithm->address, 0, 10000, &armv7m_info);
337 if (retval != ERROR_OK)
338 break;
339
340 /* check for Hard Fault */
341 if (armv7m->exception_number == 3)
342 break;
343
344 /* 6: Wait while busy */
345 retval = stm32lx_wait_until_bsy_clear(bank);
346 if (retval != ERROR_OK)
347 break;
348
349 buffer += this_count;
350 address += this_count;
351 count -= this_count;
352 }
353
354 /* restore previous flags */
355 armv7m->demcr = demcr_save;
356
357 if (armv7m->exception_number == 3) {
358
359 /* the stm32l15x devices seem to have an issue when blank.
360 * if a ram loader is executed on a blank device it will
361 * Hard Fault, this issue does not happen for a already programmed device.
362 * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
363 * The workaround of handling the Hard Fault exception does work, but makes the
364 * loader more complicated, as a compromise we manually write the pages, programming time
365 * is reduced by 50% using this slower method.
366 */
367
368 LOG_WARNING("couldn't use loader, falling back to page memory writes");
369
370 while (count > 0) {
371 uint32_t this_count;
372 this_count = (count > 128) ? 128 : count;
373
374 /* Write the next half pages */
375 retval = target_write_buffer(target, address, this_count, buffer);
376 if (retval != ERROR_OK)
377 break;
378
379 /* Wait while busy */
380 retval = stm32lx_wait_until_bsy_clear(bank);
381 if (retval != ERROR_OK)
382 break;
383
384 buffer += this_count;
385 address += this_count;
386 count -= this_count;
387 }
388 }
389
390 if (retval == ERROR_OK)
391 retval = stm32lx_lock_program_memory(bank);
392
393 target_free_working_area(target, source);
394 target_free_working_area(target, write_algorithm);
395
396 destroy_reg_param(&reg_params[0]);
397 destroy_reg_param(&reg_params[1]);
398 destroy_reg_param(&reg_params[2]);
399
400 return retval;
401 }
402
403 static int stm32lx_write(struct flash_bank *bank, uint8_t *buffer,
404 uint32_t offset, uint32_t count)
405 {
406 struct target *target = bank->target;
407
408 uint32_t halfpages_number;
409 uint32_t bytes_remaining = 0;
410 uint32_t address = bank->base + offset;
411 uint32_t bytes_written = 0;
412 int retval, retval2;
413
414 if (bank->target->state != TARGET_HALTED) {
415 LOG_ERROR("Target not halted");
416 return ERROR_TARGET_NOT_HALTED;
417 }
418
419 if (offset & 0x3) {
420 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
421 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
422 }
423
424 retval = stm32lx_unlock_program_memory(bank);
425 if (retval != ERROR_OK)
426 return retval;
427
428 /* first we need to write any unaligned head bytes upto
429 * the next 128 byte page */
430
431 if (offset % 128)
432 bytes_remaining = MIN(count, 128 - (offset % 128));
433
434 while (bytes_remaining > 0) {
435 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
436
437 /* copy remaining bytes into the write buffer */
438 uint32_t bytes_to_write = MIN(4, bytes_remaining);
439 memcpy(value, buffer + bytes_written, bytes_to_write);
440
441 retval = target_write_buffer(target, address, 4, value);
442 if (retval != ERROR_OK)
443 goto reset_pg_and_lock;
444
445 bytes_written += bytes_to_write;
446 bytes_remaining -= bytes_to_write;
447 address += 4;
448
449 retval = stm32lx_wait_until_bsy_clear(bank);
450 if (retval != ERROR_OK)
451 goto reset_pg_and_lock;
452 }
453
454 offset += bytes_written;
455 count -= bytes_written;
456
457 /* this should always pass this check here */
458 assert((offset % 128) == 0);
459
460 /* calculate half pages */
461 halfpages_number = count / 128;
462
463 if (halfpages_number) {
464 retval = stm32lx_write_half_pages(bank, buffer + bytes_written, offset, 128 * halfpages_number);
465 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
466 /* attempt slow memory writes */
467 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
468 halfpages_number = 0;
469 } else {
470 if (retval != ERROR_OK)
471 return ERROR_FAIL;
472 }
473 }
474
475 /* write any remaining bytes */
476 uint32_t page_bytes_written = 128 * halfpages_number;
477 bytes_written += page_bytes_written;
478 address += page_bytes_written;
479 bytes_remaining = count - page_bytes_written;
480
481 retval = stm32lx_unlock_program_memory(bank);
482 if (retval != ERROR_OK)
483 return retval;
484
485 while (bytes_remaining > 0) {
486 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
487
488 /* copy remaining bytes into the write buffer */
489 uint32_t bytes_to_write = MIN(4, bytes_remaining);
490 memcpy(value, buffer + bytes_written, bytes_to_write);
491
492 retval = target_write_buffer(target, address, 4, value);
493 if (retval != ERROR_OK)
494 goto reset_pg_and_lock;
495
496 bytes_written += bytes_to_write;
497 bytes_remaining -= bytes_to_write;
498 address += 4;
499
500 retval = stm32lx_wait_until_bsy_clear(bank);
501 if (retval != ERROR_OK)
502 goto reset_pg_and_lock;
503 }
504
505 reset_pg_and_lock:
506 retval2 = stm32lx_lock_program_memory(bank);
507 if (retval == ERROR_OK)
508 retval = retval2;
509
510 return retval;
511 }
512
513 static int stm32lx_probe(struct flash_bank *bank)
514 {
515 struct target *target = bank->target;
516 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
517 int i;
518 uint16_t flash_size_in_kb;
519 uint16_t max_flash_size_in_kb;
520 uint32_t device_id;
521
522 stm32lx_info->probed = 0;
523
524 /* read stm32 device id register */
525 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
526 if (retval != ERROR_OK)
527 return retval;
528
529 LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
530
531 /* set max flash size depending on family */
532 switch (device_id & 0xfff) {
533 case 0x416:
534 max_flash_size_in_kb = 128;
535 break;
536 case 0x436:
537 max_flash_size_in_kb = 384;
538 break;
539 default:
540 LOG_WARNING("Cannot identify target as a STM32L family.");
541 return ERROR_FAIL;
542 }
543
544 /* get flash size from target. */
545 retval = target_read_u16(target, F_SIZE, &flash_size_in_kb);
546
547 /* failed reading flash size or flash size invalid (early silicon),
548 * default to max target family */
549 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
550 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
551 max_flash_size_in_kb);
552 flash_size_in_kb = max_flash_size_in_kb;
553 }
554
555 /* STM32L - we have 32 sectors, 16 pages per sector -> 512 pages
556 * 16 pages for a protection area */
557
558 /* calculate numbers of sectors (4kB per sector) */
559 int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
560 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
561
562 if (bank->sectors) {
563 free(bank->sectors);
564 bank->sectors = NULL;
565 }
566
567 bank->base = FLASH_BANK0_ADDRESS;
568 bank->size = flash_size_in_kb * 1024;
569 bank->num_sectors = num_sectors;
570 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
571 if (bank->sectors == NULL) {
572 LOG_ERROR("failed to allocate bank sectors");
573 return ERROR_FAIL;
574 }
575
576 for (i = 0; i < num_sectors; i++) {
577 bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
578 bank->sectors[i].size = FLASH_SECTOR_SIZE;
579 bank->sectors[i].is_erased = -1;
580 bank->sectors[i].is_protected = 1;
581 }
582
583 stm32lx_info->probed = 1;
584
585 return ERROR_OK;
586 }
587
588 static int stm32lx_auto_probe(struct flash_bank *bank)
589 {
590 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
591
592 if (stm32lx_info->probed)
593 return ERROR_OK;
594
595 return stm32lx_probe(bank);
596 }
597
598 static int stm32lx_erase_check(struct flash_bank *bank)
599 {
600 struct target *target = bank->target;
601 const int buffer_size = 4096;
602 int i;
603 uint32_t nBytes;
604 int retval = ERROR_OK;
605
606 if (bank->target->state != TARGET_HALTED) {
607 LOG_ERROR("Target not halted");
608 return ERROR_TARGET_NOT_HALTED;
609 }
610
611 uint8_t *buffer = malloc(buffer_size);
612 if (buffer == NULL) {
613 LOG_ERROR("failed to allocate read buffer");
614 return ERROR_FAIL;
615 }
616
617 for (i = 0; i < bank->num_sectors; i++) {
618 uint32_t j;
619 bank->sectors[i].is_erased = 1;
620
621 /* Loop chunk by chunk over the sector */
622 for (j = 0; j < bank->sectors[i].size; j += buffer_size) {
623 uint32_t chunk;
624 chunk = buffer_size;
625 if (chunk > (j - bank->sectors[i].size))
626 chunk = (j - bank->sectors[i].size);
627
628 retval = target_read_memory(target, bank->base
629 + bank->sectors[i].offset + j, 4, chunk / 4, buffer);
630 if (retval != ERROR_OK)
631 break;
632
633 for (nBytes = 0; nBytes < chunk; nBytes++) {
634 if (buffer[nBytes] != 0x00) {
635 bank->sectors[i].is_erased = 0;
636 break;
637 }
638 }
639 }
640 if (retval != ERROR_OK)
641 break;
642 }
643 free(buffer);
644
645 return retval;
646 }
647
648 static int stm32lx_get_info(struct flash_bank *bank, char *buf, int buf_size)
649 {
650 /* This method must return a string displaying information about the bank */
651
652 struct target *target = bank->target;
653 uint32_t device_id;
654 int printed;
655
656 /* read stm32 device id register */
657 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
658 if (retval != ERROR_OK)
659 return retval;
660
661 if ((device_id & 0xfff) == 0x416) {
662 printed = snprintf(buf, buf_size, "stm32lx - Rev: ");
663 buf += printed;
664 buf_size -= printed;
665
666 switch (device_id >> 16) {
667 case 0x1000:
668 snprintf(buf, buf_size, "A");
669 break;
670
671 case 0x1008:
672 snprintf(buf, buf_size, "Y");
673 break;
674
675 case 0x1018:
676 snprintf(buf, buf_size, "X");
677 break;
678
679 case 0x1038:
680 snprintf(buf, buf_size, "W");
681 break;
682
683 case 0x1078:
684 snprintf(buf, buf_size, "V");
685 break;
686
687 default:
688 snprintf(buf, buf_size, "unknown");
689 break;
690 }
691 } else if ((device_id & 0xfff) == 0x436) {
692 printed = snprintf(buf, buf_size, "stm32lx (HD) - Rev: ");
693 buf += printed;
694 buf_size -= printed;
695
696 switch (device_id >> 16) {
697 case 0x1000:
698 snprintf(buf, buf_size, "A");
699 break;
700
701 case 0x1008:
702 snprintf(buf, buf_size, "Z");
703 break;
704
705 case 0x1018:
706 snprintf(buf, buf_size, "Y");
707 break;
708
709 default:
710 snprintf(buf, buf_size, "unknown");
711 break;
712 }
713 } else {
714 snprintf(buf, buf_size, "Cannot identify target as a stm32lx");
715 return ERROR_FAIL;
716 }
717
718 return ERROR_OK;
719 }
720
721 static const struct command_registration stm32lx_exec_command_handlers[] = {
722 COMMAND_REGISTRATION_DONE
723 };
724
725 static const struct command_registration stm32lx_command_handlers[] = {
726 {
727 .name = "stm32lx",
728 .mode = COMMAND_ANY,
729 .help = "stm32lx flash command group",
730 .usage = "",
731 .chain = stm32lx_exec_command_handlers,
732 },
733 COMMAND_REGISTRATION_DONE
734 };
735
736 struct flash_driver stm32lx_flash = {
737 .name = "stm32lx",
738 .commands = stm32lx_command_handlers,
739 .flash_bank_command = stm32lx_flash_bank_command,
740 .erase = stm32lx_erase,
741 .protect = stm32lx_protect,
742 .write = stm32lx_write,
743 .read = default_flash_read,
744 .probe = stm32lx_probe,
745 .auto_probe = stm32lx_auto_probe,
746 .erase_check = stm32lx_erase_check,
747 .protect_check = stm32lx_protect_check,
748 .info = stm32lx_get_info,
749 };
750
751 /* Static methods implementation */
752 static int stm32lx_unlock_program_memory(struct flash_bank *bank)
753 {
754 struct target *target = bank->target;
755 int retval;
756 uint32_t reg32;
757
758 /*
759 * Unlocking the program memory is done by unlocking the PECR,
760 * then by writing the 2 PRGKEY to the PRGKEYR register
761 */
762
763 /* check flash is not already unlocked */
764 retval = target_read_u32(target, FLASH_PECR, &reg32);
765 if (retval != ERROR_OK)
766 return retval;
767
768 if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
769 return ERROR_OK;
770
771 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
772 retval = target_write_u32(target, FLASH_PEKEYR, PEKEY1);
773 if (retval != ERROR_OK)
774 return retval;
775
776 retval = target_write_u32(target, FLASH_PEKEYR, PEKEY2);
777 if (retval != ERROR_OK)
778 return retval;
779
780 /* Make sure it worked */
781 retval = target_read_u32(target, FLASH_PECR, &reg32);
782 if (retval != ERROR_OK)
783 return retval;
784
785 if (reg32 & FLASH_PECR__PELOCK) {
786 LOG_ERROR("PELOCK is not cleared :(");
787 return ERROR_FLASH_OPERATION_FAILED;
788 }
789
790 retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY1);
791 if (retval != ERROR_OK)
792 return retval;
793 retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY2);
794 if (retval != ERROR_OK)
795 return retval;
796
797 /* Make sure it worked */
798 retval = target_read_u32(target, FLASH_PECR, &reg32);
799 if (retval != ERROR_OK)
800 return retval;
801
802 if (reg32 & FLASH_PECR__PRGLOCK) {
803 LOG_ERROR("PRGLOCK is not cleared :(");
804 return ERROR_FLASH_OPERATION_FAILED;
805 }
806
807 return ERROR_OK;
808 }
809
810 static int stm32lx_enable_write_half_page(struct flash_bank *bank)
811 {
812 struct target *target = bank->target;
813 int retval;
814 uint32_t reg32;
815
816 /**
817 * Unlock the program memory, then set the FPRG bit in the PECR register.
818 */
819 retval = stm32lx_unlock_program_memory(bank);
820 if (retval != ERROR_OK)
821 return retval;
822
823 retval = target_read_u32(target, FLASH_PECR, &reg32);
824 if (retval != ERROR_OK)
825 return retval;
826
827 reg32 |= FLASH_PECR__FPRG;
828 retval = target_write_u32(target, FLASH_PECR, reg32);
829 if (retval != ERROR_OK)
830 return retval;
831
832 retval = target_read_u32(target, FLASH_PECR, &reg32);
833 if (retval != ERROR_OK)
834 return retval;
835
836 reg32 |= FLASH_PECR__PROG;
837 retval = target_write_u32(target, FLASH_PECR, reg32);
838
839 return retval;
840 }
841
842 static int stm32lx_lock_program_memory(struct flash_bank *bank)
843 {
844 struct target *target = bank->target;
845 int retval;
846 uint32_t reg32;
847
848 /* To lock the program memory, simply set the lock bit and lock PECR */
849
850 retval = target_read_u32(target, FLASH_PECR, &reg32);
851 if (retval != ERROR_OK)
852 return retval;
853
854 reg32 |= FLASH_PECR__PRGLOCK;
855 retval = target_write_u32(target, FLASH_PECR, reg32);
856 if (retval != ERROR_OK)
857 return retval;
858
859 retval = target_read_u32(target, FLASH_PECR, &reg32);
860 if (retval != ERROR_OK)
861 return retval;
862
863 reg32 |= FLASH_PECR__PELOCK;
864 retval = target_write_u32(target, FLASH_PECR, reg32);
865 if (retval != ERROR_OK)
866 return retval;
867
868 return ERROR_OK;
869 }
870
871 static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
872 {
873 struct target *target = bank->target;
874 int retval;
875 uint32_t reg32;
876
877 /*
878 * To erase a sector (i.e. FLASH_PAGES_PER_SECTOR pages),
879 * first unlock the memory, loop over the pages of this sector
880 * and write 0x0 to its first word.
881 */
882
883 retval = stm32lx_unlock_program_memory(bank);
884 if (retval != ERROR_OK)
885 return retval;
886
887 for (int page = 0; page < FLASH_PAGES_PER_SECTOR; page++) {
888 reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
889 retval = target_write_u32(target, FLASH_PECR, reg32);
890 if (retval != ERROR_OK)
891 return retval;
892
893 retval = stm32lx_wait_until_bsy_clear(bank);
894 if (retval != ERROR_OK)
895 return retval;
896
897 uint32_t addr = bank->base + bank->sectors[sector].offset + (page
898 * FLASH_PAGE_SIZE);
899 retval = target_write_u32(target, addr, 0x0);
900 if (retval != ERROR_OK)
901 return retval;
902
903 retval = stm32lx_wait_until_bsy_clear(bank);
904 if (retval != ERROR_OK)
905 return retval;
906 }
907
908 retval = stm32lx_lock_program_memory(bank);
909 if (retval != ERROR_OK)
910 return retval;
911
912 return ERROR_OK;
913 }
914
915 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
916 {
917 struct target *target = bank->target;
918 uint32_t status;
919 int retval = ERROR_OK;
920 int timeout = 100;
921
922 /* wait for busy to clear */
923 for (;;) {
924 retval = target_read_u32(target, FLASH_SR, &status);
925 if (retval != ERROR_OK)
926 return retval;
927
928 if ((status & FLASH_SR__BSY) == 0)
929 break;
930 if (timeout-- <= 0) {
931 LOG_ERROR("timed out waiting for flash");
932 return ERROR_FAIL;
933 }
934 alive_sleep(1);
935 }
936
937 if (status & FLASH_SR__WRPERR) {
938 LOG_ERROR("access denied / write protected");
939 retval = ERROR_FAIL;
940 }
941
942 if (status & FLASH_SR__PGAERR) {
943 LOG_ERROR("invalid program address");
944 retval = ERROR_FAIL;
945 }
946
947 return retval;
948 }
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