1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ***************************************************************************/
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35 #include <target/cortex_m.h>
37 /* stm32lx flash register locations */
39 #define FLASH_ACR 0x00
40 #define FLASH_PECR 0x04
41 #define FLASH_PDKEYR 0x08
42 #define FLASH_PEKEYR 0x0C
43 #define FLASH_PRGKEYR 0x10
44 #define FLASH_OPTKEYR 0x14
46 #define FLASH_OBR 0x1C
47 #define FLASH_WRPR 0x20
50 #define FLASH_ACR__LATENCY (1<<0)
51 #define FLASH_ACR__PRFTEN (1<<1)
52 #define FLASH_ACR__ACC64 (1<<2)
53 #define FLASH_ACR__SLEEP_PD (1<<3)
54 #define FLASH_ACR__RUN_PD (1<<4)
57 #define FLASH_PECR__PELOCK (1<<0)
58 #define FLASH_PECR__PRGLOCK (1<<1)
59 #define FLASH_PECR__OPTLOCK (1<<2)
60 #define FLASH_PECR__PROG (1<<3)
61 #define FLASH_PECR__DATA (1<<4)
62 #define FLASH_PECR__FTDW (1<<8)
63 #define FLASH_PECR__ERASE (1<<9)
64 #define FLASH_PECR__FPRG (1<<10)
65 #define FLASH_PECR__EOPIE (1<<16)
66 #define FLASH_PECR__ERRIE (1<<17)
67 #define FLASH_PECR__OBL_LAUNCH (1<<18)
70 #define FLASH_SR__BSY (1<<0)
71 #define FLASH_SR__EOP (1<<1)
72 #define FLASH_SR__ENDHV (1<<2)
73 #define FLASH_SR__READY (1<<3)
74 #define FLASH_SR__WRPERR (1<<8)
75 #define FLASH_SR__PGAERR (1<<9)
76 #define FLASH_SR__SIZERR (1<<10)
77 #define FLASH_SR__OPTVERR (1<<11)
80 #define PEKEY1 0x89ABCDEF
81 #define PEKEY2 0x02030405
82 #define PRGKEY1 0x8C9DAEBF
83 #define PRGKEY2 0x13141516
84 #define OPTKEY1 0xFBEAD9C8
85 #define OPTKEY2 0x24252627
88 #define DBGMCU_IDCODE 0xE0042000
89 #define DBGMCU_IDCODE_L0 0x40015800
92 #define FLASH_SECTOR_SIZE 4096
93 #define FLASH_BANK0_ADDRESS 0x08000000
95 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
);
96 static int stm32lx_lock_program_memory(struct flash_bank
*bank
);
97 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
);
98 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
);
99 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
);
106 struct stm32lx_part_info
{
108 const char *device_str
;
109 const struct stm32lx_rev
*revs
;
111 unsigned int page_size
;
112 unsigned int pages_per_sector
;
113 uint16_t max_flash_size_kb
;
114 uint16_t first_bank_size_kb
; /* used when has_dual_banks is true */
117 uint32_t flash_base
; /* Flash controller registers location */
118 uint32_t fsize_base
; /* Location of FSIZE register */
121 struct stm32lx_flash_bank
{
124 uint32_t user_bank_size
;
127 const struct stm32lx_part_info
*part_info
;
130 static const struct stm32lx_rev stm32_416_revs
[] = {
131 { 0x1000, "A" }, { 0x1008, "Y" }, { 0x1018, "X" }, { 0x1038, "W" },
134 static const struct stm32lx_rev stm32_417_revs
[] = {
135 { 0x1000, "A" }, { 0x1008, "Z" },
137 static const struct stm32lx_rev stm32_427_revs
[] = {
140 static const struct stm32lx_rev stm32_436_revs
[] = {
141 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" },
144 static const struct stm32lx_part_info stm32lx_parts
[] = {
147 .revs
= stm32_416_revs
,
148 .num_revs
= ARRAY_SIZE(stm32_416_revs
),
149 .device_str
= "STM32L1xx (Low/Medium Density)",
151 .pages_per_sector
= 16,
152 .max_flash_size_kb
= 128,
153 .has_dual_banks
= false,
154 .flash_base
= 0x40023C00,
155 .fsize_base
= 0x1FF8004C,
159 .revs
= stm32_417_revs
,
160 .num_revs
= ARRAY_SIZE(stm32_417_revs
),
161 .device_str
= "STM32L0xx",
163 .pages_per_sector
= 32,
164 .max_flash_size_kb
= 64,
165 .has_dual_banks
= false,
166 .flash_base
= 0x40022000,
167 .fsize_base
= 0x1FF8007C,
171 .revs
= stm32_427_revs
,
172 .num_revs
= ARRAY_SIZE(stm32_427_revs
),
173 .device_str
= "STM32L1xx (Medium+ Density)",
175 .pages_per_sector
= 16,
176 .max_flash_size_kb
= 256,
177 .first_bank_size_kb
= 192,
178 .has_dual_banks
= true,
179 .flash_base
= 0x40023C00,
180 .fsize_base
= 0x1FF800CC,
184 .revs
= stm32_436_revs
,
185 .num_revs
= ARRAY_SIZE(stm32_436_revs
),
186 .device_str
= "STM32L1xx (Medium+/High Density)",
188 .pages_per_sector
= 16,
189 .max_flash_size_kb
= 384,
190 .first_bank_size_kb
= 192,
191 .has_dual_banks
= true,
192 .flash_base
= 0x40023C00,
193 .fsize_base
= 0x1FF800CC,
197 .device_str
= "STM32L1xx (Medium+/High Density)",
199 .pages_per_sector
= 16,
200 .max_flash_size_kb
= 512,
201 .first_bank_size_kb
= 256,
202 .has_dual_banks
= true,
203 .flash_base
= 0x40023C00,
204 .fsize_base
= 0x1FF800CC,
208 /* flash bank stm32lx <base> <size> 0 0 <target#>
210 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command
)
212 struct stm32lx_flash_bank
*stm32lx_info
;
214 return ERROR_COMMAND_SYNTAX_ERROR
;
216 /* Create the bank structure */
217 stm32lx_info
= malloc(sizeof(struct stm32lx_flash_bank
));
219 /* Check allocation */
220 if (stm32lx_info
== NULL
) {
221 LOG_ERROR("failed to allocate bank structure");
225 bank
->driver_priv
= stm32lx_info
;
227 stm32lx_info
->probed
= 0;
228 stm32lx_info
->user_bank_size
= bank
->size
;
230 /* the stm32l erased value is 0x00 */
231 bank
->default_padded_value
= 0x00;
236 static int stm32lx_protect_check(struct flash_bank
*bank
)
239 struct target
*target
= bank
->target
;
240 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
245 * Read the WRPR word, and check each bit (corresponding to each
248 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_WRPR
,
250 if (retval
!= ERROR_OK
)
253 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
255 bank
->sectors
[i
].is_protected
= 1;
257 bank
->sectors
[i
].is_protected
= 0;
262 static int stm32lx_erase(struct flash_bank
*bank
, int first
, int last
)
267 * It could be possible to do a mass erase if all sectors must be
268 * erased, but it is not implemented yet.
271 if (bank
->target
->state
!= TARGET_HALTED
) {
272 LOG_ERROR("Target not halted");
273 return ERROR_TARGET_NOT_HALTED
;
277 * Loop over the selected sectors and erase them
279 for (int i
= first
; i
<= last
; i
++) {
280 retval
= stm32lx_erase_sector(bank
, i
);
281 if (retval
!= ERROR_OK
)
283 bank
->sectors
[i
].is_erased
= 1;
288 static int stm32lx_protect(struct flash_bank
*bank
, int set
, int first
,
291 LOG_WARNING("protection of the STM32L flash is not implemented");
295 static int stm32lx_write_half_pages(struct flash_bank
*bank
, const uint8_t *buffer
,
296 uint32_t offset
, uint32_t count
)
298 struct target
*target
= bank
->target
;
299 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
301 uint32_t hp_nb
= stm32lx_info
->part_info
->page_size
/ 2;
302 uint32_t buffer_size
= 16384;
303 struct working_area
*write_algorithm
;
304 struct working_area
*source
;
305 uint32_t address
= bank
->base
+ offset
;
307 struct reg_param reg_params
[3];
308 struct armv7m_algorithm armv7m_info
;
310 int retval
= ERROR_OK
;
312 /* see contib/loaders/flash/stm32lx.S for src */
314 static const uint8_t stm32lx_flash_write_code
[] = {
316 0x00, 0x23, /* movs r3, #0 */
317 0x04, 0xe0, /* b test_done */
320 0x51, 0xf8, 0x04, 0xcb, /* ldr ip, [r1], #4 */
321 0x40, 0xf8, 0x04, 0xcb, /* str ip, [r0], #4 */
322 0x01, 0x33, /* adds r3, #1 */
325 0x93, 0x42, /* cmp r3, r2 */
326 0xf8, 0xd3, /* bcc write_word */
327 0x00, 0xbe, /* bkpt 0 */
331 /* Make sure we're performing a half-page aligned write. */
333 LOG_ERROR("The byte count must be %" PRIu32
"B-aligned but count is %" PRIi32
"B)", hp_nb
, count
);
337 /* flash write code */
338 if (target_alloc_working_area(target
, sizeof(stm32lx_flash_write_code
),
339 &write_algorithm
) != ERROR_OK
) {
340 LOG_DEBUG("no working area for block memory writes");
341 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
344 /* Write the flashing code */
345 retval
= target_write_buffer(target
,
346 write_algorithm
->address
,
347 sizeof(stm32lx_flash_write_code
),
348 stm32lx_flash_write_code
);
349 if (retval
!= ERROR_OK
) {
350 target_free_working_area(target
, write_algorithm
);
354 /* Allocate half pages memory */
355 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
356 if (buffer_size
> 1024)
361 if (buffer_size
<= stm32lx_info
->part_info
->page_size
) {
362 /* we already allocated the writing code, but failed to get a
363 * buffer, free the algorithm */
364 target_free_working_area(target
, write_algorithm
);
366 LOG_WARNING("no large enough working area available, can't do block memory writes");
367 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
371 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
372 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
373 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
374 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
375 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
377 /* Enable half-page write */
378 retval
= stm32lx_enable_write_half_page(bank
);
379 if (retval
!= ERROR_OK
) {
380 target_free_working_area(target
, source
);
381 target_free_working_area(target
, write_algorithm
);
383 destroy_reg_param(®_params
[0]);
384 destroy_reg_param(®_params
[1]);
385 destroy_reg_param(®_params
[2]);
389 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
390 if (armv7m
== NULL
) {
392 /* something is very wrong if armv7m is NULL */
393 LOG_ERROR("unable to get armv7m target");
397 /* save any DEMCR flags and configure target to catch any Hard Faults */
398 uint32_t demcr_save
= armv7m
->demcr
;
399 armv7m
->demcr
= VC_HARDERR
;
401 /* Loop while there are bytes to write */
404 this_count
= (count
> buffer_size
) ? buffer_size
: count
;
406 /* Write the next half pages */
407 retval
= target_write_buffer(target
, source
->address
, this_count
, buffer
);
408 if (retval
!= ERROR_OK
)
411 /* 4: Store useful information in the registers */
412 /* the destination address of the copy (R0) */
413 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
414 /* The source address of the copy (R1) */
415 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
416 /* The length of the copy (R2) */
417 buf_set_u32(reg_params
[2].value
, 0, 32, this_count
/ 4);
419 /* 5: Execute the bunch of code */
420 retval
= target_run_algorithm(target
, 0, NULL
, sizeof(reg_params
)
421 / sizeof(*reg_params
), reg_params
,
422 write_algorithm
->address
, 0, 10000, &armv7m_info
);
423 if (retval
!= ERROR_OK
)
426 /* check for Hard Fault */
427 if (armv7m
->exception_number
== 3)
430 /* 6: Wait while busy */
431 retval
= stm32lx_wait_until_bsy_clear(bank
);
432 if (retval
!= ERROR_OK
)
435 buffer
+= this_count
;
436 address
+= this_count
;
440 /* restore previous flags */
441 armv7m
->demcr
= demcr_save
;
443 if (armv7m
->exception_number
== 3) {
445 /* the stm32l15x devices seem to have an issue when blank.
446 * if a ram loader is executed on a blank device it will
447 * Hard Fault, this issue does not happen for a already programmed device.
448 * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
449 * The workaround of handling the Hard Fault exception does work, but makes the
450 * loader more complicated, as a compromise we manually write the pages, programming time
451 * is reduced by 50% using this slower method.
454 LOG_WARNING("couldn't use loader, falling back to page memory writes");
458 this_count
= (count
> hp_nb
) ? hp_nb
: count
;
460 /* Write the next half pages */
461 retval
= target_write_buffer(target
, address
, this_count
, buffer
);
462 if (retval
!= ERROR_OK
)
465 /* Wait while busy */
466 retval
= stm32lx_wait_until_bsy_clear(bank
);
467 if (retval
!= ERROR_OK
)
470 buffer
+= this_count
;
471 address
+= this_count
;
476 if (retval
== ERROR_OK
)
477 retval
= stm32lx_lock_program_memory(bank
);
479 target_free_working_area(target
, source
);
480 target_free_working_area(target
, write_algorithm
);
482 destroy_reg_param(®_params
[0]);
483 destroy_reg_param(®_params
[1]);
484 destroy_reg_param(®_params
[2]);
489 static int stm32lx_write(struct flash_bank
*bank
, const uint8_t *buffer
,
490 uint32_t offset
, uint32_t count
)
492 struct target
*target
= bank
->target
;
493 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
495 uint32_t hp_nb
= stm32lx_info
->part_info
->page_size
/ 2;
496 uint32_t halfpages_number
;
497 uint32_t bytes_remaining
= 0;
498 uint32_t address
= bank
->base
+ offset
;
499 uint32_t bytes_written
= 0;
502 if (bank
->target
->state
!= TARGET_HALTED
) {
503 LOG_ERROR("Target not halted");
504 return ERROR_TARGET_NOT_HALTED
;
508 LOG_ERROR("offset 0x%" PRIx32
" breaks required 4-byte alignment", offset
);
509 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
512 retval
= stm32lx_unlock_program_memory(bank
);
513 if (retval
!= ERROR_OK
)
516 /* first we need to write any unaligned head bytes upto
517 * the next 128 byte page */
520 bytes_remaining
= MIN(count
, hp_nb
- (offset
% hp_nb
));
522 while (bytes_remaining
> 0) {
523 uint8_t value
[4] = {0xff, 0xff, 0xff, 0xff};
525 /* copy remaining bytes into the write buffer */
526 uint32_t bytes_to_write
= MIN(4, bytes_remaining
);
527 memcpy(value
, buffer
+ bytes_written
, bytes_to_write
);
529 retval
= target_write_buffer(target
, address
, 4, value
);
530 if (retval
!= ERROR_OK
)
531 goto reset_pg_and_lock
;
533 bytes_written
+= bytes_to_write
;
534 bytes_remaining
-= bytes_to_write
;
537 retval
= stm32lx_wait_until_bsy_clear(bank
);
538 if (retval
!= ERROR_OK
)
539 goto reset_pg_and_lock
;
542 offset
+= bytes_written
;
543 count
-= bytes_written
;
545 /* this should always pass this check here */
546 assert((offset
% hp_nb
) == 0);
548 /* calculate half pages */
549 halfpages_number
= count
/ hp_nb
;
551 if (halfpages_number
) {
552 retval
= stm32lx_write_half_pages(bank
, buffer
+ bytes_written
, offset
, hp_nb
* halfpages_number
);
553 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
554 /* attempt slow memory writes */
555 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
556 halfpages_number
= 0;
558 if (retval
!= ERROR_OK
)
563 /* write any remaining bytes */
564 uint32_t page_bytes_written
= hp_nb
* halfpages_number
;
565 bytes_written
+= page_bytes_written
;
566 address
+= page_bytes_written
;
567 bytes_remaining
= count
- page_bytes_written
;
569 retval
= stm32lx_unlock_program_memory(bank
);
570 if (retval
!= ERROR_OK
)
573 while (bytes_remaining
> 0) {
574 uint8_t value
[4] = {0xff, 0xff, 0xff, 0xff};
576 /* copy remaining bytes into the write buffer */
577 uint32_t bytes_to_write
= MIN(4, bytes_remaining
);
578 memcpy(value
, buffer
+ bytes_written
, bytes_to_write
);
580 retval
= target_write_buffer(target
, address
, 4, value
);
581 if (retval
!= ERROR_OK
)
582 goto reset_pg_and_lock
;
584 bytes_written
+= bytes_to_write
;
585 bytes_remaining
-= bytes_to_write
;
588 retval
= stm32lx_wait_until_bsy_clear(bank
);
589 if (retval
!= ERROR_OK
)
590 goto reset_pg_and_lock
;
594 retval2
= stm32lx_lock_program_memory(bank
);
595 if (retval
== ERROR_OK
)
601 static int stm32lx_read_id_code(struct target
*target
, uint32_t *id
)
603 /* read stm32 device id register */
604 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, id
);
605 if (retval
!= ERROR_OK
)
608 /* STM32L0 parts will have 0 there, try reading the L0's location for
609 * DBG_IDCODE in case this is an L0 part. */
611 retval
= target_read_u32(target
, DBGMCU_IDCODE_L0
, id
);
616 static int stm32lx_probe(struct flash_bank
*bank
)
618 struct target
*target
= bank
->target
;
619 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
621 uint16_t flash_size_in_kb
;
623 uint32_t base_address
= FLASH_BANK0_ADDRESS
;
624 uint32_t second_bank_base
;
626 stm32lx_info
->probed
= 0;
628 int retval
= stm32lx_read_id_code(bank
->target
, &device_id
);
629 if (retval
!= ERROR_OK
)
632 stm32lx_info
->idcode
= device_id
;
634 LOG_DEBUG("device id = 0x%08" PRIx32
"", device_id
);
636 for (unsigned int n
= 0; n
< ARRAY_SIZE(stm32lx_parts
); n
++) {
637 if ((device_id
& 0xfff) == stm32lx_parts
[n
].id
)
638 stm32lx_info
->part_info
= &stm32lx_parts
[n
];
641 if (!stm32lx_info
->part_info
) {
642 LOG_WARNING("Cannot identify target as a STM32L family.");
646 stm32lx_info
->flash_base
= stm32lx_info
->part_info
->flash_base
;
648 /* Get the flash size from target. */
649 retval
= target_read_u16(target
, stm32lx_info
->part_info
->fsize_base
,
652 /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
653 * or 256K, respectively. Please see RM0038 r8 or newer and refer to
655 if (retval
== ERROR_OK
&& (device_id
& 0xfff) == 0x436) {
656 if (flash_size_in_kb
== 0)
657 flash_size_in_kb
= 384;
658 else if (flash_size_in_kb
== 1)
659 flash_size_in_kb
= 256;
662 /* Failed reading flash size or flash size invalid (early silicon),
663 * default to max target family */
664 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
665 LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
666 stm32lx_info
->part_info
->max_flash_size_kb
);
667 flash_size_in_kb
= stm32lx_info
->part_info
->max_flash_size_kb
;
668 } else if (flash_size_in_kb
> stm32lx_info
->part_info
->max_flash_size_kb
) {
669 LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
670 flash_size_in_kb
, stm32lx_info
->part_info
->max_flash_size_kb
,
671 stm32lx_info
->part_info
->max_flash_size_kb
);
672 flash_size_in_kb
= stm32lx_info
->part_info
->max_flash_size_kb
;
675 if (stm32lx_info
->part_info
->has_dual_banks
) {
676 /* Use the configured base address to determine if this is the first or second flash bank.
677 * Verify that the base address is reasonably correct and determine the flash bank size
679 second_bank_base
= base_address
+
680 stm32lx_info
->part_info
->first_bank_size_kb
* 1024;
681 if (bank
->base
== second_bank_base
) {
682 /* This is the second bank */
683 base_address
= second_bank_base
;
684 flash_size_in_kb
= flash_size_in_kb
-
685 stm32lx_info
->part_info
->first_bank_size_kb
;
686 } else if (bank
->base
== 0 || bank
->base
== base_address
) {
687 /* This is the first bank */
688 flash_size_in_kb
= stm32lx_info
->part_info
->first_bank_size_kb
;
690 LOG_WARNING("STM32L flash bank base address config is incorrect."
691 " 0x%" PRIx32
" but should rather be 0x%" PRIx32
" or 0x%" PRIx32
,
692 bank
->base
, base_address
, second_bank_base
);
695 LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32
,
696 bank
->bank_number
, flash_size_in_kb
, base_address
);
698 LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32
, flash_size_in_kb
, base_address
);
701 /* if the user sets the size manually then ignore the probed value
702 * this allows us to work around devices that have a invalid flash size register value */
703 if (stm32lx_info
->user_bank_size
) {
704 flash_size_in_kb
= stm32lx_info
->user_bank_size
/ 1024;
705 LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb
);
708 /* calculate numbers of sectors (4kB per sector) */
709 int num_sectors
= (flash_size_in_kb
* 1024) / FLASH_SECTOR_SIZE
;
713 bank
->sectors
= NULL
;
716 bank
->size
= flash_size_in_kb
* 1024;
717 bank
->base
= base_address
;
718 bank
->num_sectors
= num_sectors
;
719 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
720 if (bank
->sectors
== NULL
) {
721 LOG_ERROR("failed to allocate bank sectors");
725 for (i
= 0; i
< num_sectors
; i
++) {
726 bank
->sectors
[i
].offset
= i
* FLASH_SECTOR_SIZE
;
727 bank
->sectors
[i
].size
= FLASH_SECTOR_SIZE
;
728 bank
->sectors
[i
].is_erased
= -1;
729 bank
->sectors
[i
].is_protected
= 1;
732 stm32lx_info
->probed
= 1;
737 static int stm32lx_auto_probe(struct flash_bank
*bank
)
739 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
741 if (stm32lx_info
->probed
)
744 return stm32lx_probe(bank
);
747 static int stm32lx_erase_check(struct flash_bank
*bank
)
749 struct target
*target
= bank
->target
;
750 const int buffer_size
= 4096;
753 int retval
= ERROR_OK
;
755 if (bank
->target
->state
!= TARGET_HALTED
) {
756 LOG_ERROR("Target not halted");
757 return ERROR_TARGET_NOT_HALTED
;
760 uint8_t *buffer
= malloc(buffer_size
);
761 if (buffer
== NULL
) {
762 LOG_ERROR("failed to allocate read buffer");
766 for (i
= 0; i
< bank
->num_sectors
; i
++) {
768 bank
->sectors
[i
].is_erased
= 1;
770 /* Loop chunk by chunk over the sector */
771 for (j
= 0; j
< bank
->sectors
[i
].size
; j
+= buffer_size
) {
774 if (chunk
> (j
- bank
->sectors
[i
].size
))
775 chunk
= (j
- bank
->sectors
[i
].size
);
777 retval
= target_read_memory(target
, bank
->base
778 + bank
->sectors
[i
].offset
+ j
, 4, chunk
/ 4, buffer
);
779 if (retval
!= ERROR_OK
)
782 for (nBytes
= 0; nBytes
< chunk
; nBytes
++) {
783 if (buffer
[nBytes
] != 0x00) {
784 bank
->sectors
[i
].is_erased
= 0;
789 if (retval
!= ERROR_OK
)
797 /* This method must return a string displaying information about the bank */
798 static int stm32lx_get_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
800 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
802 if (!stm32lx_info
->probed
) {
803 int retval
= stm32lx_probe(bank
);
804 if (retval
!= ERROR_OK
) {
805 snprintf(buf
, buf_size
,
806 "Unable to find bank information.");
812 const struct stm32lx_part_info
*info
= stm32lx_info
->part_info
;
815 const char *rev_str
= NULL
;
816 uint16_t rev_id
= stm32lx_info
->idcode
>> 16;
818 for (unsigned int i
= 0; i
< info
->num_revs
; i
++)
819 if (rev_id
== info
->revs
[i
].rev
)
820 rev_str
= info
->revs
[i
].str
;
822 if (rev_str
!= NULL
) {
823 snprintf(buf
, buf_size
,
825 stm32lx_info
->part_info
->device_str
, rev_str
);
827 snprintf(buf
, buf_size
,
828 "%s - Rev: unknown (0x%04x)",
829 stm32lx_info
->part_info
->device_str
, rev_id
);
834 snprintf(buf
, buf_size
, "Cannot identify target as a STM32Lx");
840 static const struct command_registration stm32lx_exec_command_handlers
[] = {
841 COMMAND_REGISTRATION_DONE
844 static const struct command_registration stm32lx_command_handlers
[] = {
848 .help
= "stm32lx flash command group",
850 .chain
= stm32lx_exec_command_handlers
,
852 COMMAND_REGISTRATION_DONE
855 struct flash_driver stm32lx_flash
= {
857 .commands
= stm32lx_command_handlers
,
858 .flash_bank_command
= stm32lx_flash_bank_command
,
859 .erase
= stm32lx_erase
,
860 .protect
= stm32lx_protect
,
861 .write
= stm32lx_write
,
862 .read
= default_flash_read
,
863 .probe
= stm32lx_probe
,
864 .auto_probe
= stm32lx_auto_probe
,
865 .erase_check
= stm32lx_erase_check
,
866 .protect_check
= stm32lx_protect_check
,
867 .info
= stm32lx_get_info
,
870 /* Static methods implementation */
871 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
)
873 struct target
*target
= bank
->target
;
874 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
879 * Unlocking the program memory is done by unlocking the PECR,
880 * then by writing the 2 PRGKEY to the PRGKEYR register
883 /* check flash is not already unlocked */
884 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
886 if (retval
!= ERROR_OK
)
889 if ((reg32
& FLASH_PECR__PRGLOCK
) == 0)
892 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
893 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
,
895 if (retval
!= ERROR_OK
)
898 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
,
900 if (retval
!= ERROR_OK
)
903 /* Make sure it worked */
904 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
906 if (retval
!= ERROR_OK
)
909 if (reg32
& FLASH_PECR__PELOCK
) {
910 LOG_ERROR("PELOCK is not cleared :(");
911 return ERROR_FLASH_OPERATION_FAILED
;
914 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PRGKEYR
,
916 if (retval
!= ERROR_OK
)
918 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PRGKEYR
,
920 if (retval
!= ERROR_OK
)
923 /* Make sure it worked */
924 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
926 if (retval
!= ERROR_OK
)
929 if (reg32
& FLASH_PECR__PRGLOCK
) {
930 LOG_ERROR("PRGLOCK is not cleared :(");
931 return ERROR_FLASH_OPERATION_FAILED
;
937 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
)
939 struct target
*target
= bank
->target
;
940 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
945 * Unlock the program memory, then set the FPRG bit in the PECR register.
947 retval
= stm32lx_unlock_program_memory(bank
);
948 if (retval
!= ERROR_OK
)
951 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
953 if (retval
!= ERROR_OK
)
956 reg32
|= FLASH_PECR__FPRG
;
957 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
959 if (retval
!= ERROR_OK
)
962 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
964 if (retval
!= ERROR_OK
)
967 reg32
|= FLASH_PECR__PROG
;
968 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
974 static int stm32lx_lock_program_memory(struct flash_bank
*bank
)
976 struct target
*target
= bank
->target
;
977 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
981 /* To lock the program memory, simply set the lock bit and lock PECR */
983 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
985 if (retval
!= ERROR_OK
)
988 reg32
|= FLASH_PECR__PRGLOCK
;
989 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
991 if (retval
!= ERROR_OK
)
994 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
996 if (retval
!= ERROR_OK
)
999 reg32
|= FLASH_PECR__PELOCK
;
1000 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1002 if (retval
!= ERROR_OK
)
1008 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
)
1010 struct target
*target
= bank
->target
;
1011 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1016 * To erase a sector (i.e. stm32lx_info->part_info.pages_per_sector pages),
1017 * first unlock the memory, loop over the pages of this sector
1018 * and write 0x0 to its first word.
1021 retval
= stm32lx_unlock_program_memory(bank
);
1022 if (retval
!= ERROR_OK
)
1025 for (int page
= 0; page
< (int)stm32lx_info
->part_info
->pages_per_sector
;
1027 reg32
= FLASH_PECR__PROG
| FLASH_PECR__ERASE
;
1028 retval
= target_write_u32(target
,
1029 stm32lx_info
->flash_base
+ FLASH_PECR
, reg32
);
1030 if (retval
!= ERROR_OK
)
1033 retval
= stm32lx_wait_until_bsy_clear(bank
);
1034 if (retval
!= ERROR_OK
)
1037 uint32_t addr
= bank
->base
+ bank
->sectors
[sector
].offset
+ (page
1038 * stm32lx_info
->part_info
->page_size
);
1039 retval
= target_write_u32(target
, addr
, 0x0);
1040 if (retval
!= ERROR_OK
)
1043 retval
= stm32lx_wait_until_bsy_clear(bank
);
1044 if (retval
!= ERROR_OK
)
1048 retval
= stm32lx_lock_program_memory(bank
);
1049 if (retval
!= ERROR_OK
)
1055 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
)
1057 struct target
*target
= bank
->target
;
1058 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1060 int retval
= ERROR_OK
;
1063 /* wait for busy to clear */
1065 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_SR
,
1067 if (retval
!= ERROR_OK
)
1070 if ((status
& FLASH_SR__BSY
) == 0)
1072 if (timeout
-- <= 0) {
1073 LOG_ERROR("timed out waiting for flash");
1079 if (status
& FLASH_SR__WRPERR
) {
1080 LOG_ERROR("access denied / write protected");
1081 retval
= ERROR_FAIL
;
1084 if (status
& FLASH_SR__PGAERR
) {
1085 LOG_ERROR("invalid program address");
1086 retval
= ERROR_FAIL
;
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