Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
stm32: enable flash bank size override
[openocd.git] / src / flash / nor / stm32lx.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35 #include <target/cortex_m.h>
36
37 /* stm32lx flash register locations */
38
39 #define FLASH_BASE 0x40023C00
40 #define FLASH_ACR 0x40023C00
41 #define FLASH_PECR 0x40023C04
42 #define FLASH_PDKEYR 0x40023C08
43 #define FLASH_PEKEYR 0x40023C0C
44 #define FLASH_PRGKEYR 0x40023C10
45 #define FLASH_OPTKEYR 0x40023C14
46 #define FLASH_SR 0x40023C18
47 #define FLASH_OBR 0x40023C1C
48 #define FLASH_WRPR 0x40023C20
49
50 /* FLASH_ACR bites */
51 #define FLASH_ACR__LATENCY (1<<0)
52 #define FLASH_ACR__PRFTEN (1<<1)
53 #define FLASH_ACR__ACC64 (1<<2)
54 #define FLASH_ACR__SLEEP_PD (1<<3)
55 #define FLASH_ACR__RUN_PD (1<<4)
56
57 /* FLASH_PECR bits */
58 #define FLASH_PECR__PELOCK (1<<0)
59 #define FLASH_PECR__PRGLOCK (1<<1)
60 #define FLASH_PECR__OPTLOCK (1<<2)
61 #define FLASH_PECR__PROG (1<<3)
62 #define FLASH_PECR__DATA (1<<4)
63 #define FLASH_PECR__FTDW (1<<8)
64 #define FLASH_PECR__ERASE (1<<9)
65 #define FLASH_PECR__FPRG (1<<10)
66 #define FLASH_PECR__EOPIE (1<<16)
67 #define FLASH_PECR__ERRIE (1<<17)
68 #define FLASH_PECR__OBL_LAUNCH (1<<18)
69
70 /* FLASH_SR bits */
71 #define FLASH_SR__BSY (1<<0)
72 #define FLASH_SR__EOP (1<<1)
73 #define FLASH_SR__ENDHV (1<<2)
74 #define FLASH_SR__READY (1<<3)
75 #define FLASH_SR__WRPERR (1<<8)
76 #define FLASH_SR__PGAERR (1<<9)
77 #define FLASH_SR__SIZERR (1<<10)
78 #define FLASH_SR__OPTVERR (1<<11)
79
80 /* Unlock keys */
81 #define PEKEY1 0x89ABCDEF
82 #define PEKEY2 0x02030405
83 #define PRGKEY1 0x8C9DAEBF
84 #define PRGKEY2 0x13141516
85 #define OPTKEY1 0xFBEAD9C8
86 #define OPTKEY2 0x24252627
87
88 /* other registers */
89 #define DBGMCU_IDCODE 0xE0042000
90 #define F_SIZE 0x1FF8004C
91
92 /* Constants */
93 #define FLASH_PAGE_SIZE 256
94 #define FLASH_SECTOR_SIZE 4096
95 #define FLASH_PAGES_PER_SECTOR 16
96 #define FLASH_BANK0_ADDRESS 0x08000000
97
98 /* stm32lx option byte register location */
99 #define OB_RDP 0x1FF80000
100 #define OB_USER 0x1FF80004
101 #define OB_WRP0_1 0x1FF80008
102 #define OB_WRP2_3 0x1FF8000C
103
104 /* OB_RDP values */
105 #define OB_RDP__LEVEL0 0xFF5500AA
106 #define OB_RDP__LEVEL1 0xFFFF0000
107
108 /* stm32lx RCC register locations */
109 #define RCC_CR 0x40023800
110 #define RCC_ICSCR 0x40023804
111 #define RCC_CFGR 0x40023808
112
113 /* RCC_ICSCR bits */
114 #define RCC_ICSCR__MSIRANGE_MASK (7<<13)
115
116 static int stm32lx_unlock_program_memory(struct flash_bank *bank);
117 static int stm32lx_lock_program_memory(struct flash_bank *bank);
118 static int stm32lx_enable_write_half_page(struct flash_bank *bank);
119 static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
120 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
121
122 struct stm32lx_flash_bank {
123 int probed;
124 };
125
126 /* flash bank stm32lx <base> <size> 0 0 <target#>
127 */
128 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
129 {
130 struct stm32lx_flash_bank *stm32lx_info;
131 if (CMD_ARGC < 6)
132 return ERROR_COMMAND_SYNTAX_ERROR;
133
134 /* Create the bank structure */
135 stm32lx_info = malloc(sizeof(struct stm32lx_flash_bank));
136
137 /* Check allocation */
138 if (stm32lx_info == NULL) {
139 LOG_ERROR("failed to allocate bank structure");
140 return ERROR_FAIL;
141 }
142
143 bank->driver_priv = stm32lx_info;
144
145 stm32lx_info->probed = 0;
146
147 return ERROR_OK;
148 }
149
150 static int stm32lx_protect_check(struct flash_bank *bank)
151 {
152 int retval;
153 struct target *target = bank->target;
154
155 uint32_t wrpr;
156
157 if (target->state != TARGET_HALTED) {
158 LOG_ERROR("Target not halted");
159 return ERROR_TARGET_NOT_HALTED;
160 }
161
162 /*
163 * Read the WRPR word, and check each bit (corresponding to each
164 * flash sector
165 */
166 retval = target_read_u32(target, FLASH_WRPR, &wrpr);
167 if (retval != ERROR_OK)
168 return retval;
169
170 for (int i = 0; i < 32; i++) {
171 if (wrpr & (1 << i))
172 bank->sectors[i].is_protected = 1;
173 else
174 bank->sectors[i].is_protected = 0;
175 }
176 return ERROR_OK;
177 }
178
179 static int stm32lx_erase(struct flash_bank *bank, int first, int last)
180 {
181 int retval;
182
183 /*
184 * It could be possible to do a mass erase if all sectors must be
185 * erased, but it is not implemented yet.
186 */
187
188 if (bank->target->state != TARGET_HALTED) {
189 LOG_ERROR("Target not halted");
190 return ERROR_TARGET_NOT_HALTED;
191 }
192
193 /*
194 * Loop over the selected sectors and erase them
195 */
196 for (int i = first; i <= last; i++) {
197 retval = stm32lx_erase_sector(bank, i);
198 if (retval != ERROR_OK)
199 return retval;
200 bank->sectors[i].is_erased = 1;
201 }
202 return ERROR_OK;
203 }
204
205 static int stm32lx_protect(struct flash_bank *bank, int set, int first,
206 int last)
207 {
208 LOG_WARNING("protection of the STM32L flash is not implemented");
209 return ERROR_OK;
210 }
211
212 static int stm32lx_write_half_pages(struct flash_bank *bank, uint8_t *buffer,
213 uint32_t offset, uint32_t count)
214 {
215 struct target *target = bank->target;
216 uint32_t buffer_size = 16384;
217 struct working_area *write_algorithm;
218 struct working_area *source;
219 uint32_t address = bank->base + offset;
220
221 struct reg_param reg_params[3];
222 struct armv7m_algorithm armv7m_info;
223
224 int retval = ERROR_OK;
225
226 /* see contib/loaders/flash/stm32lx.S for src */
227
228 static const uint8_t stm32lx_flash_write_code[] = {
229 /* write_word: */
230 0x00, 0x23, /* movs r3, #0 */
231 0x04, 0xe0, /* b test_done */
232
233 /* write_word: */
234 0x51, 0xf8, 0x04, 0xcb, /* ldr ip, [r1], #4 */
235 0x40, 0xf8, 0x04, 0xcb, /* str ip, [r0], #4 */
236 0x01, 0x33, /* adds r3, #1 */
237
238 /* test_done: */
239 0x93, 0x42, /* cmp r3, r2 */
240 0xf8, 0xd3, /* bcc write_word */
241 0x00, 0xbe, /* bkpt 0 */
242 };
243
244 /* Check if there is an even number of half pages (128bytes) */
245 if (count % 128) {
246 LOG_ERROR("there should be an even number "
247 "of half pages = 128 bytes (count = %" PRIi32 " bytes)", count);
248 return ERROR_FAIL;
249 }
250
251 /* flash write code */
252 if (target_alloc_working_area(target, sizeof(stm32lx_flash_write_code),
253 &write_algorithm) != ERROR_OK) {
254 LOG_DEBUG("no working area for block memory writes");
255 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
256 };
257
258 /* Write the flashing code */
259 retval = target_write_buffer(target,
260 write_algorithm->address,
261 sizeof(stm32lx_flash_write_code),
262 (uint8_t *)stm32lx_flash_write_code);
263 if (retval != ERROR_OK) {
264 target_free_working_area(target, write_algorithm);
265 return retval;
266 }
267
268 /* Allocate half pages memory */
269 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
270 if (buffer_size > 1024)
271 buffer_size -= 1024;
272 else
273 buffer_size /= 2;
274
275 if (buffer_size <= 256) {
276 /* we already allocated the writing code, but failed to get a
277 * buffer, free the algorithm */
278 target_free_working_area(target, write_algorithm);
279
280 LOG_WARNING("no large enough working area available, can't do block memory writes");
281 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
282 }
283 }
284
285 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
286 armv7m_info.core_mode = ARM_MODE_THREAD;
287 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
288 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
289 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
290
291 /* Enable half-page write */
292 retval = stm32lx_enable_write_half_page(bank);
293 if (retval != ERROR_OK) {
294 target_free_working_area(target, source);
295 target_free_working_area(target, write_algorithm);
296
297 destroy_reg_param(&reg_params[0]);
298 destroy_reg_param(&reg_params[1]);
299 destroy_reg_param(&reg_params[2]);
300 return retval;
301 }
302
303 struct armv7m_common *armv7m = target_to_armv7m(target);
304 if (armv7m == NULL) {
305
306 /* something is very wrong if armv7m is NULL */
307 LOG_ERROR("unable to get armv7m target");
308 return retval;
309 }
310
311 /* save any DEMCR flags and configure target to catch any Hard Faults */
312 uint32_t demcr_save = armv7m->demcr;
313 armv7m->demcr = VC_HARDERR;
314
315 /* Loop while there are bytes to write */
316 while (count > 0) {
317 uint32_t this_count;
318 this_count = (count > buffer_size) ? buffer_size : count;
319
320 /* Write the next half pages */
321 retval = target_write_buffer(target, source->address, this_count, buffer);
322 if (retval != ERROR_OK)
323 break;
324
325 /* 4: Store useful information in the registers */
326 /* the destination address of the copy (R0) */
327 buf_set_u32(reg_params[0].value, 0, 32, address);
328 /* The source address of the copy (R1) */
329 buf_set_u32(reg_params[1].value, 0, 32, source->address);
330 /* The length of the copy (R2) */
331 buf_set_u32(reg_params[2].value, 0, 32, this_count / 4);
332
333 /* 5: Execute the bunch of code */
334 retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params)
335 / sizeof(*reg_params), reg_params,
336 write_algorithm->address, 0, 10000, &armv7m_info);
337 if (retval != ERROR_OK)
338 break;
339
340 /* check for Hard Fault */
341 if (armv7m->exception_number == 3)
342 break;
343
344 /* 6: Wait while busy */
345 retval = stm32lx_wait_until_bsy_clear(bank);
346 if (retval != ERROR_OK)
347 break;
348
349 buffer += this_count;
350 address += this_count;
351 count -= this_count;
352 }
353
354 /* restore previous flags */
355 armv7m->demcr = demcr_save;
356
357 if (armv7m->exception_number == 3) {
358
359 /* the stm32l15x devices seem to have an issue when blank.
360 * if a ram loader is executed on a blank device it will
361 * Hard Fault, this issue does not happen for a already programmed device.
362 * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
363 * The workaround of handling the Hard Fault exception does work, but makes the
364 * loader more complicated, as a compromise we manually write the pages, programming time
365 * is reduced by 50% using this slower method.
366 */
367
368 LOG_WARNING("couldn't use loader, falling back to page memory writes");
369
370 while (count > 0) {
371 uint32_t this_count;
372 this_count = (count > 128) ? 128 : count;
373
374 /* Write the next half pages */
375 retval = target_write_buffer(target, address, this_count, buffer);
376 if (retval != ERROR_OK)
377 break;
378
379 /* Wait while busy */
380 retval = stm32lx_wait_until_bsy_clear(bank);
381 if (retval != ERROR_OK)
382 break;
383
384 buffer += this_count;
385 address += this_count;
386 count -= this_count;
387 }
388 }
389
390 if (retval == ERROR_OK)
391 retval = stm32lx_lock_program_memory(bank);
392
393 target_free_working_area(target, source);
394 target_free_working_area(target, write_algorithm);
395
396 destroy_reg_param(&reg_params[0]);
397 destroy_reg_param(&reg_params[1]);
398 destroy_reg_param(&reg_params[2]);
399
400 return retval;
401 }
402
403 static int stm32lx_write(struct flash_bank *bank, uint8_t *buffer,
404 uint32_t offset, uint32_t count)
405 {
406 struct target *target = bank->target;
407
408 uint32_t halfpages_number;
409 uint32_t bytes_remaining = 0;
410 uint32_t address = bank->base + offset;
411 uint32_t bytes_written = 0;
412 int retval, retval2;
413
414 if (bank->target->state != TARGET_HALTED) {
415 LOG_ERROR("Target not halted");
416 return ERROR_TARGET_NOT_HALTED;
417 }
418
419 if (offset & 0x3) {
420 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
421 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
422 }
423
424 retval = stm32lx_unlock_program_memory(bank);
425 if (retval != ERROR_OK)
426 return retval;
427
428 /* first we need to write any unaligned head bytes upto
429 * the next 128 byte page */
430
431 if (offset % 128)
432 bytes_remaining = MIN(count, 128 - (offset % 128));
433
434 while (bytes_remaining > 0) {
435 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
436
437 /* copy remaining bytes into the write buffer */
438 uint32_t bytes_to_write = MIN(4, bytes_remaining);
439 memcpy(value, buffer + bytes_written, bytes_to_write);
440
441 retval = target_write_buffer(target, address, 4, value);
442 if (retval != ERROR_OK)
443 goto reset_pg_and_lock;
444
445 bytes_written += bytes_to_write;
446 bytes_remaining -= bytes_to_write;
447 address += 4;
448
449 retval = stm32lx_wait_until_bsy_clear(bank);
450 if (retval != ERROR_OK)
451 goto reset_pg_and_lock;
452 }
453
454 offset += bytes_written;
455 count -= bytes_written;
456
457 /* this should always pass this check here */
458 assert((offset % 128) == 0);
459
460 /* calculate half pages */
461 halfpages_number = count / 128;
462
463 if (halfpages_number) {
464 retval = stm32lx_write_half_pages(bank, buffer + bytes_written, offset, 128 * halfpages_number);
465 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
466 /* attempt slow memory writes */
467 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
468 halfpages_number = 0;
469 } else {
470 if (retval != ERROR_OK)
471 return ERROR_FAIL;
472 }
473 }
474
475 /* write any remaining bytes */
476 uint32_t page_bytes_written = 128 * halfpages_number;
477 bytes_written += page_bytes_written;
478 address += page_bytes_written;
479 bytes_remaining = count - page_bytes_written;
480
481 retval = stm32lx_unlock_program_memory(bank);
482 if (retval != ERROR_OK)
483 return retval;
484
485 while (bytes_remaining > 0) {
486 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
487
488 /* copy remaining bytes into the write buffer */
489 uint32_t bytes_to_write = MIN(4, bytes_remaining);
490 memcpy(value, buffer + bytes_written, bytes_to_write);
491
492 retval = target_write_buffer(target, address, 4, value);
493 if (retval != ERROR_OK)
494 goto reset_pg_and_lock;
495
496 bytes_written += bytes_to_write;
497 bytes_remaining -= bytes_to_write;
498 address += 4;
499
500 retval = stm32lx_wait_until_bsy_clear(bank);
501 if (retval != ERROR_OK)
502 goto reset_pg_and_lock;
503 }
504
505 reset_pg_and_lock:
506 retval2 = stm32lx_lock_program_memory(bank);
507 if (retval == ERROR_OK)
508 retval = retval2;
509
510 return retval;
511 }
512
513 static int stm32lx_probe(struct flash_bank *bank)
514 {
515 struct target *target = bank->target;
516 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
517 int i;
518 uint16_t flash_size_in_kb;
519 uint16_t max_flash_size_in_kb;
520 uint32_t device_id;
521
522 stm32lx_info->probed = 0;
523
524 /* read stm32 device id register */
525 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
526 if (retval != ERROR_OK)
527 return retval;
528
529 LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
530
531 /* set max flash size depending on family */
532 switch (device_id & 0xfff) {
533 case 0x416:
534 max_flash_size_in_kb = 128;
535 break;
536 case 0x436:
537 max_flash_size_in_kb = 384;
538 break;
539 default:
540 LOG_WARNING("Cannot identify target as a STM32L family.");
541 return ERROR_FAIL;
542 }
543
544 /* get flash size from target. */
545 retval = target_read_u16(target, F_SIZE, &flash_size_in_kb);
546
547 /* failed reading flash size or flash size invalid (early silicon),
548 * default to max target family */
549 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
550 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
551 max_flash_size_in_kb);
552 flash_size_in_kb = max_flash_size_in_kb;
553 }
554
555 /* if the user sets the size manually then ignore the probed value
556 * this allows us to work around devices that have a invalid flash size register value */
557 if (bank->size) {
558 LOG_INFO("ignoring flash probed value, using configured bank size");
559 flash_size_in_kb = bank->size / 1024;
560 }
561
562 /* STM32L - we have 32 sectors, 16 pages per sector -> 512 pages
563 * 16 pages for a protection area */
564
565 /* calculate numbers of sectors (4kB per sector) */
566 int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
567 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
568
569 if (bank->sectors) {
570 free(bank->sectors);
571 bank->sectors = NULL;
572 }
573
574 bank->base = FLASH_BANK0_ADDRESS;
575 bank->size = flash_size_in_kb * 1024;
576 bank->num_sectors = num_sectors;
577 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
578 if (bank->sectors == NULL) {
579 LOG_ERROR("failed to allocate bank sectors");
580 return ERROR_FAIL;
581 }
582
583 for (i = 0; i < num_sectors; i++) {
584 bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
585 bank->sectors[i].size = FLASH_SECTOR_SIZE;
586 bank->sectors[i].is_erased = -1;
587 bank->sectors[i].is_protected = 1;
588 }
589
590 stm32lx_info->probed = 1;
591
592 return ERROR_OK;
593 }
594
595 static int stm32lx_auto_probe(struct flash_bank *bank)
596 {
597 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
598
599 if (stm32lx_info->probed)
600 return ERROR_OK;
601
602 return stm32lx_probe(bank);
603 }
604
605 static int stm32lx_erase_check(struct flash_bank *bank)
606 {
607 struct target *target = bank->target;
608 const int buffer_size = 4096;
609 int i;
610 uint32_t nBytes;
611 int retval = ERROR_OK;
612
613 if (bank->target->state != TARGET_HALTED) {
614 LOG_ERROR("Target not halted");
615 return ERROR_TARGET_NOT_HALTED;
616 }
617
618 uint8_t *buffer = malloc(buffer_size);
619 if (buffer == NULL) {
620 LOG_ERROR("failed to allocate read buffer");
621 return ERROR_FAIL;
622 }
623
624 for (i = 0; i < bank->num_sectors; i++) {
625 uint32_t j;
626 bank->sectors[i].is_erased = 1;
627
628 /* Loop chunk by chunk over the sector */
629 for (j = 0; j < bank->sectors[i].size; j += buffer_size) {
630 uint32_t chunk;
631 chunk = buffer_size;
632 if (chunk > (j - bank->sectors[i].size))
633 chunk = (j - bank->sectors[i].size);
634
635 retval = target_read_memory(target, bank->base
636 + bank->sectors[i].offset + j, 4, chunk / 4, buffer);
637 if (retval != ERROR_OK)
638 break;
639
640 for (nBytes = 0; nBytes < chunk; nBytes++) {
641 if (buffer[nBytes] != 0x00) {
642 bank->sectors[i].is_erased = 0;
643 break;
644 }
645 }
646 }
647 if (retval != ERROR_OK)
648 break;
649 }
650 free(buffer);
651
652 return retval;
653 }
654
655 static int stm32lx_get_info(struct flash_bank *bank, char *buf, int buf_size)
656 {
657 /* This method must return a string displaying information about the bank */
658
659 struct target *target = bank->target;
660 uint32_t device_id;
661 int printed;
662
663 /* read stm32 device id register */
664 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
665 if (retval != ERROR_OK)
666 return retval;
667
668 if ((device_id & 0xfff) == 0x416) {
669 printed = snprintf(buf, buf_size, "stm32lx - Rev: ");
670 buf += printed;
671 buf_size -= printed;
672
673 switch (device_id >> 16) {
674 case 0x1000:
675 snprintf(buf, buf_size, "A");
676 break;
677
678 case 0x1008:
679 snprintf(buf, buf_size, "Y");
680 break;
681
682 case 0x1018:
683 snprintf(buf, buf_size, "X");
684 break;
685
686 case 0x1038:
687 snprintf(buf, buf_size, "W");
688 break;
689
690 case 0x1078:
691 snprintf(buf, buf_size, "V");
692 break;
693
694 default:
695 snprintf(buf, buf_size, "unknown");
696 break;
697 }
698 } else if ((device_id & 0xfff) == 0x436) {
699 printed = snprintf(buf, buf_size, "stm32lx (HD) - Rev: ");
700 buf += printed;
701 buf_size -= printed;
702
703 switch (device_id >> 16) {
704 case 0x1000:
705 snprintf(buf, buf_size, "A");
706 break;
707
708 case 0x1008:
709 snprintf(buf, buf_size, "Z");
710 break;
711
712 case 0x1018:
713 snprintf(buf, buf_size, "Y");
714 break;
715
716 default:
717 snprintf(buf, buf_size, "unknown");
718 break;
719 }
720 } else {
721 snprintf(buf, buf_size, "Cannot identify target as a stm32lx");
722 return ERROR_FAIL;
723 }
724
725 return ERROR_OK;
726 }
727
728 static const struct command_registration stm32lx_exec_command_handlers[] = {
729 COMMAND_REGISTRATION_DONE
730 };
731
732 static const struct command_registration stm32lx_command_handlers[] = {
733 {
734 .name = "stm32lx",
735 .mode = COMMAND_ANY,
736 .help = "stm32lx flash command group",
737 .usage = "",
738 .chain = stm32lx_exec_command_handlers,
739 },
740 COMMAND_REGISTRATION_DONE
741 };
742
743 struct flash_driver stm32lx_flash = {
744 .name = "stm32lx",
745 .commands = stm32lx_command_handlers,
746 .flash_bank_command = stm32lx_flash_bank_command,
747 .erase = stm32lx_erase,
748 .protect = stm32lx_protect,
749 .write = stm32lx_write,
750 .read = default_flash_read,
751 .probe = stm32lx_probe,
752 .auto_probe = stm32lx_auto_probe,
753 .erase_check = stm32lx_erase_check,
754 .protect_check = stm32lx_protect_check,
755 .info = stm32lx_get_info,
756 };
757
758 /* Static methods implementation */
759 static int stm32lx_unlock_program_memory(struct flash_bank *bank)
760 {
761 struct target *target = bank->target;
762 int retval;
763 uint32_t reg32;
764
765 /*
766 * Unlocking the program memory is done by unlocking the PECR,
767 * then by writing the 2 PRGKEY to the PRGKEYR register
768 */
769
770 /* check flash is not already unlocked */
771 retval = target_read_u32(target, FLASH_PECR, &reg32);
772 if (retval != ERROR_OK)
773 return retval;
774
775 if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
776 return ERROR_OK;
777
778 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
779 retval = target_write_u32(target, FLASH_PEKEYR, PEKEY1);
780 if (retval != ERROR_OK)
781 return retval;
782
783 retval = target_write_u32(target, FLASH_PEKEYR, PEKEY2);
784 if (retval != ERROR_OK)
785 return retval;
786
787 /* Make sure it worked */
788 retval = target_read_u32(target, FLASH_PECR, &reg32);
789 if (retval != ERROR_OK)
790 return retval;
791
792 if (reg32 & FLASH_PECR__PELOCK) {
793 LOG_ERROR("PELOCK is not cleared :(");
794 return ERROR_FLASH_OPERATION_FAILED;
795 }
796
797 retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY1);
798 if (retval != ERROR_OK)
799 return retval;
800 retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY2);
801 if (retval != ERROR_OK)
802 return retval;
803
804 /* Make sure it worked */
805 retval = target_read_u32(target, FLASH_PECR, &reg32);
806 if (retval != ERROR_OK)
807 return retval;
808
809 if (reg32 & FLASH_PECR__PRGLOCK) {
810 LOG_ERROR("PRGLOCK is not cleared :(");
811 return ERROR_FLASH_OPERATION_FAILED;
812 }
813
814 return ERROR_OK;
815 }
816
817 static int stm32lx_enable_write_half_page(struct flash_bank *bank)
818 {
819 struct target *target = bank->target;
820 int retval;
821 uint32_t reg32;
822
823 /**
824 * Unlock the program memory, then set the FPRG bit in the PECR register.
825 */
826 retval = stm32lx_unlock_program_memory(bank);
827 if (retval != ERROR_OK)
828 return retval;
829
830 retval = target_read_u32(target, FLASH_PECR, &reg32);
831 if (retval != ERROR_OK)
832 return retval;
833
834 reg32 |= FLASH_PECR__FPRG;
835 retval = target_write_u32(target, FLASH_PECR, reg32);
836 if (retval != ERROR_OK)
837 return retval;
838
839 retval = target_read_u32(target, FLASH_PECR, &reg32);
840 if (retval != ERROR_OK)
841 return retval;
842
843 reg32 |= FLASH_PECR__PROG;
844 retval = target_write_u32(target, FLASH_PECR, reg32);
845
846 return retval;
847 }
848
849 static int stm32lx_lock_program_memory(struct flash_bank *bank)
850 {
851 struct target *target = bank->target;
852 int retval;
853 uint32_t reg32;
854
855 /* To lock the program memory, simply set the lock bit and lock PECR */
856
857 retval = target_read_u32(target, FLASH_PECR, &reg32);
858 if (retval != ERROR_OK)
859 return retval;
860
861 reg32 |= FLASH_PECR__PRGLOCK;
862 retval = target_write_u32(target, FLASH_PECR, reg32);
863 if (retval != ERROR_OK)
864 return retval;
865
866 retval = target_read_u32(target, FLASH_PECR, &reg32);
867 if (retval != ERROR_OK)
868 return retval;
869
870 reg32 |= FLASH_PECR__PELOCK;
871 retval = target_write_u32(target, FLASH_PECR, reg32);
872 if (retval != ERROR_OK)
873 return retval;
874
875 return ERROR_OK;
876 }
877
878 static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
879 {
880 struct target *target = bank->target;
881 int retval;
882 uint32_t reg32;
883
884 /*
885 * To erase a sector (i.e. FLASH_PAGES_PER_SECTOR pages),
886 * first unlock the memory, loop over the pages of this sector
887 * and write 0x0 to its first word.
888 */
889
890 retval = stm32lx_unlock_program_memory(bank);
891 if (retval != ERROR_OK)
892 return retval;
893
894 for (int page = 0; page < FLASH_PAGES_PER_SECTOR; page++) {
895 reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
896 retval = target_write_u32(target, FLASH_PECR, reg32);
897 if (retval != ERROR_OK)
898 return retval;
899
900 retval = stm32lx_wait_until_bsy_clear(bank);
901 if (retval != ERROR_OK)
902 return retval;
903
904 uint32_t addr = bank->base + bank->sectors[sector].offset + (page
905 * FLASH_PAGE_SIZE);
906 retval = target_write_u32(target, addr, 0x0);
907 if (retval != ERROR_OK)
908 return retval;
909
910 retval = stm32lx_wait_until_bsy_clear(bank);
911 if (retval != ERROR_OK)
912 return retval;
913 }
914
915 retval = stm32lx_lock_program_memory(bank);
916 if (retval != ERROR_OK)
917 return retval;
918
919 return ERROR_OK;
920 }
921
922 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
923 {
924 struct target *target = bank->target;
925 uint32_t status;
926 int retval = ERROR_OK;
927 int timeout = 100;
928
929 /* wait for busy to clear */
930 for (;;) {
931 retval = target_read_u32(target, FLASH_SR, &status);
932 if (retval != ERROR_OK)
933 return retval;
934
935 if ((status & FLASH_SR__BSY) == 0)
936 break;
937 if (timeout-- <= 0) {
938 LOG_ERROR("timed out waiting for flash");
939 return ERROR_FAIL;
940 }
941 alive_sleep(1);
942 }
943
944 if (status & FLASH_SR__WRPERR) {
945 LOG_ERROR("access denied / write protected");
946 retval = ERROR_FAIL;
947 }
948
949 if (status & FLASH_SR__PGAERR) {
950 LOG_ERROR("invalid program address");
951 retval = ERROR_FAIL;
952 }
953
954 return retval;
955 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)