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helper/command: change prototype of command_print/command_print_sameline
[openocd.git] / src / flash / nor / stm32lx.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33 #include <target/cortex_m.h>
34
35 /* stm32lx flash register locations */
36
37 #define FLASH_ACR 0x00
38 #define FLASH_PECR 0x04
39 #define FLASH_PDKEYR 0x08
40 #define FLASH_PEKEYR 0x0C
41 #define FLASH_PRGKEYR 0x10
42 #define FLASH_OPTKEYR 0x14
43 #define FLASH_SR 0x18
44 #define FLASH_OBR 0x1C
45 #define FLASH_WRPR 0x20
46
47 /* FLASH_ACR bites */
48 #define FLASH_ACR__LATENCY (1<<0)
49 #define FLASH_ACR__PRFTEN (1<<1)
50 #define FLASH_ACR__ACC64 (1<<2)
51 #define FLASH_ACR__SLEEP_PD (1<<3)
52 #define FLASH_ACR__RUN_PD (1<<4)
53
54 /* FLASH_PECR bits */
55 #define FLASH_PECR__PELOCK (1<<0)
56 #define FLASH_PECR__PRGLOCK (1<<1)
57 #define FLASH_PECR__OPTLOCK (1<<2)
58 #define FLASH_PECR__PROG (1<<3)
59 #define FLASH_PECR__DATA (1<<4)
60 #define FLASH_PECR__FTDW (1<<8)
61 #define FLASH_PECR__ERASE (1<<9)
62 #define FLASH_PECR__FPRG (1<<10)
63 #define FLASH_PECR__EOPIE (1<<16)
64 #define FLASH_PECR__ERRIE (1<<17)
65 #define FLASH_PECR__OBL_LAUNCH (1<<18)
66
67 /* FLASH_SR bits */
68 #define FLASH_SR__BSY (1<<0)
69 #define FLASH_SR__EOP (1<<1)
70 #define FLASH_SR__ENDHV (1<<2)
71 #define FLASH_SR__READY (1<<3)
72 #define FLASH_SR__WRPERR (1<<8)
73 #define FLASH_SR__PGAERR (1<<9)
74 #define FLASH_SR__SIZERR (1<<10)
75 #define FLASH_SR__OPTVERR (1<<11)
76
77 /* Unlock keys */
78 #define PEKEY1 0x89ABCDEF
79 #define PEKEY2 0x02030405
80 #define PRGKEY1 0x8C9DAEBF
81 #define PRGKEY2 0x13141516
82 #define OPTKEY1 0xFBEAD9C8
83 #define OPTKEY2 0x24252627
84
85 /* other registers */
86 #define DBGMCU_IDCODE 0xE0042000
87 #define DBGMCU_IDCODE_L0 0x40015800
88
89 /* Constants */
90 #define FLASH_SECTOR_SIZE 4096
91 #define FLASH_BANK0_ADDRESS 0x08000000
92
93 /* option bytes */
94 #define OPTION_BYTES_ADDRESS 0x1FF80000
95
96 #define OPTION_BYTE_0_PR1 0xFFFF0000
97 #define OPTION_BYTE_0_PR0 0xFF5500AA
98
99 static int stm32lx_unlock_program_memory(struct flash_bank *bank);
100 static int stm32lx_lock_program_memory(struct flash_bank *bank);
101 static int stm32lx_enable_write_half_page(struct flash_bank *bank);
102 static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
103 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
104 static int stm32lx_lock(struct flash_bank *bank);
105 static int stm32lx_unlock(struct flash_bank *bank);
106 static int stm32lx_mass_erase(struct flash_bank *bank);
107 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout);
108 static int stm32lx_update_part_info(struct flash_bank *bank, uint16_t flash_size_in_kb);
109
110 struct stm32lx_rev {
111 uint16_t rev;
112 const char *str;
113 };
114
115 struct stm32lx_part_info {
116 uint16_t id;
117 const char *device_str;
118 const struct stm32lx_rev *revs;
119 size_t num_revs;
120 unsigned int page_size;
121 unsigned int pages_per_sector;
122 uint16_t max_flash_size_kb;
123 uint16_t first_bank_size_kb; /* used when has_dual_banks is true */
124 bool has_dual_banks;
125
126 uint32_t flash_base; /* Flash controller registers location */
127 uint32_t fsize_base; /* Location of FSIZE register */
128 };
129
130 struct stm32lx_flash_bank {
131 int probed;
132 uint32_t idcode;
133 uint32_t user_bank_size;
134 uint32_t flash_base;
135
136 struct stm32lx_part_info part_info;
137 };
138
139 static const struct stm32lx_rev stm32_416_revs[] = {
140 { 0x1000, "A" }, { 0x1008, "Y" }, { 0x1038, "W" }, { 0x1078, "V" },
141 };
142 static const struct stm32lx_rev stm32_417_revs[] = {
143 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, { 0x1038, "X" }
144 };
145 static const struct stm32lx_rev stm32_425_revs[] = {
146 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" },
147 };
148 static const struct stm32lx_rev stm32_427_revs[] = {
149 { 0x1000, "A" }, { 0x1018, "Y" }, { 0x1038, "X" }, { 0x10f8, "V" },
150 };
151 static const struct stm32lx_rev stm32_429_revs[] = {
152 { 0x1000, "A" }, { 0x1018, "Z" },
153 };
154 static const struct stm32lx_rev stm32_436_revs[] = {
155 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" },
156 };
157 static const struct stm32lx_rev stm32_437_revs[] = {
158 { 0x1000, "A" },
159 };
160 static const struct stm32lx_rev stm32_447_revs[] = {
161 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Z" },
162 };
163 static const struct stm32lx_rev stm32_457_revs[] = {
164 { 0x1000, "A" }, { 0x1008, "Z" },
165 };
166
167 static const struct stm32lx_part_info stm32lx_parts[] = {
168 {
169 .id = 0x416,
170 .revs = stm32_416_revs,
171 .num_revs = ARRAY_SIZE(stm32_416_revs),
172 .device_str = "STM32L1xx (Cat.1 - Low/Medium Density)",
173 .page_size = 256,
174 .pages_per_sector = 16,
175 .max_flash_size_kb = 128,
176 .has_dual_banks = false,
177 .flash_base = 0x40023C00,
178 .fsize_base = 0x1FF8004C,
179 },
180 {
181 .id = 0x417,
182 .revs = stm32_417_revs,
183 .num_revs = ARRAY_SIZE(stm32_417_revs),
184 .device_str = "STM32L0xx (Cat. 3)",
185 .page_size = 128,
186 .pages_per_sector = 32,
187 .max_flash_size_kb = 64,
188 .has_dual_banks = false,
189 .flash_base = 0x40022000,
190 .fsize_base = 0x1FF8007C,
191 },
192 {
193 .id = 0x425,
194 .revs = stm32_425_revs,
195 .num_revs = ARRAY_SIZE(stm32_425_revs),
196 .device_str = "STM32L0xx (Cat. 2)",
197 .page_size = 128,
198 .pages_per_sector = 32,
199 .max_flash_size_kb = 32,
200 .has_dual_banks = false,
201 .flash_base = 0x40022000,
202 .fsize_base = 0x1FF8007C,
203 },
204 {
205 .id = 0x427,
206 .revs = stm32_427_revs,
207 .num_revs = ARRAY_SIZE(stm32_427_revs),
208 .device_str = "STM32L1xx (Cat.3 - Medium+ Density)",
209 .page_size = 256,
210 .pages_per_sector = 16,
211 .max_flash_size_kb = 256,
212 .has_dual_banks = false,
213 .flash_base = 0x40023C00,
214 .fsize_base = 0x1FF800CC,
215 },
216 {
217 .id = 0x429,
218 .revs = stm32_429_revs,
219 .num_revs = ARRAY_SIZE(stm32_429_revs),
220 .device_str = "STM32L1xx (Cat.2)",
221 .page_size = 256,
222 .pages_per_sector = 16,
223 .max_flash_size_kb = 128,
224 .has_dual_banks = false,
225 .flash_base = 0x40023C00,
226 .fsize_base = 0x1FF8004C,
227 },
228 {
229 .id = 0x436,
230 .revs = stm32_436_revs,
231 .num_revs = ARRAY_SIZE(stm32_436_revs),
232 .device_str = "STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)",
233 .page_size = 256,
234 .pages_per_sector = 16,
235 .max_flash_size_kb = 384,
236 .first_bank_size_kb = 192,
237 .has_dual_banks = true,
238 .flash_base = 0x40023C00,
239 .fsize_base = 0x1FF800CC,
240 },
241 {
242 .id = 0x437,
243 .revs = stm32_437_revs,
244 .num_revs = ARRAY_SIZE(stm32_437_revs),
245 .device_str = "STM32L1xx (Cat.5/Cat.6)",
246 .page_size = 256,
247 .pages_per_sector = 16,
248 .max_flash_size_kb = 512,
249 .first_bank_size_kb = 0, /* determined in runtime */
250 .has_dual_banks = true,
251 .flash_base = 0x40023C00,
252 .fsize_base = 0x1FF800CC,
253 },
254 {
255 .id = 0x447,
256 .revs = stm32_447_revs,
257 .num_revs = ARRAY_SIZE(stm32_447_revs),
258 .device_str = "STM32L0xx (Cat.5)",
259 .page_size = 128,
260 .pages_per_sector = 32,
261 .max_flash_size_kb = 192,
262 .first_bank_size_kb = 0, /* determined in runtime */
263 .has_dual_banks = false, /* determined in runtime */
264 .flash_base = 0x40022000,
265 .fsize_base = 0x1FF8007C,
266 },
267 {
268 .id = 0x457,
269 .revs = stm32_457_revs,
270 .num_revs = ARRAY_SIZE(stm32_457_revs),
271 .device_str = "STM32L0xx (Cat.1)",
272 .page_size = 128,
273 .pages_per_sector = 32,
274 .max_flash_size_kb = 16,
275 .has_dual_banks = false,
276 .flash_base = 0x40022000,
277 .fsize_base = 0x1FF8007C,
278 },
279 };
280
281 /* flash bank stm32lx <base> <size> 0 0 <target#>
282 */
283 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
284 {
285 struct stm32lx_flash_bank *stm32lx_info;
286 if (CMD_ARGC < 6)
287 return ERROR_COMMAND_SYNTAX_ERROR;
288
289 /* Create the bank structure */
290 stm32lx_info = calloc(1, sizeof(*stm32lx_info));
291
292 /* Check allocation */
293 if (stm32lx_info == NULL) {
294 LOG_ERROR("failed to allocate bank structure");
295 return ERROR_FAIL;
296 }
297
298 bank->driver_priv = stm32lx_info;
299
300 stm32lx_info->probed = 0;
301 stm32lx_info->user_bank_size = bank->size;
302
303 /* the stm32l erased value is 0x00 */
304 bank->default_padded_value = bank->erased_value = 0x00;
305
306 return ERROR_OK;
307 }
308
309 COMMAND_HANDLER(stm32lx_handle_mass_erase_command)
310 {
311 int i;
312
313 if (CMD_ARGC < 1)
314 return ERROR_COMMAND_SYNTAX_ERROR;
315
316 struct flash_bank *bank;
317 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
318 if (ERROR_OK != retval)
319 return retval;
320
321 retval = stm32lx_mass_erase(bank);
322 if (retval == ERROR_OK) {
323 /* set all sectors as erased */
324 for (i = 0; i < bank->num_sectors; i++)
325 bank->sectors[i].is_erased = 1;
326
327 command_print(CMD, "stm32lx mass erase complete");
328 } else {
329 command_print(CMD, "stm32lx mass erase failed");
330 }
331
332 return retval;
333 }
334
335 COMMAND_HANDLER(stm32lx_handle_lock_command)
336 {
337 if (CMD_ARGC < 1)
338 return ERROR_COMMAND_SYNTAX_ERROR;
339
340 struct flash_bank *bank;
341 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
342 if (ERROR_OK != retval)
343 return retval;
344
345 retval = stm32lx_lock(bank);
346
347 if (retval == ERROR_OK)
348 command_print(CMD, "STM32Lx locked, takes effect after power cycle.");
349 else
350 command_print(CMD, "STM32Lx lock failed");
351
352 return retval;
353 }
354
355 COMMAND_HANDLER(stm32lx_handle_unlock_command)
356 {
357 if (CMD_ARGC < 1)
358 return ERROR_COMMAND_SYNTAX_ERROR;
359
360 struct flash_bank *bank;
361 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
362 if (ERROR_OK != retval)
363 return retval;
364
365 retval = stm32lx_unlock(bank);
366
367 if (retval == ERROR_OK)
368 command_print(CMD, "STM32Lx unlocked, takes effect after power cycle.");
369 else
370 command_print(CMD, "STM32Lx unlock failed");
371
372 return retval;
373 }
374
375 static int stm32lx_protect_check(struct flash_bank *bank)
376 {
377 int retval;
378 struct target *target = bank->target;
379 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
380
381 uint32_t wrpr;
382
383 /*
384 * Read the WRPR word, and check each bit (corresponding to each
385 * flash sector
386 */
387 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_WRPR,
388 &wrpr);
389 if (retval != ERROR_OK)
390 return retval;
391
392 for (int i = 0; i < bank->num_sectors; i++) {
393 if (wrpr & (1 << i))
394 bank->sectors[i].is_protected = 1;
395 else
396 bank->sectors[i].is_protected = 0;
397 }
398 return ERROR_OK;
399 }
400
401 static int stm32lx_erase(struct flash_bank *bank, int first, int last)
402 {
403 int retval;
404
405 /*
406 * It could be possible to do a mass erase if all sectors must be
407 * erased, but it is not implemented yet.
408 */
409
410 if (bank->target->state != TARGET_HALTED) {
411 LOG_ERROR("Target not halted");
412 return ERROR_TARGET_NOT_HALTED;
413 }
414
415 /*
416 * Loop over the selected sectors and erase them
417 */
418 for (int i = first; i <= last; i++) {
419 retval = stm32lx_erase_sector(bank, i);
420 if (retval != ERROR_OK)
421 return retval;
422 bank->sectors[i].is_erased = 1;
423 }
424 return ERROR_OK;
425 }
426
427 static int stm32lx_write_half_pages(struct flash_bank *bank, const uint8_t *buffer,
428 uint32_t offset, uint32_t count)
429 {
430 struct target *target = bank->target;
431 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
432
433 uint32_t hp_nb = stm32lx_info->part_info.page_size / 2;
434 uint32_t buffer_size = 16384;
435 struct working_area *write_algorithm;
436 struct working_area *source;
437 uint32_t address = bank->base + offset;
438
439 struct reg_param reg_params[3];
440 struct armv7m_algorithm armv7m_info;
441
442 int retval = ERROR_OK;
443
444 static const uint8_t stm32lx_flash_write_code[] = {
445 #include "../../../contrib/loaders/flash/stm32/stm32lx.inc"
446 };
447
448 /* Make sure we're performing a half-page aligned write. */
449 if (count % hp_nb) {
450 LOG_ERROR("The byte count must be %" PRIu32 "B-aligned but count is %" PRIi32 "B)", hp_nb, count);
451 return ERROR_FAIL;
452 }
453
454 /* flash write code */
455 if (target_alloc_working_area(target, sizeof(stm32lx_flash_write_code),
456 &write_algorithm) != ERROR_OK) {
457 LOG_DEBUG("no working area for block memory writes");
458 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
459 }
460
461 /* Write the flashing code */
462 retval = target_write_buffer(target,
463 write_algorithm->address,
464 sizeof(stm32lx_flash_write_code),
465 stm32lx_flash_write_code);
466 if (retval != ERROR_OK) {
467 target_free_working_area(target, write_algorithm);
468 return retval;
469 }
470
471 /* Allocate half pages memory */
472 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
473 if (buffer_size > 1024)
474 buffer_size -= 1024;
475 else
476 buffer_size /= 2;
477
478 if (buffer_size <= stm32lx_info->part_info.page_size) {
479 /* we already allocated the writing code, but failed to get a
480 * buffer, free the algorithm */
481 target_free_working_area(target, write_algorithm);
482
483 LOG_WARNING("no large enough working area available, can't do block memory writes");
484 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
485 }
486 }
487
488 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
489 armv7m_info.core_mode = ARM_MODE_THREAD;
490 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
491 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
492 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
493
494 /* Enable half-page write */
495 retval = stm32lx_enable_write_half_page(bank);
496 if (retval != ERROR_OK) {
497 target_free_working_area(target, source);
498 target_free_working_area(target, write_algorithm);
499
500 destroy_reg_param(&reg_params[0]);
501 destroy_reg_param(&reg_params[1]);
502 destroy_reg_param(&reg_params[2]);
503 return retval;
504 }
505
506 struct armv7m_common *armv7m = target_to_armv7m(target);
507 if (armv7m == NULL) {
508
509 /* something is very wrong if armv7m is NULL */
510 LOG_ERROR("unable to get armv7m target");
511 return retval;
512 }
513
514 /* save any DEMCR flags and configure target to catch any Hard Faults */
515 uint32_t demcr_save = armv7m->demcr;
516 armv7m->demcr = VC_HARDERR;
517
518 /* Loop while there are bytes to write */
519 while (count > 0) {
520 uint32_t this_count;
521 this_count = (count > buffer_size) ? buffer_size : count;
522
523 /* Write the next half pages */
524 retval = target_write_buffer(target, source->address, this_count, buffer);
525 if (retval != ERROR_OK)
526 break;
527
528 /* 4: Store useful information in the registers */
529 /* the destination address of the copy (R0) */
530 buf_set_u32(reg_params[0].value, 0, 32, address);
531 /* The source address of the copy (R1) */
532 buf_set_u32(reg_params[1].value, 0, 32, source->address);
533 /* The length of the copy (R2) */
534 buf_set_u32(reg_params[2].value, 0, 32, this_count / 4);
535
536 /* 5: Execute the bunch of code */
537 retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params)
538 / sizeof(*reg_params), reg_params,
539 write_algorithm->address, 0, 10000, &armv7m_info);
540 if (retval != ERROR_OK)
541 break;
542
543 /* check for Hard Fault */
544 if (armv7m->exception_number == 3)
545 break;
546
547 /* 6: Wait while busy */
548 retval = stm32lx_wait_until_bsy_clear(bank);
549 if (retval != ERROR_OK)
550 break;
551
552 buffer += this_count;
553 address += this_count;
554 count -= this_count;
555 }
556
557 /* restore previous flags */
558 armv7m->demcr = demcr_save;
559
560 if (armv7m->exception_number == 3) {
561
562 /* the stm32l15x devices seem to have an issue when blank.
563 * if a ram loader is executed on a blank device it will
564 * Hard Fault, this issue does not happen for a already programmed device.
565 * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
566 * The workaround of handling the Hard Fault exception does work, but makes the
567 * loader more complicated, as a compromise we manually write the pages, programming time
568 * is reduced by 50% using this slower method.
569 */
570
571 LOG_WARNING("Couldn't use loader, falling back to page memory writes");
572
573 while (count > 0) {
574 uint32_t this_count;
575 this_count = (count > hp_nb) ? hp_nb : count;
576
577 /* Write the next half pages */
578 retval = target_write_buffer(target, address, this_count, buffer);
579 if (retval != ERROR_OK)
580 break;
581
582 /* Wait while busy */
583 retval = stm32lx_wait_until_bsy_clear(bank);
584 if (retval != ERROR_OK)
585 break;
586
587 buffer += this_count;
588 address += this_count;
589 count -= this_count;
590 }
591 }
592
593 if (retval == ERROR_OK)
594 retval = stm32lx_lock_program_memory(bank);
595
596 target_free_working_area(target, source);
597 target_free_working_area(target, write_algorithm);
598
599 destroy_reg_param(&reg_params[0]);
600 destroy_reg_param(&reg_params[1]);
601 destroy_reg_param(&reg_params[2]);
602
603 return retval;
604 }
605
606 static int stm32lx_write(struct flash_bank *bank, const uint8_t *buffer,
607 uint32_t offset, uint32_t count)
608 {
609 struct target *target = bank->target;
610 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
611
612 uint32_t hp_nb = stm32lx_info->part_info.page_size / 2;
613 uint32_t halfpages_number;
614 uint32_t bytes_remaining = 0;
615 uint32_t address = bank->base + offset;
616 uint32_t bytes_written = 0;
617 int retval, retval2;
618
619 if (bank->target->state != TARGET_HALTED) {
620 LOG_ERROR("Target not halted");
621 return ERROR_TARGET_NOT_HALTED;
622 }
623
624 if (offset & 0x3) {
625 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
626 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
627 }
628
629 retval = stm32lx_unlock_program_memory(bank);
630 if (retval != ERROR_OK)
631 return retval;
632
633 /* first we need to write any unaligned head bytes upto
634 * the next 128 byte page */
635
636 if (offset % hp_nb)
637 bytes_remaining = MIN(count, hp_nb - (offset % hp_nb));
638
639 while (bytes_remaining > 0) {
640 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
641
642 /* copy remaining bytes into the write buffer */
643 uint32_t bytes_to_write = MIN(4, bytes_remaining);
644 memcpy(value, buffer + bytes_written, bytes_to_write);
645
646 retval = target_write_buffer(target, address, 4, value);
647 if (retval != ERROR_OK)
648 goto reset_pg_and_lock;
649
650 bytes_written += bytes_to_write;
651 bytes_remaining -= bytes_to_write;
652 address += 4;
653
654 retval = stm32lx_wait_until_bsy_clear(bank);
655 if (retval != ERROR_OK)
656 goto reset_pg_and_lock;
657 }
658
659 offset += bytes_written;
660 count -= bytes_written;
661
662 /* this should always pass this check here */
663 assert((offset % hp_nb) == 0);
664
665 /* calculate half pages */
666 halfpages_number = count / hp_nb;
667
668 if (halfpages_number) {
669 retval = stm32lx_write_half_pages(bank, buffer + bytes_written, offset, hp_nb * halfpages_number);
670 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
671 /* attempt slow memory writes */
672 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
673 halfpages_number = 0;
674 } else {
675 if (retval != ERROR_OK)
676 return ERROR_FAIL;
677 }
678 }
679
680 /* write any remaining bytes */
681 uint32_t page_bytes_written = hp_nb * halfpages_number;
682 bytes_written += page_bytes_written;
683 address += page_bytes_written;
684 bytes_remaining = count - page_bytes_written;
685
686 retval = stm32lx_unlock_program_memory(bank);
687 if (retval != ERROR_OK)
688 return retval;
689
690 while (bytes_remaining > 0) {
691 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
692
693 /* copy remaining bytes into the write buffer */
694 uint32_t bytes_to_write = MIN(4, bytes_remaining);
695 memcpy(value, buffer + bytes_written, bytes_to_write);
696
697 retval = target_write_buffer(target, address, 4, value);
698 if (retval != ERROR_OK)
699 goto reset_pg_and_lock;
700
701 bytes_written += bytes_to_write;
702 bytes_remaining -= bytes_to_write;
703 address += 4;
704
705 retval = stm32lx_wait_until_bsy_clear(bank);
706 if (retval != ERROR_OK)
707 goto reset_pg_and_lock;
708 }
709
710 reset_pg_and_lock:
711 retval2 = stm32lx_lock_program_memory(bank);
712 if (retval == ERROR_OK)
713 retval = retval2;
714
715 return retval;
716 }
717
718 static int stm32lx_read_id_code(struct target *target, uint32_t *id)
719 {
720 struct armv7m_common *armv7m = target_to_armv7m(target);
721 int retval;
722 if (armv7m->arm.is_armv6m == true)
723 retval = target_read_u32(target, DBGMCU_IDCODE_L0, id);
724 else
725 /* read stm32 device id register */
726 retval = target_read_u32(target, DBGMCU_IDCODE, id);
727 return retval;
728 }
729
730 static int stm32lx_probe(struct flash_bank *bank)
731 {
732 struct target *target = bank->target;
733 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
734 int i;
735 uint16_t flash_size_in_kb;
736 uint32_t device_id;
737 uint32_t base_address = FLASH_BANK0_ADDRESS;
738 uint32_t second_bank_base;
739 unsigned int n;
740
741 stm32lx_info->probed = 0;
742
743 int retval = stm32lx_read_id_code(bank->target, &device_id);
744 if (retval != ERROR_OK)
745 return retval;
746
747 stm32lx_info->idcode = device_id;
748
749 LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
750
751 for (n = 0; n < ARRAY_SIZE(stm32lx_parts); n++) {
752 if ((device_id & 0xfff) == stm32lx_parts[n].id) {
753 stm32lx_info->part_info = stm32lx_parts[n];
754 break;
755 }
756 }
757
758 if (n == ARRAY_SIZE(stm32lx_parts)) {
759 LOG_WARNING("Cannot identify target as a STM32L family.");
760 return ERROR_FAIL;
761 } else {
762 LOG_INFO("Device: %s", stm32lx_info->part_info.device_str);
763 }
764
765 stm32lx_info->flash_base = stm32lx_info->part_info.flash_base;
766
767 /* Get the flash size from target. */
768 retval = target_read_u16(target, stm32lx_info->part_info.fsize_base,
769 &flash_size_in_kb);
770
771 /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
772 * or 256K, respectively. Please see RM0038 r8 or newer and refer to
773 * section 30.1.1. */
774 if (retval == ERROR_OK && (device_id & 0xfff) == 0x436) {
775 if (flash_size_in_kb == 0)
776 flash_size_in_kb = 384;
777 else if (flash_size_in_kb == 1)
778 flash_size_in_kb = 256;
779 }
780
781 /* 0x429 devices only use the lowest 8 bits of the flash size register */
782 if (retval == ERROR_OK && (device_id & 0xfff) == 0x429) {
783 flash_size_in_kb &= 0xff;
784 }
785
786 /* Failed reading flash size or flash size invalid (early silicon),
787 * default to max target family */
788 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
789 LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
790 stm32lx_info->part_info.max_flash_size_kb);
791 flash_size_in_kb = stm32lx_info->part_info.max_flash_size_kb;
792 } else if (flash_size_in_kb > stm32lx_info->part_info.max_flash_size_kb) {
793 LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
794 flash_size_in_kb, stm32lx_info->part_info.max_flash_size_kb,
795 stm32lx_info->part_info.max_flash_size_kb);
796 flash_size_in_kb = stm32lx_info->part_info.max_flash_size_kb;
797 }
798
799 /* Overwrite default dual-bank configuration */
800 retval = stm32lx_update_part_info(bank, flash_size_in_kb);
801 if (retval != ERROR_OK)
802 return ERROR_FAIL;
803
804 if (stm32lx_info->part_info.has_dual_banks) {
805 /* Use the configured base address to determine if this is the first or second flash bank.
806 * Verify that the base address is reasonably correct and determine the flash bank size
807 */
808 second_bank_base = base_address +
809 stm32lx_info->part_info.first_bank_size_kb * 1024;
810 if (bank->base == second_bank_base || !bank->base) {
811 /* This is the second bank */
812 base_address = second_bank_base;
813 flash_size_in_kb = flash_size_in_kb -
814 stm32lx_info->part_info.first_bank_size_kb;
815 } else if (bank->base == base_address) {
816 /* This is the first bank */
817 flash_size_in_kb = stm32lx_info->part_info.first_bank_size_kb;
818 } else {
819 LOG_WARNING("STM32L flash bank base address config is incorrect. "
820 TARGET_ADDR_FMT " but should rather be 0x%" PRIx32
821 " or 0x%" PRIx32,
822 bank->base, base_address, second_bank_base);
823 return ERROR_FAIL;
824 }
825 LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32,
826 bank->bank_number, flash_size_in_kb, base_address);
827 } else {
828 LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
829 }
830
831 /* if the user sets the size manually then ignore the probed value
832 * this allows us to work around devices that have a invalid flash size register value */
833 if (stm32lx_info->user_bank_size) {
834 flash_size_in_kb = stm32lx_info->user_bank_size / 1024;
835 LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb);
836 }
837
838 /* calculate numbers of sectors (4kB per sector) */
839 int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
840
841 if (bank->sectors) {
842 free(bank->sectors);
843 bank->sectors = NULL;
844 }
845
846 bank->size = flash_size_in_kb * 1024;
847 bank->base = base_address;
848 bank->num_sectors = num_sectors;
849 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
850 if (bank->sectors == NULL) {
851 LOG_ERROR("failed to allocate bank sectors");
852 return ERROR_FAIL;
853 }
854
855 for (i = 0; i < num_sectors; i++) {
856 bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
857 bank->sectors[i].size = FLASH_SECTOR_SIZE;
858 bank->sectors[i].is_erased = -1;
859 bank->sectors[i].is_protected = -1;
860 }
861
862 stm32lx_info->probed = 1;
863
864 return ERROR_OK;
865 }
866
867 static int stm32lx_auto_probe(struct flash_bank *bank)
868 {
869 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
870
871 if (stm32lx_info->probed)
872 return ERROR_OK;
873
874 return stm32lx_probe(bank);
875 }
876
877 /* This method must return a string displaying information about the bank */
878 static int stm32lx_get_info(struct flash_bank *bank, char *buf, int buf_size)
879 {
880 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
881 const struct stm32lx_part_info *info = &stm32lx_info->part_info;
882 uint16_t rev_id = stm32lx_info->idcode >> 16;
883 const char *rev_str = NULL;
884
885 if (!stm32lx_info->probed) {
886 int retval = stm32lx_probe(bank);
887 if (retval != ERROR_OK) {
888 snprintf(buf, buf_size,
889 "Unable to find bank information.");
890 return retval;
891 }
892 }
893
894 for (unsigned int i = 0; i < info->num_revs; i++)
895 if (rev_id == info->revs[i].rev)
896 rev_str = info->revs[i].str;
897
898 if (rev_str != NULL) {
899 snprintf(buf, buf_size,
900 "%s - Rev: %s",
901 info->device_str, rev_str);
902 } else {
903 snprintf(buf, buf_size,
904 "%s - Rev: unknown (0x%04x)",
905 info->device_str, rev_id);
906 }
907
908 return ERROR_OK;
909 }
910
911 static const struct command_registration stm32lx_exec_command_handlers[] = {
912 {
913 .name = "mass_erase",
914 .handler = stm32lx_handle_mass_erase_command,
915 .mode = COMMAND_EXEC,
916 .usage = "bank_id",
917 .help = "Erase entire flash device. including available EEPROM",
918 },
919 {
920 .name = "lock",
921 .handler = stm32lx_handle_lock_command,
922 .mode = COMMAND_EXEC,
923 .usage = "bank_id",
924 .help = "Increase the readout protection to Level 1.",
925 },
926 {
927 .name = "unlock",
928 .handler = stm32lx_handle_unlock_command,
929 .mode = COMMAND_EXEC,
930 .usage = "bank_id",
931 .help = "Lower the readout protection from Level 1 to 0.",
932 },
933 COMMAND_REGISTRATION_DONE
934 };
935
936 static const struct command_registration stm32lx_command_handlers[] = {
937 {
938 .name = "stm32lx",
939 .mode = COMMAND_ANY,
940 .help = "stm32lx flash command group",
941 .usage = "",
942 .chain = stm32lx_exec_command_handlers,
943 },
944 COMMAND_REGISTRATION_DONE
945 };
946
947 const struct flash_driver stm32lx_flash = {
948 .name = "stm32lx",
949 .commands = stm32lx_command_handlers,
950 .flash_bank_command = stm32lx_flash_bank_command,
951 .erase = stm32lx_erase,
952 .write = stm32lx_write,
953 .read = default_flash_read,
954 .probe = stm32lx_probe,
955 .auto_probe = stm32lx_auto_probe,
956 .erase_check = default_flash_blank_check,
957 .protect_check = stm32lx_protect_check,
958 .info = stm32lx_get_info,
959 .free_driver_priv = default_flash_free_driver_priv,
960 };
961
962 /* Static methods implementation */
963 static int stm32lx_unlock_program_memory(struct flash_bank *bank)
964 {
965 struct target *target = bank->target;
966 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
967 int retval;
968 uint32_t reg32;
969
970 /*
971 * Unlocking the program memory is done by unlocking the PECR,
972 * then by writing the 2 PRGKEY to the PRGKEYR register
973 */
974
975 /* check flash is not already unlocked */
976 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
977 &reg32);
978 if (retval != ERROR_OK)
979 return retval;
980
981 if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
982 return ERROR_OK;
983
984 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
985 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
986 PEKEY1);
987 if (retval != ERROR_OK)
988 return retval;
989
990 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
991 PEKEY2);
992 if (retval != ERROR_OK)
993 return retval;
994
995 /* Make sure it worked */
996 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
997 &reg32);
998 if (retval != ERROR_OK)
999 return retval;
1000
1001 if (reg32 & FLASH_PECR__PELOCK) {
1002 LOG_ERROR("PELOCK is not cleared :(");
1003 return ERROR_FLASH_OPERATION_FAILED;
1004 }
1005
1006 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
1007 PRGKEY1);
1008 if (retval != ERROR_OK)
1009 return retval;
1010 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
1011 PRGKEY2);
1012 if (retval != ERROR_OK)
1013 return retval;
1014
1015 /* Make sure it worked */
1016 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1017 &reg32);
1018 if (retval != ERROR_OK)
1019 return retval;
1020
1021 if (reg32 & FLASH_PECR__PRGLOCK) {
1022 LOG_ERROR("PRGLOCK is not cleared :(");
1023 return ERROR_FLASH_OPERATION_FAILED;
1024 }
1025
1026 return ERROR_OK;
1027 }
1028
1029 static int stm32lx_enable_write_half_page(struct flash_bank *bank)
1030 {
1031 struct target *target = bank->target;
1032 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1033 int retval;
1034 uint32_t reg32;
1035
1036 /**
1037 * Unlock the program memory, then set the FPRG bit in the PECR register.
1038 */
1039 retval = stm32lx_unlock_program_memory(bank);
1040 if (retval != ERROR_OK)
1041 return retval;
1042
1043 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1044 &reg32);
1045 if (retval != ERROR_OK)
1046 return retval;
1047
1048 reg32 |= FLASH_PECR__FPRG;
1049 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1050 reg32);
1051 if (retval != ERROR_OK)
1052 return retval;
1053
1054 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1055 &reg32);
1056 if (retval != ERROR_OK)
1057 return retval;
1058
1059 reg32 |= FLASH_PECR__PROG;
1060 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1061 reg32);
1062
1063 return retval;
1064 }
1065
1066 static int stm32lx_lock_program_memory(struct flash_bank *bank)
1067 {
1068 struct target *target = bank->target;
1069 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1070 int retval;
1071 uint32_t reg32;
1072
1073 /* To lock the program memory, simply set the lock bit and lock PECR */
1074
1075 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1076 &reg32);
1077 if (retval != ERROR_OK)
1078 return retval;
1079
1080 reg32 |= FLASH_PECR__PRGLOCK;
1081 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1082 reg32);
1083 if (retval != ERROR_OK)
1084 return retval;
1085
1086 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1087 &reg32);
1088 if (retval != ERROR_OK)
1089 return retval;
1090
1091 reg32 |= FLASH_PECR__PELOCK;
1092 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1093 reg32);
1094 if (retval != ERROR_OK)
1095 return retval;
1096
1097 return ERROR_OK;
1098 }
1099
1100 static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
1101 {
1102 struct target *target = bank->target;
1103 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1104 int retval;
1105 uint32_t reg32;
1106
1107 /*
1108 * To erase a sector (i.e. stm32lx_info->part_info.pages_per_sector pages),
1109 * first unlock the memory, loop over the pages of this sector
1110 * and write 0x0 to its first word.
1111 */
1112
1113 retval = stm32lx_unlock_program_memory(bank);
1114 if (retval != ERROR_OK)
1115 return retval;
1116
1117 for (int page = 0; page < (int)stm32lx_info->part_info.pages_per_sector;
1118 page++) {
1119 reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
1120 retval = target_write_u32(target,
1121 stm32lx_info->flash_base + FLASH_PECR, reg32);
1122 if (retval != ERROR_OK)
1123 return retval;
1124
1125 retval = stm32lx_wait_until_bsy_clear(bank);
1126 if (retval != ERROR_OK)
1127 return retval;
1128
1129 uint32_t addr = bank->base + bank->sectors[sector].offset + (page
1130 * stm32lx_info->part_info.page_size);
1131 retval = target_write_u32(target, addr, 0x0);
1132 if (retval != ERROR_OK)
1133 return retval;
1134
1135 retval = stm32lx_wait_until_bsy_clear(bank);
1136 if (retval != ERROR_OK)
1137 return retval;
1138 }
1139
1140 retval = stm32lx_lock_program_memory(bank);
1141 if (retval != ERROR_OK)
1142 return retval;
1143
1144 return ERROR_OK;
1145 }
1146
1147 static inline int stm32lx_get_flash_status(struct flash_bank *bank, uint32_t *status)
1148 {
1149 struct target *target = bank->target;
1150 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1151
1152 return target_read_u32(target, stm32lx_info->flash_base + FLASH_SR, status);
1153 }
1154
1155 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
1156 {
1157 return stm32lx_wait_until_bsy_clear_timeout(bank, 100);
1158 }
1159
1160 static int stm32lx_unlock_options_bytes(struct flash_bank *bank)
1161 {
1162 struct target *target = bank->target;
1163 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1164 int retval;
1165 uint32_t reg32;
1166
1167 /*
1168 * Unlocking the options bytes is done by unlocking the PECR,
1169 * then by writing the 2 FLASH_PEKEYR to the FLASH_OPTKEYR register
1170 */
1171
1172 /* check flash is not already unlocked */
1173 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
1174 if (retval != ERROR_OK)
1175 return retval;
1176
1177 if ((reg32 & FLASH_PECR__OPTLOCK) == 0)
1178 return ERROR_OK;
1179
1180 if ((reg32 & FLASH_PECR__PELOCK) != 0) {
1181
1182 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY1);
1183 if (retval != ERROR_OK)
1184 return retval;
1185
1186 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY2);
1187 if (retval != ERROR_OK)
1188 return retval;
1189 }
1190
1191 /* To unlock the PECR write the 2 OPTKEY to the FLASH_OPTKEYR register */
1192 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY1);
1193 if (retval != ERROR_OK)
1194 return retval;
1195
1196 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY2);
1197 if (retval != ERROR_OK)
1198 return retval;
1199
1200 return ERROR_OK;
1201 }
1202
1203 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout)
1204 {
1205 struct target *target = bank->target;
1206 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1207 uint32_t status;
1208 int retval = ERROR_OK;
1209
1210 /* wait for busy to clear */
1211 for (;;) {
1212 retval = stm32lx_get_flash_status(bank, &status);
1213 if (retval != ERROR_OK)
1214 return retval;
1215
1216 LOG_DEBUG("status: 0x%" PRIx32 "", status);
1217 if ((status & FLASH_SR__BSY) == 0)
1218 break;
1219
1220 if (timeout-- <= 0) {
1221 LOG_ERROR("timed out waiting for flash");
1222 return ERROR_FAIL;
1223 }
1224 alive_sleep(1);
1225 }
1226
1227 if (status & FLASH_SR__WRPERR) {
1228 LOG_ERROR("access denied / write protected");
1229 retval = ERROR_FAIL;
1230 }
1231
1232 if (status & FLASH_SR__PGAERR) {
1233 LOG_ERROR("invalid program address");
1234 retval = ERROR_FAIL;
1235 }
1236
1237 /* Clear but report errors */
1238 if (status & FLASH_SR__OPTVERR) {
1239 /* If this operation fails, we ignore it and report the original retval */
1240 target_write_u32(target, stm32lx_info->flash_base + FLASH_SR, status & FLASH_SR__OPTVERR);
1241 }
1242
1243 return retval;
1244 }
1245
1246 static int stm32lx_obl_launch(struct flash_bank *bank)
1247 {
1248 struct target *target = bank->target;
1249 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1250 int retval;
1251
1252 /* This will fail as the target gets immediately rebooted */
1253 target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1254 FLASH_PECR__OBL_LAUNCH);
1255
1256 size_t tries = 10;
1257 do {
1258 target_halt(target);
1259 retval = target_poll(target);
1260 } while (--tries > 0 &&
1261 (retval != ERROR_OK || target->state != TARGET_HALTED));
1262
1263 return tries ? ERROR_OK : ERROR_FAIL;
1264 }
1265
1266 static int stm32lx_lock(struct flash_bank *bank)
1267 {
1268 int retval;
1269 struct target *target = bank->target;
1270
1271 if (target->state != TARGET_HALTED) {
1272 LOG_ERROR("Target not halted");
1273 return ERROR_TARGET_NOT_HALTED;
1274 }
1275
1276 retval = stm32lx_unlock_options_bytes(bank);
1277 if (retval != ERROR_OK)
1278 return retval;
1279
1280 /* set the RDP protection level to 1 */
1281 retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR1);
1282 if (retval != ERROR_OK)
1283 return retval;
1284
1285 return ERROR_OK;
1286 }
1287
1288 static int stm32lx_unlock(struct flash_bank *bank)
1289 {
1290 int retval;
1291 struct target *target = bank->target;
1292
1293 if (target->state != TARGET_HALTED) {
1294 LOG_ERROR("Target not halted");
1295 return ERROR_TARGET_NOT_HALTED;
1296 }
1297
1298 retval = stm32lx_unlock_options_bytes(bank);
1299 if (retval != ERROR_OK)
1300 return retval;
1301
1302 /* set the RDP protection level to 0 */
1303 retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR0);
1304 if (retval != ERROR_OK)
1305 return retval;
1306
1307 retval = stm32lx_wait_until_bsy_clear_timeout(bank, 30000);
1308 if (retval != ERROR_OK)
1309 return retval;
1310
1311 return ERROR_OK;
1312 }
1313
1314 static int stm32lx_mass_erase(struct flash_bank *bank)
1315 {
1316 int retval;
1317 struct target *target = bank->target;
1318 struct stm32lx_flash_bank *stm32lx_info = NULL;
1319 uint32_t reg32;
1320
1321 if (target->state != TARGET_HALTED) {
1322 LOG_ERROR("Target not halted");
1323 return ERROR_TARGET_NOT_HALTED;
1324 }
1325
1326 stm32lx_info = bank->driver_priv;
1327
1328 retval = stm32lx_lock(bank);
1329 if (retval != ERROR_OK)
1330 return retval;
1331
1332 retval = stm32lx_obl_launch(bank);
1333 if (retval != ERROR_OK)
1334 return retval;
1335
1336 retval = stm32lx_unlock(bank);
1337 if (retval != ERROR_OK)
1338 return retval;
1339
1340 retval = stm32lx_obl_launch(bank);
1341 if (retval != ERROR_OK)
1342 return retval;
1343
1344 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
1345 if (retval != ERROR_OK)
1346 return retval;
1347
1348 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR, reg32 | FLASH_PECR__OPTLOCK);
1349 if (retval != ERROR_OK)
1350 return retval;
1351
1352 return ERROR_OK;
1353 }
1354
1355 static int stm32lx_update_part_info(struct flash_bank *bank, uint16_t flash_size_in_kb)
1356 {
1357 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1358
1359 switch (stm32lx_info->part_info.id) {
1360 case 0x447: /* STM32L0xx (Cat.5) devices */
1361 if (flash_size_in_kb == 192 || flash_size_in_kb == 128) {
1362 stm32lx_info->part_info.first_bank_size_kb = flash_size_in_kb / 2;
1363 stm32lx_info->part_info.has_dual_banks = true;
1364 }
1365 break;
1366 case 0x437: /* STM32L1xx (Cat.5/Cat.6) */
1367 stm32lx_info->part_info.first_bank_size_kb = flash_size_in_kb / 2;
1368 break;
1369 }
1370
1371 return ERROR_OK;
1372 }
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