Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
Clean up many C99 integer types format specifiers
[openocd.git] / src / flash / nor / stm32lx.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35 #include <target/cortex_m.h>
36
37 /* stm32lx flash register locations */
38
39 #define FLASH_BASE 0x40023C00
40 #define FLASH_ACR 0x40023C00
41 #define FLASH_PECR 0x40023C04
42 #define FLASH_PDKEYR 0x40023C08
43 #define FLASH_PEKEYR 0x40023C0C
44 #define FLASH_PRGKEYR 0x40023C10
45 #define FLASH_OPTKEYR 0x40023C14
46 #define FLASH_SR 0x40023C18
47 #define FLASH_OBR 0x40023C1C
48 #define FLASH_WRPR 0x40023C20
49
50 /* FLASH_ACR bites */
51 #define FLASH_ACR__LATENCY (1<<0)
52 #define FLASH_ACR__PRFTEN (1<<1)
53 #define FLASH_ACR__ACC64 (1<<2)
54 #define FLASH_ACR__SLEEP_PD (1<<3)
55 #define FLASH_ACR__RUN_PD (1<<4)
56
57 /* FLASH_PECR bits */
58 #define FLASH_PECR__PELOCK (1<<0)
59 #define FLASH_PECR__PRGLOCK (1<<1)
60 #define FLASH_PECR__OPTLOCK (1<<2)
61 #define FLASH_PECR__PROG (1<<3)
62 #define FLASH_PECR__DATA (1<<4)
63 #define FLASH_PECR__FTDW (1<<8)
64 #define FLASH_PECR__ERASE (1<<9)
65 #define FLASH_PECR__FPRG (1<<10)
66 #define FLASH_PECR__EOPIE (1<<16)
67 #define FLASH_PECR__ERRIE (1<<17)
68 #define FLASH_PECR__OBL_LAUNCH (1<<18)
69
70 /* FLASH_SR bits */
71 #define FLASH_SR__BSY (1<<0)
72 #define FLASH_SR__EOP (1<<1)
73 #define FLASH_SR__ENDHV (1<<2)
74 #define FLASH_SR__READY (1<<3)
75 #define FLASH_SR__WRPERR (1<<8)
76 #define FLASH_SR__PGAERR (1<<9)
77 #define FLASH_SR__SIZERR (1<<10)
78 #define FLASH_SR__OPTVERR (1<<11)
79
80 /* Unlock keys */
81 #define PEKEY1 0x89ABCDEF
82 #define PEKEY2 0x02030405
83 #define PRGKEY1 0x8C9DAEBF
84 #define PRGKEY2 0x13141516
85 #define OPTKEY1 0xFBEAD9C8
86 #define OPTKEY2 0x24252627
87
88 /* other registers */
89 #define DBGMCU_IDCODE 0xE0042000
90 #define F_SIZE 0x1FF8004C
91 #define F_SIZE_MP 0x1FF800CC /* on 0x427 Medium+ and 0x436 HD devices */
92
93 /* Constants */
94 #define FLASH_PAGE_SIZE 256
95 #define FLASH_SECTOR_SIZE 4096
96 #define FLASH_PAGES_PER_SECTOR 16
97 #define FLASH_BANK0_ADDRESS 0x08000000
98
99 /* stm32lx option byte register location */
100 #define OB_RDP 0x1FF80000
101 #define OB_USER 0x1FF80004
102 #define OB_WRP0_1 0x1FF80008
103 #define OB_WRP2_3 0x1FF8000C
104
105 /* OB_RDP values */
106 #define OB_RDP__LEVEL0 0xFF5500AA
107 #define OB_RDP__LEVEL1 0xFFFF0000
108
109 /* stm32lx RCC register locations */
110 #define RCC_CR 0x40023800
111 #define RCC_ICSCR 0x40023804
112 #define RCC_CFGR 0x40023808
113
114 /* RCC_ICSCR bits */
115 #define RCC_ICSCR__MSIRANGE_MASK (7<<13)
116
117 static int stm32lx_unlock_program_memory(struct flash_bank *bank);
118 static int stm32lx_lock_program_memory(struct flash_bank *bank);
119 static int stm32lx_enable_write_half_page(struct flash_bank *bank);
120 static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
121 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
122
123 struct stm32lx_flash_bank {
124 int probed;
125 bool has_dual_banks;
126 uint32_t user_bank_size;
127 };
128
129 /* flash bank stm32lx <base> <size> 0 0 <target#>
130 */
131 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
132 {
133 struct stm32lx_flash_bank *stm32lx_info;
134 if (CMD_ARGC < 6)
135 return ERROR_COMMAND_SYNTAX_ERROR;
136
137 /* Create the bank structure */
138 stm32lx_info = malloc(sizeof(struct stm32lx_flash_bank));
139
140 /* Check allocation */
141 if (stm32lx_info == NULL) {
142 LOG_ERROR("failed to allocate bank structure");
143 return ERROR_FAIL;
144 }
145
146 bank->driver_priv = stm32lx_info;
147
148 stm32lx_info->probed = 0;
149 stm32lx_info->has_dual_banks = false;
150 stm32lx_info->user_bank_size = bank->size;
151
152 return ERROR_OK;
153 }
154
155 static int stm32lx_protect_check(struct flash_bank *bank)
156 {
157 int retval;
158 struct target *target = bank->target;
159
160 uint32_t wrpr;
161
162 /*
163 * Read the WRPR word, and check each bit (corresponding to each
164 * flash sector
165 */
166 retval = target_read_u32(target, FLASH_WRPR, &wrpr);
167 if (retval != ERROR_OK)
168 return retval;
169
170 for (int i = 0; i < 32; i++) {
171 if (wrpr & (1 << i))
172 bank->sectors[i].is_protected = 1;
173 else
174 bank->sectors[i].is_protected = 0;
175 }
176 return ERROR_OK;
177 }
178
179 static int stm32lx_erase(struct flash_bank *bank, int first, int last)
180 {
181 int retval;
182
183 /*
184 * It could be possible to do a mass erase if all sectors must be
185 * erased, but it is not implemented yet.
186 */
187
188 if (bank->target->state != TARGET_HALTED) {
189 LOG_ERROR("Target not halted");
190 return ERROR_TARGET_NOT_HALTED;
191 }
192
193 /*
194 * Loop over the selected sectors and erase them
195 */
196 for (int i = first; i <= last; i++) {
197 retval = stm32lx_erase_sector(bank, i);
198 if (retval != ERROR_OK)
199 return retval;
200 bank->sectors[i].is_erased = 1;
201 }
202 return ERROR_OK;
203 }
204
205 static int stm32lx_protect(struct flash_bank *bank, int set, int first,
206 int last)
207 {
208 LOG_WARNING("protection of the STM32L flash is not implemented");
209 return ERROR_OK;
210 }
211
212 static int stm32lx_write_half_pages(struct flash_bank *bank, uint8_t *buffer,
213 uint32_t offset, uint32_t count)
214 {
215 struct target *target = bank->target;
216 uint32_t buffer_size = 16384;
217 struct working_area *write_algorithm;
218 struct working_area *source;
219 uint32_t address = bank->base + offset;
220
221 struct reg_param reg_params[3];
222 struct armv7m_algorithm armv7m_info;
223
224 int retval = ERROR_OK;
225
226 /* see contib/loaders/flash/stm32lx.S for src */
227
228 static const uint8_t stm32lx_flash_write_code[] = {
229 /* write_word: */
230 0x00, 0x23, /* movs r3, #0 */
231 0x04, 0xe0, /* b test_done */
232
233 /* write_word: */
234 0x51, 0xf8, 0x04, 0xcb, /* ldr ip, [r1], #4 */
235 0x40, 0xf8, 0x04, 0xcb, /* str ip, [r0], #4 */
236 0x01, 0x33, /* adds r3, #1 */
237
238 /* test_done: */
239 0x93, 0x42, /* cmp r3, r2 */
240 0xf8, 0xd3, /* bcc write_word */
241 0x00, 0xbe, /* bkpt 0 */
242 };
243
244 /* Check if there is an even number of half pages (128bytes) */
245 if (count % 128) {
246 LOG_ERROR("there should be an even number "
247 "of half pages = 128 bytes (count = %" PRIi32 " bytes)", count);
248 return ERROR_FAIL;
249 }
250
251 /* flash write code */
252 if (target_alloc_working_area(target, sizeof(stm32lx_flash_write_code),
253 &write_algorithm) != ERROR_OK) {
254 LOG_DEBUG("no working area for block memory writes");
255 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
256 };
257
258 /* Write the flashing code */
259 retval = target_write_buffer(target,
260 write_algorithm->address,
261 sizeof(stm32lx_flash_write_code),
262 (uint8_t *)stm32lx_flash_write_code);
263 if (retval != ERROR_OK) {
264 target_free_working_area(target, write_algorithm);
265 return retval;
266 }
267
268 /* Allocate half pages memory */
269 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
270 if (buffer_size > 1024)
271 buffer_size -= 1024;
272 else
273 buffer_size /= 2;
274
275 if (buffer_size <= 256) {
276 /* we already allocated the writing code, but failed to get a
277 * buffer, free the algorithm */
278 target_free_working_area(target, write_algorithm);
279
280 LOG_WARNING("no large enough working area available, can't do block memory writes");
281 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
282 }
283 }
284
285 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
286 armv7m_info.core_mode = ARM_MODE_THREAD;
287 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
288 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
289 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
290
291 /* Enable half-page write */
292 retval = stm32lx_enable_write_half_page(bank);
293 if (retval != ERROR_OK) {
294 target_free_working_area(target, source);
295 target_free_working_area(target, write_algorithm);
296
297 destroy_reg_param(&reg_params[0]);
298 destroy_reg_param(&reg_params[1]);
299 destroy_reg_param(&reg_params[2]);
300 return retval;
301 }
302
303 struct armv7m_common *armv7m = target_to_armv7m(target);
304 if (armv7m == NULL) {
305
306 /* something is very wrong if armv7m is NULL */
307 LOG_ERROR("unable to get armv7m target");
308 return retval;
309 }
310
311 /* save any DEMCR flags and configure target to catch any Hard Faults */
312 uint32_t demcr_save = armv7m->demcr;
313 armv7m->demcr = VC_HARDERR;
314
315 /* Loop while there are bytes to write */
316 while (count > 0) {
317 uint32_t this_count;
318 this_count = (count > buffer_size) ? buffer_size : count;
319
320 /* Write the next half pages */
321 retval = target_write_buffer(target, source->address, this_count, buffer);
322 if (retval != ERROR_OK)
323 break;
324
325 /* 4: Store useful information in the registers */
326 /* the destination address of the copy (R0) */
327 buf_set_u32(reg_params[0].value, 0, 32, address);
328 /* The source address of the copy (R1) */
329 buf_set_u32(reg_params[1].value, 0, 32, source->address);
330 /* The length of the copy (R2) */
331 buf_set_u32(reg_params[2].value, 0, 32, this_count / 4);
332
333 /* 5: Execute the bunch of code */
334 retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params)
335 / sizeof(*reg_params), reg_params,
336 write_algorithm->address, 0, 10000, &armv7m_info);
337 if (retval != ERROR_OK)
338 break;
339
340 /* check for Hard Fault */
341 if (armv7m->exception_number == 3)
342 break;
343
344 /* 6: Wait while busy */
345 retval = stm32lx_wait_until_bsy_clear(bank);
346 if (retval != ERROR_OK)
347 break;
348
349 buffer += this_count;
350 address += this_count;
351 count -= this_count;
352 }
353
354 /* restore previous flags */
355 armv7m->demcr = demcr_save;
356
357 if (armv7m->exception_number == 3) {
358
359 /* the stm32l15x devices seem to have an issue when blank.
360 * if a ram loader is executed on a blank device it will
361 * Hard Fault, this issue does not happen for a already programmed device.
362 * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
363 * The workaround of handling the Hard Fault exception does work, but makes the
364 * loader more complicated, as a compromise we manually write the pages, programming time
365 * is reduced by 50% using this slower method.
366 */
367
368 LOG_WARNING("couldn't use loader, falling back to page memory writes");
369
370 while (count > 0) {
371 uint32_t this_count;
372 this_count = (count > 128) ? 128 : count;
373
374 /* Write the next half pages */
375 retval = target_write_buffer(target, address, this_count, buffer);
376 if (retval != ERROR_OK)
377 break;
378
379 /* Wait while busy */
380 retval = stm32lx_wait_until_bsy_clear(bank);
381 if (retval != ERROR_OK)
382 break;
383
384 buffer += this_count;
385 address += this_count;
386 count -= this_count;
387 }
388 }
389
390 if (retval == ERROR_OK)
391 retval = stm32lx_lock_program_memory(bank);
392
393 target_free_working_area(target, source);
394 target_free_working_area(target, write_algorithm);
395
396 destroy_reg_param(&reg_params[0]);
397 destroy_reg_param(&reg_params[1]);
398 destroy_reg_param(&reg_params[2]);
399
400 return retval;
401 }
402
403 static int stm32lx_write(struct flash_bank *bank, uint8_t *buffer,
404 uint32_t offset, uint32_t count)
405 {
406 struct target *target = bank->target;
407
408 uint32_t halfpages_number;
409 uint32_t bytes_remaining = 0;
410 uint32_t address = bank->base + offset;
411 uint32_t bytes_written = 0;
412 int retval, retval2;
413
414 if (bank->target->state != TARGET_HALTED) {
415 LOG_ERROR("Target not halted");
416 return ERROR_TARGET_NOT_HALTED;
417 }
418
419 if (offset & 0x3) {
420 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
421 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
422 }
423
424 retval = stm32lx_unlock_program_memory(bank);
425 if (retval != ERROR_OK)
426 return retval;
427
428 /* first we need to write any unaligned head bytes upto
429 * the next 128 byte page */
430
431 if (offset % 128)
432 bytes_remaining = MIN(count, 128 - (offset % 128));
433
434 while (bytes_remaining > 0) {
435 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
436
437 /* copy remaining bytes into the write buffer */
438 uint32_t bytes_to_write = MIN(4, bytes_remaining);
439 memcpy(value, buffer + bytes_written, bytes_to_write);
440
441 retval = target_write_buffer(target, address, 4, value);
442 if (retval != ERROR_OK)
443 goto reset_pg_and_lock;
444
445 bytes_written += bytes_to_write;
446 bytes_remaining -= bytes_to_write;
447 address += 4;
448
449 retval = stm32lx_wait_until_bsy_clear(bank);
450 if (retval != ERROR_OK)
451 goto reset_pg_and_lock;
452 }
453
454 offset += bytes_written;
455 count -= bytes_written;
456
457 /* this should always pass this check here */
458 assert((offset % 128) == 0);
459
460 /* calculate half pages */
461 halfpages_number = count / 128;
462
463 if (halfpages_number) {
464 retval = stm32lx_write_half_pages(bank, buffer + bytes_written, offset, 128 * halfpages_number);
465 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
466 /* attempt slow memory writes */
467 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
468 halfpages_number = 0;
469 } else {
470 if (retval != ERROR_OK)
471 return ERROR_FAIL;
472 }
473 }
474
475 /* write any remaining bytes */
476 uint32_t page_bytes_written = 128 * halfpages_number;
477 bytes_written += page_bytes_written;
478 address += page_bytes_written;
479 bytes_remaining = count - page_bytes_written;
480
481 retval = stm32lx_unlock_program_memory(bank);
482 if (retval != ERROR_OK)
483 return retval;
484
485 while (bytes_remaining > 0) {
486 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
487
488 /* copy remaining bytes into the write buffer */
489 uint32_t bytes_to_write = MIN(4, bytes_remaining);
490 memcpy(value, buffer + bytes_written, bytes_to_write);
491
492 retval = target_write_buffer(target, address, 4, value);
493 if (retval != ERROR_OK)
494 goto reset_pg_and_lock;
495
496 bytes_written += bytes_to_write;
497 bytes_remaining -= bytes_to_write;
498 address += 4;
499
500 retval = stm32lx_wait_until_bsy_clear(bank);
501 if (retval != ERROR_OK)
502 goto reset_pg_and_lock;
503 }
504
505 reset_pg_and_lock:
506 retval2 = stm32lx_lock_program_memory(bank);
507 if (retval == ERROR_OK)
508 retval = retval2;
509
510 return retval;
511 }
512
513 static int stm32lx_probe(struct flash_bank *bank)
514 {
515 struct target *target = bank->target;
516 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
517 int i;
518 uint16_t flash_size_in_kb;
519 uint16_t max_flash_size_in_kb;
520 uint32_t device_id;
521 uint32_t base_address = FLASH_BANK0_ADDRESS;
522 uint32_t second_bank_base;
523 uint32_t first_bank_size_in_kb;
524
525 stm32lx_info->probed = 0;
526
527 /* read stm32 device id register */
528 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
529 if (retval != ERROR_OK)
530 return retval;
531
532 LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
533
534 /* set max flash size depending on family */
535 switch (device_id & 0xfff) {
536 case 0x416:
537 max_flash_size_in_kb = 128;
538 break;
539 case 0x427:
540 /* single bank, high density */
541 max_flash_size_in_kb = 256;
542 break;
543 case 0x436:
544 /* According to ST, the devices with id 0x436 have dual bank flash and comes with
545 * a total flash size of 384k or 256kb. However, the first bank is always 192kb,
546 * and second one holds the rest. The reason is that the 256kb version is actually
547 * the same physical flash but only the first 256kb are verified.
548 */
549 max_flash_size_in_kb = 384;
550 first_bank_size_in_kb = 192;
551 stm32lx_info->has_dual_banks = true;
552 break;
553 default:
554 LOG_WARNING("Cannot identify target as a STM32L family.");
555 return ERROR_FAIL;
556 }
557
558 /* Get the flash size from target. 0x427 and 0x436 devices use a
559 * different location for the Flash Size register, please see RM0038 r8 or
560 * newer. */
561 if ((device_id & 0xfff) == 0x427 || (device_id & 0xfff) == 0x436)
562 retval = target_read_u16(target, F_SIZE_MP, &flash_size_in_kb);
563 else
564 retval = target_read_u16(target, F_SIZE, &flash_size_in_kb);
565
566 /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
567 * or 256K, respectively. Please see RM0038 r8 or newer and refer to
568 * section 30.1.1. */
569 if (retval == ERROR_OK && (device_id & 0xfff) == 0x436) {
570 if (flash_size_in_kb == 0)
571 flash_size_in_kb = 384;
572 else if (flash_size_in_kb == 1)
573 flash_size_in_kb = 256;
574 }
575
576 /* Failed reading flash size or flash size invalid (early silicon),
577 * default to max target family */
578 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
579 LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
580 max_flash_size_in_kb);
581 flash_size_in_kb = max_flash_size_in_kb;
582 } else if (flash_size_in_kb > max_flash_size_in_kb) {
583 LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
584 flash_size_in_kb, max_flash_size_in_kb, max_flash_size_in_kb);
585 flash_size_in_kb = max_flash_size_in_kb;
586 }
587
588 if (stm32lx_info->has_dual_banks) {
589 /* Use the configured base address to determine if this is the first or second flash bank.
590 * Verify that the base address is reasonably correct and determine the flash bank size
591 */
592 second_bank_base = base_address + first_bank_size_in_kb * 1024;
593 if (bank->base == second_bank_base) {
594 /* This is the second bank */
595 base_address = second_bank_base;
596 flash_size_in_kb = flash_size_in_kb - first_bank_size_in_kb;
597 } else if (bank->base == 0 || bank->base == base_address) {
598 /* This is the first bank */
599 flash_size_in_kb = first_bank_size_in_kb;
600 } else {
601 LOG_WARNING("STM32L flash bank base address config is incorrect."
602 " 0x%" PRIx32 " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
603 bank->base, base_address, second_bank_base);
604 return ERROR_FAIL;
605 }
606 LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32,
607 bank->bank_number, flash_size_in_kb, base_address);
608 } else {
609 LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
610 }
611
612 /* if the user sets the size manually then ignore the probed value
613 * this allows us to work around devices that have a invalid flash size register value */
614 if (stm32lx_info->user_bank_size) {
615 flash_size_in_kb = stm32lx_info->user_bank_size / 1024;
616 LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb);
617 }
618
619 /* STM32L - we have 32 sectors, 16 pages per sector -> 512 pages
620 * 16 pages for a protection area */
621
622 /* calculate numbers of sectors (4kB per sector) */
623 int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
624
625 if (bank->sectors) {
626 free(bank->sectors);
627 bank->sectors = NULL;
628 }
629
630 bank->size = flash_size_in_kb * 1024;
631 bank->base = base_address;
632 bank->num_sectors = num_sectors;
633 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
634 if (bank->sectors == NULL) {
635 LOG_ERROR("failed to allocate bank sectors");
636 return ERROR_FAIL;
637 }
638
639 for (i = 0; i < num_sectors; i++) {
640 bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
641 bank->sectors[i].size = FLASH_SECTOR_SIZE;
642 bank->sectors[i].is_erased = -1;
643 bank->sectors[i].is_protected = 1;
644 }
645
646 stm32lx_info->probed = 1;
647
648 return ERROR_OK;
649 }
650
651 static int stm32lx_auto_probe(struct flash_bank *bank)
652 {
653 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
654
655 if (stm32lx_info->probed)
656 return ERROR_OK;
657
658 return stm32lx_probe(bank);
659 }
660
661 static int stm32lx_erase_check(struct flash_bank *bank)
662 {
663 struct target *target = bank->target;
664 const int buffer_size = 4096;
665 int i;
666 uint32_t nBytes;
667 int retval = ERROR_OK;
668
669 if (bank->target->state != TARGET_HALTED) {
670 LOG_ERROR("Target not halted");
671 return ERROR_TARGET_NOT_HALTED;
672 }
673
674 uint8_t *buffer = malloc(buffer_size);
675 if (buffer == NULL) {
676 LOG_ERROR("failed to allocate read buffer");
677 return ERROR_FAIL;
678 }
679
680 for (i = 0; i < bank->num_sectors; i++) {
681 uint32_t j;
682 bank->sectors[i].is_erased = 1;
683
684 /* Loop chunk by chunk over the sector */
685 for (j = 0; j < bank->sectors[i].size; j += buffer_size) {
686 uint32_t chunk;
687 chunk = buffer_size;
688 if (chunk > (j - bank->sectors[i].size))
689 chunk = (j - bank->sectors[i].size);
690
691 retval = target_read_memory(target, bank->base
692 + bank->sectors[i].offset + j, 4, chunk / 4, buffer);
693 if (retval != ERROR_OK)
694 break;
695
696 for (nBytes = 0; nBytes < chunk; nBytes++) {
697 if (buffer[nBytes] != 0x00) {
698 bank->sectors[i].is_erased = 0;
699 break;
700 }
701 }
702 }
703 if (retval != ERROR_OK)
704 break;
705 }
706 free(buffer);
707
708 return retval;
709 }
710
711 static int stm32lx_get_info(struct flash_bank *bank, char *buf, int buf_size)
712 {
713 /* This method must return a string displaying information about the bank */
714
715 uint32_t dbgmcu_idcode;
716
717 /* read stm32 device id register */
718 int retval = target_read_u32(bank->target, DBGMCU_IDCODE, &dbgmcu_idcode);
719 if (retval != ERROR_OK)
720 return retval;
721
722 uint16_t device_id = dbgmcu_idcode & 0xfff;
723 uint16_t rev_id = dbgmcu_idcode >> 16;
724 const char *device_str;
725 const char *rev_str = NULL;
726
727 switch (device_id) {
728 case 0x416:
729 device_str = "STM32L1xx (Low/Medium Density)";
730
731 switch (rev_id) {
732 case 0x1000:
733 rev_str = "A";
734 break;
735
736 case 0x1008:
737 rev_str = "Y";
738 break;
739
740 case 0x1018:
741 rev_str = "X";
742 break;
743
744 case 0x1038:
745 rev_str = "W";
746 break;
747
748 case 0x1078:
749 rev_str = "V";
750 break;
751 }
752 break;
753
754 case 0x427:
755 device_str = "STM32L1xx (Medium+ Density)";
756
757 switch (rev_id) {
758 case 0x1018:
759 rev_str = "A";
760 break;
761 }
762 break;
763
764 case 0x436:
765 device_str = "STM32L1xx (Medium+/High Density)";
766
767 switch (rev_id) {
768 case 0x1000:
769 rev_str = "A";
770 break;
771
772 case 0x1008:
773 rev_str = "Z";
774 break;
775
776 case 0x1018:
777 rev_str = "Y";
778 break;
779 }
780 break;
781
782 default:
783 snprintf(buf, buf_size, "Cannot identify target as a STM32L1");
784 return ERROR_FAIL;
785 }
786
787 if (rev_str != NULL)
788 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
789 else
790 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
791
792 return ERROR_OK;
793 }
794
795 static const struct command_registration stm32lx_exec_command_handlers[] = {
796 COMMAND_REGISTRATION_DONE
797 };
798
799 static const struct command_registration stm32lx_command_handlers[] = {
800 {
801 .name = "stm32lx",
802 .mode = COMMAND_ANY,
803 .help = "stm32lx flash command group",
804 .usage = "",
805 .chain = stm32lx_exec_command_handlers,
806 },
807 COMMAND_REGISTRATION_DONE
808 };
809
810 struct flash_driver stm32lx_flash = {
811 .name = "stm32lx",
812 .commands = stm32lx_command_handlers,
813 .flash_bank_command = stm32lx_flash_bank_command,
814 .erase = stm32lx_erase,
815 .protect = stm32lx_protect,
816 .write = stm32lx_write,
817 .read = default_flash_read,
818 .probe = stm32lx_probe,
819 .auto_probe = stm32lx_auto_probe,
820 .erase_check = stm32lx_erase_check,
821 .protect_check = stm32lx_protect_check,
822 .info = stm32lx_get_info,
823 };
824
825 /* Static methods implementation */
826 static int stm32lx_unlock_program_memory(struct flash_bank *bank)
827 {
828 struct target *target = bank->target;
829 int retval;
830 uint32_t reg32;
831
832 /*
833 * Unlocking the program memory is done by unlocking the PECR,
834 * then by writing the 2 PRGKEY to the PRGKEYR register
835 */
836
837 /* check flash is not already unlocked */
838 retval = target_read_u32(target, FLASH_PECR, &reg32);
839 if (retval != ERROR_OK)
840 return retval;
841
842 if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
843 return ERROR_OK;
844
845 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
846 retval = target_write_u32(target, FLASH_PEKEYR, PEKEY1);
847 if (retval != ERROR_OK)
848 return retval;
849
850 retval = target_write_u32(target, FLASH_PEKEYR, PEKEY2);
851 if (retval != ERROR_OK)
852 return retval;
853
854 /* Make sure it worked */
855 retval = target_read_u32(target, FLASH_PECR, &reg32);
856 if (retval != ERROR_OK)
857 return retval;
858
859 if (reg32 & FLASH_PECR__PELOCK) {
860 LOG_ERROR("PELOCK is not cleared :(");
861 return ERROR_FLASH_OPERATION_FAILED;
862 }
863
864 retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY1);
865 if (retval != ERROR_OK)
866 return retval;
867 retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY2);
868 if (retval != ERROR_OK)
869 return retval;
870
871 /* Make sure it worked */
872 retval = target_read_u32(target, FLASH_PECR, &reg32);
873 if (retval != ERROR_OK)
874 return retval;
875
876 if (reg32 & FLASH_PECR__PRGLOCK) {
877 LOG_ERROR("PRGLOCK is not cleared :(");
878 return ERROR_FLASH_OPERATION_FAILED;
879 }
880
881 return ERROR_OK;
882 }
883
884 static int stm32lx_enable_write_half_page(struct flash_bank *bank)
885 {
886 struct target *target = bank->target;
887 int retval;
888 uint32_t reg32;
889
890 /**
891 * Unlock the program memory, then set the FPRG bit in the PECR register.
892 */
893 retval = stm32lx_unlock_program_memory(bank);
894 if (retval != ERROR_OK)
895 return retval;
896
897 retval = target_read_u32(target, FLASH_PECR, &reg32);
898 if (retval != ERROR_OK)
899 return retval;
900
901 reg32 |= FLASH_PECR__FPRG;
902 retval = target_write_u32(target, FLASH_PECR, reg32);
903 if (retval != ERROR_OK)
904 return retval;
905
906 retval = target_read_u32(target, FLASH_PECR, &reg32);
907 if (retval != ERROR_OK)
908 return retval;
909
910 reg32 |= FLASH_PECR__PROG;
911 retval = target_write_u32(target, FLASH_PECR, reg32);
912
913 return retval;
914 }
915
916 static int stm32lx_lock_program_memory(struct flash_bank *bank)
917 {
918 struct target *target = bank->target;
919 int retval;
920 uint32_t reg32;
921
922 /* To lock the program memory, simply set the lock bit and lock PECR */
923
924 retval = target_read_u32(target, FLASH_PECR, &reg32);
925 if (retval != ERROR_OK)
926 return retval;
927
928 reg32 |= FLASH_PECR__PRGLOCK;
929 retval = target_write_u32(target, FLASH_PECR, reg32);
930 if (retval != ERROR_OK)
931 return retval;
932
933 retval = target_read_u32(target, FLASH_PECR, &reg32);
934 if (retval != ERROR_OK)
935 return retval;
936
937 reg32 |= FLASH_PECR__PELOCK;
938 retval = target_write_u32(target, FLASH_PECR, reg32);
939 if (retval != ERROR_OK)
940 return retval;
941
942 return ERROR_OK;
943 }
944
945 static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
946 {
947 struct target *target = bank->target;
948 int retval;
949 uint32_t reg32;
950
951 /*
952 * To erase a sector (i.e. FLASH_PAGES_PER_SECTOR pages),
953 * first unlock the memory, loop over the pages of this sector
954 * and write 0x0 to its first word.
955 */
956
957 retval = stm32lx_unlock_program_memory(bank);
958 if (retval != ERROR_OK)
959 return retval;
960
961 for (int page = 0; page < FLASH_PAGES_PER_SECTOR; page++) {
962 reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
963 retval = target_write_u32(target, FLASH_PECR, reg32);
964 if (retval != ERROR_OK)
965 return retval;
966
967 retval = stm32lx_wait_until_bsy_clear(bank);
968 if (retval != ERROR_OK)
969 return retval;
970
971 uint32_t addr = bank->base + bank->sectors[sector].offset + (page
972 * FLASH_PAGE_SIZE);
973 retval = target_write_u32(target, addr, 0x0);
974 if (retval != ERROR_OK)
975 return retval;
976
977 retval = stm32lx_wait_until_bsy_clear(bank);
978 if (retval != ERROR_OK)
979 return retval;
980 }
981
982 retval = stm32lx_lock_program_memory(bank);
983 if (retval != ERROR_OK)
984 return retval;
985
986 return ERROR_OK;
987 }
988
989 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
990 {
991 struct target *target = bank->target;
992 uint32_t status;
993 int retval = ERROR_OK;
994 int timeout = 100;
995
996 /* wait for busy to clear */
997 for (;;) {
998 retval = target_read_u32(target, FLASH_SR, &status);
999 if (retval != ERROR_OK)
1000 return retval;
1001
1002 if ((status & FLASH_SR__BSY) == 0)
1003 break;
1004 if (timeout-- <= 0) {
1005 LOG_ERROR("timed out waiting for flash");
1006 return ERROR_FAIL;
1007 }
1008 alive_sleep(1);
1009 }
1010
1011 if (status & FLASH_SR__WRPERR) {
1012 LOG_ERROR("access denied / write protected");
1013 retval = ERROR_FAIL;
1014 }
1015
1016 if (status & FLASH_SR__PGAERR) {
1017 LOG_ERROR("invalid program address");
1018 retval = ERROR_FAIL;
1019 }
1020
1021 return retval;
1022 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)