ae0ae26ac14f74cbaa386fefb8fc8990d78bde91
[openocd.git] / src / flash / nor / stm32l4x.c
1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
4 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include "imp.h"
24 #include <helper/binarybuffer.h>
25 #include <target/algorithm.h>
26 #include <target/armv7m.h>
27
28 /* STM32L4xxx series for reference.
29 *
30 * RM0351 (STM32L4x5/STM32L4x6)
31 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
32 *
33 * RM0394 (STM32L43x/44x/45x/46x)
34 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
35 *
36 * STM32L476RG Datasheet (for erase timing)
37 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
38 *
39 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
40 * an option byte is available to map all sectors to the first bank.
41 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
42 * handlers do!
43 *
44 * RM0394 devices have a single bank only.
45 *
46 */
47
48 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
49
50 #define FLASH_ERASE_TIMEOUT 250
51
52 #define STM32_FLASH_BASE 0x40022000
53 #define STM32_FLASH_ACR 0x40022000
54 #define STM32_FLASH_KEYR 0x40022008
55 #define STM32_FLASH_OPTKEYR 0x4002200c
56 #define STM32_FLASH_SR 0x40022010
57 #define STM32_FLASH_CR 0x40022014
58 #define STM32_FLASH_OPTR 0x40022020
59 #define STM32_FLASH_WRP1AR 0x4002202c
60 #define STM32_FLASH_WRP1BR 0x40022030
61 #define STM32_FLASH_WRP2AR 0x4002204c
62 #define STM32_FLASH_WRP2BR 0x40022050
63
64 /* FLASH_CR register bits */
65
66 #define FLASH_PG (1 << 0)
67 #define FLASH_PER (1 << 1)
68 #define FLASH_MER1 (1 << 2)
69 #define FLASH_PAGE_SHIFT 3
70 #define FLASH_CR_BKER (1 << 11)
71 #define FLASH_MER2 (1 << 15)
72 #define FLASH_STRT (1 << 16)
73 #define FLASH_OPTSTRT (1 << 17)
74 #define FLASH_EOPIE (1 << 24)
75 #define FLASH_ERRIE (1 << 25)
76 #define FLASH_OBLLAUNCH (1 << 27)
77 #define FLASH_OPTLOCK (1 << 30)
78 #define FLASH_LOCK (1 << 31)
79
80 /* FLASH_SR register bits */
81
82 #define FLASH_BSY (1 << 16)
83 /* Fast programming not used => related errors not used*/
84 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
85 #define FLASH_SIZERR (1 << 6) /* Size error */
86 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
87 #define FLASH_WRPERR (1 << 4) /* Write protection error */
88 #define FLASH_PROGERR (1 << 3) /* Programming error */
89 #define FLASH_OPERR (1 << 1) /* Operation error */
90 #define FLASH_EOP (1 << 0) /* End of operation */
91
92 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
93
94 /* STM32_FLASH_OBR bit definitions (reading) */
95
96 #define OPT_DUALBANK (1 << 21) /* dual flash bank only */
97
98 /* register unlock keys */
99
100 #define KEY1 0x45670123
101 #define KEY2 0xCDEF89AB
102
103 /* option register unlock key */
104 #define OPTKEY1 0x08192A3B
105 #define OPTKEY2 0x4C5D6E7F
106
107 #define RDP_LEVEL_0 0xAA
108 #define RDP_LEVEL_1 0xBB
109 #define RDP_LEVEL_2 0xCC
110
111
112 /* other registers */
113 #define DBGMCU_IDCODE 0xE0042000
114 #define FLASH_SIZE_REG 0x1FFF75E0
115
116 struct stm32l4_flash_bank {
117 uint16_t bank2_start;
118 int probed;
119 };
120
121 /* flash bank stm32l4x <base> <size> 0 0 <target#>
122 */
123 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
124 {
125 struct stm32l4_flash_bank *stm32l4_info;
126
127 if (CMD_ARGC < 6)
128 return ERROR_COMMAND_SYNTAX_ERROR;
129
130 stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
131 if (!stm32l4_info)
132 return ERROR_FAIL; /* Checkme: What better error to use?*/
133 bank->driver_priv = stm32l4_info;
134
135 stm32l4_info->probed = 0;
136
137 return ERROR_OK;
138 }
139
140 static inline int stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg)
141 {
142 return reg;
143 }
144
145 static inline int stm32l4_get_flash_status(struct flash_bank *bank, uint32_t *status)
146 {
147 struct target *target = bank->target;
148 return target_read_u32(
149 target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR), status);
150 }
151
152 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
153 {
154 struct target *target = bank->target;
155 uint32_t status;
156 int retval = ERROR_OK;
157
158 /* wait for busy to clear */
159 for (;;) {
160 retval = stm32l4_get_flash_status(bank, &status);
161 if (retval != ERROR_OK)
162 return retval;
163 LOG_DEBUG("status: 0x%" PRIx32 "", status);
164 if ((status & FLASH_BSY) == 0)
165 break;
166 if (timeout-- <= 0) {
167 LOG_ERROR("timed out waiting for flash");
168 return ERROR_FAIL;
169 }
170 alive_sleep(1);
171 }
172
173
174 if (status & FLASH_WRPERR) {
175 LOG_ERROR("stm32x device protected");
176 retval = ERROR_FAIL;
177 }
178
179 /* Clear but report errors */
180 if (status & FLASH_ERROR) {
181 if (retval == ERROR_OK)
182 retval = ERROR_FAIL;
183 /* If this operation fails, we ignore it and report the original
184 * retval
185 */
186 target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR),
187 status & FLASH_ERROR);
188 }
189 return retval;
190 }
191
192 static int stm32l4_unlock_reg(struct target *target)
193 {
194 uint32_t ctrl;
195
196 /* first check if not already unlocked
197 * otherwise writing on STM32_FLASH_KEYR will fail
198 */
199 int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
200 if (retval != ERROR_OK)
201 return retval;
202
203 if ((ctrl & FLASH_LOCK) == 0)
204 return ERROR_OK;
205
206 /* unlock flash registers */
207 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
208 if (retval != ERROR_OK)
209 return retval;
210
211 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
212 if (retval != ERROR_OK)
213 return retval;
214
215 retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
216 if (retval != ERROR_OK)
217 return retval;
218
219 if (ctrl & FLASH_LOCK) {
220 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
221 return ERROR_TARGET_FAILURE;
222 }
223
224 return ERROR_OK;
225 }
226
227 static int stm32l4_unlock_option_reg(struct target *target)
228 {
229 uint32_t ctrl;
230
231 int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
232 if (retval != ERROR_OK)
233 return retval;
234
235 if ((ctrl & FLASH_OPTLOCK) == 0)
236 return ERROR_OK;
237
238 /* unlock option registers */
239 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY1);
240 if (retval != ERROR_OK)
241 return retval;
242
243 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY2);
244 if (retval != ERROR_OK)
245 return retval;
246
247 retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
248 if (retval != ERROR_OK)
249 return retval;
250
251 if (ctrl & FLASH_OPTLOCK) {
252 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
253 return ERROR_TARGET_FAILURE;
254 }
255
256 return ERROR_OK;
257 }
258
259 static int stm32l4_read_option(struct flash_bank *bank, uint32_t address, uint32_t* value)
260 {
261 struct target *target = bank->target;
262 return target_read_u32(target, address, value);
263 }
264
265 static int stm32l4_write_option(struct flash_bank *bank, uint32_t address, uint32_t value, uint32_t mask)
266 {
267 struct target *target = bank->target;
268 uint32_t optiondata;
269
270 int retval = target_read_u32(target, address, &optiondata);
271 if (retval != ERROR_OK)
272 return retval;
273
274 retval = stm32l4_unlock_reg(target);
275 if (retval != ERROR_OK)
276 return retval;
277
278 retval = stm32l4_unlock_option_reg(target);
279 if (retval != ERROR_OK)
280 return retval;
281
282 optiondata = (optiondata & ~mask) | (value & mask);
283
284 retval = target_write_u32(target, address, optiondata);
285 if (retval != ERROR_OK)
286 return retval;
287
288 retval = target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OPTSTRT);
289 if (retval != ERROR_OK)
290 return retval;
291
292 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
293 if (retval != ERROR_OK)
294 return retval;
295
296 return retval;
297 }
298
299 static int stm32l4_protect_check(struct flash_bank *bank)
300 {
301 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
302 uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
303 stm32l4_read_option(bank, STM32_FLASH_WRP1AR, &wrp1ar);
304 stm32l4_read_option(bank, STM32_FLASH_WRP1BR, &wrp1br);
305 stm32l4_read_option(bank, STM32_FLASH_WRP2AR, &wrp2ar);
306 stm32l4_read_option(bank, STM32_FLASH_WRP2BR, &wrp2br);
307
308 const uint8_t wrp1a_start = wrp1ar & 0xFF;
309 const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
310 const uint8_t wrp1b_start = wrp1br & 0xFF;
311 const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
312 const uint8_t wrp2a_start = wrp2ar & 0xFF;
313 const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
314 const uint8_t wrp2b_start = wrp2br & 0xFF;
315 const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
316
317 for (int i = 0; i < bank->num_sectors; i++) {
318 if (i < stm32l4_info->bank2_start) {
319 if (((i >= wrp1a_start) &&
320 (i <= wrp1a_end)) ||
321 ((i >= wrp1b_start) &&
322 (i <= wrp1b_end)))
323 bank->sectors[i].is_protected = 1;
324 else
325 bank->sectors[i].is_protected = 0;
326 } else {
327 uint8_t snb;
328 snb = i - stm32l4_info->bank2_start + 256;
329 if (((snb >= wrp2a_start) &&
330 (snb <= wrp2a_end)) ||
331 ((snb >= wrp2b_start) &&
332 (snb <= wrp2b_end)))
333 bank->sectors[i].is_protected = 1;
334 else
335 bank->sectors[i].is_protected = 0;
336 }
337 }
338 return ERROR_OK;
339 }
340
341 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
342 {
343 struct target *target = bank->target;
344 int i;
345
346 assert(first < bank->num_sectors);
347 assert(last < bank->num_sectors);
348
349 if (bank->target->state != TARGET_HALTED) {
350 LOG_ERROR("Target not halted");
351 return ERROR_TARGET_NOT_HALTED;
352 }
353
354 int retval;
355 retval = stm32l4_unlock_reg(target);
356 if (retval != ERROR_OK)
357 return retval;
358
359 /*
360 Sector Erase
361 To erase a sector, follow the procedure below:
362 1. Check that no Flash memory operation is ongoing by
363 checking the BSY bit in the FLASH_SR register
364 2. Set the PER bit and select the page and bank
365 you wish to erase in the FLASH_CR register
366 3. Set the STRT bit in the FLASH_CR register
367 4. Wait for the BSY bit to be cleared
368 */
369 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
370
371 for (i = first; i <= last; i++) {
372 uint32_t erase_flags;
373 erase_flags = FLASH_PER | FLASH_STRT;
374
375 if (i >= stm32l4_info->bank2_start) {
376 uint8_t snb;
377 snb = (i - stm32l4_info->bank2_start) + 256;
378 erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
379 } else
380 erase_flags |= i << FLASH_PAGE_SHIFT;
381 retval = target_write_u32(target,
382 stm32l4_get_flash_reg(bank, STM32_FLASH_CR), erase_flags);
383 if (retval != ERROR_OK)
384 return retval;
385
386 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
387 if (retval != ERROR_OK)
388 return retval;
389
390 bank->sectors[i].is_erased = 1;
391 }
392
393 retval = target_write_u32(
394 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
395 if (retval != ERROR_OK)
396 return retval;
397
398 return ERROR_OK;
399 }
400
401 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
402 {
403 struct target *target = bank->target;
404 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
405
406 if (target->state != TARGET_HALTED) {
407 LOG_ERROR("Target not halted");
408 return ERROR_TARGET_NOT_HALTED;
409 }
410
411 int ret = ERROR_OK;
412 /* Bank 2 */
413 uint32_t reg_value = 0xFF; /* Default to bank un-protected */
414 if (last >= stm32l4_info->bank2_start) {
415 if (set == 1) {
416 uint8_t begin = first > stm32l4_info->bank2_start ? first : 0x00;
417 reg_value = ((last & 0xFF) << 16) | begin;
418 }
419
420 ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
421 }
422 /* Bank 1 */
423 reg_value = 0xFF; /* Default to bank un-protected */
424 if (first < stm32l4_info->bank2_start) {
425 if (set == 1) {
426 uint8_t end = last >= stm32l4_info->bank2_start ? 0xFF : last;
427 reg_value = (end << 16) | (first & 0xFF);
428 }
429
430 ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
431 }
432
433 return ret;
434 }
435
436 /* Count is in halfwords */
437 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
438 uint32_t offset, uint32_t count)
439 {
440 struct target *target = bank->target;
441 uint32_t buffer_size = 16384;
442 struct working_area *write_algorithm;
443 struct working_area *source;
444 uint32_t address = bank->base + offset;
445 struct reg_param reg_params[5];
446 struct armv7m_algorithm armv7m_info;
447 int retval = ERROR_OK;
448
449 static const uint8_t stm32l4_flash_write_code[] = {
450 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
451 };
452
453 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
454 &write_algorithm) != ERROR_OK) {
455 LOG_WARNING("no working area available, can't do block memory writes");
456 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
457 }
458
459 retval = target_write_buffer(target, write_algorithm->address,
460 sizeof(stm32l4_flash_write_code),
461 stm32l4_flash_write_code);
462 if (retval != ERROR_OK) {
463 target_free_working_area(target, write_algorithm);
464 return retval;
465 }
466
467 /* memory buffer */
468 while (target_alloc_working_area_try(target, buffer_size, &source) !=
469 ERROR_OK) {
470 buffer_size /= 2;
471 if (buffer_size <= 256) {
472 /* we already allocated the writing code, but failed to get a
473 * buffer, free the algorithm */
474 target_free_working_area(target, write_algorithm);
475
476 LOG_WARNING("no large enough working area available, can't do block memory writes");
477 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
478 }
479 }
480
481 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
482 armv7m_info.core_mode = ARM_MODE_THREAD;
483
484 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
485 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
486 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
487 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
488 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* flash base */
489
490 buf_set_u32(reg_params[0].value, 0, 32, source->address);
491 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
492 buf_set_u32(reg_params[2].value, 0, 32, address);
493 buf_set_u32(reg_params[3].value, 0, 32, count / 4);
494 buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
495
496 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
497 0, NULL,
498 5, reg_params,
499 source->address, source->size,
500 write_algorithm->address, 0,
501 &armv7m_info);
502
503 if (retval == ERROR_FLASH_OPERATION_FAILED) {
504 LOG_ERROR("error executing stm32l4 flash write algorithm");
505
506 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
507
508 if (error & FLASH_WRPERR)
509 LOG_ERROR("flash memory write protected");
510
511 if (error != 0) {
512 LOG_ERROR("flash write failed = %08" PRIx32, error);
513 /* Clear but report errors */
514 target_write_u32(target, STM32_FLASH_SR, error);
515 retval = ERROR_FAIL;
516 }
517 }
518
519 target_free_working_area(target, source);
520 target_free_working_area(target, write_algorithm);
521
522 destroy_reg_param(&reg_params[0]);
523 destroy_reg_param(&reg_params[1]);
524 destroy_reg_param(&reg_params[2]);
525 destroy_reg_param(&reg_params[3]);
526 destroy_reg_param(&reg_params[4]);
527
528 return retval;
529 }
530
531 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
532 uint32_t offset, uint32_t count)
533 {
534 struct target *target = bank->target;
535 int retval;
536
537 if (bank->target->state != TARGET_HALTED) {
538 LOG_ERROR("Target not halted");
539 return ERROR_TARGET_NOT_HALTED;
540 }
541
542 if (offset & 0x7) {
543 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment",
544 offset);
545 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
546 }
547
548 if (count & 0x7) {
549 LOG_WARNING("Padding %d bytes to keep 8-byte write size",
550 count & 7);
551 count = (count + 7) & ~7;
552 /* This pads the write chunk with random bytes by overrunning the
553 * write buffer. Padding with the erased pattern 0xff is purely
554 * cosmetical, as 8-byte flash words are ECC secured and the first
555 * write will program the ECC bits. A second write would need
556 * to reprogramm these ECC bits.
557 * But this can only be done after erase!
558 */
559 }
560
561 retval = stm32l4_unlock_reg(target);
562 if (retval != ERROR_OK)
563 return retval;
564
565 /* Only full double words (8-byte) can be programmed*/
566 retval = stm32l4_write_block(bank, buffer, offset, count / 2);
567 if (retval != ERROR_OK) {
568 LOG_WARNING("block write failed");
569 return retval;
570 }
571
572 LOG_WARNING("block write succeeded");
573 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
574 }
575
576 static int stm32l4_probe(struct flash_bank *bank)
577 {
578 struct target *target = bank->target;
579 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
580 int i;
581 uint16_t flash_size_in_kb = 0xffff;
582 uint16_t max_flash_size_in_kb;
583 uint32_t device_id;
584 uint32_t options;
585 uint32_t base_address = 0x08000000;
586
587 stm32l4_info->probed = 0;
588
589 /* read stm32 device id register */
590 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
591 if (retval != ERROR_OK)
592 return retval;
593 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
594
595 /* set max flash size depending on family */
596 switch (device_id & 0xfff) {
597 case 0x461:
598 case 0x415:
599 max_flash_size_in_kb = 1024;
600 break;
601 case 0x462:
602 max_flash_size_in_kb = 512;
603 break;
604 case 0x435:
605 max_flash_size_in_kb = 256;
606 break;
607 default:
608 LOG_WARNING("Cannot identify target as a STM32L4 family.");
609 return ERROR_FAIL;
610 }
611
612 /* get flash size from target. */
613 retval = target_read_u16(target, FLASH_SIZE_REG, &flash_size_in_kb);
614
615 /* failed reading flash size or flash size invalid (early silicon),
616 * default to max target family */
617 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
618 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
619 max_flash_size_in_kb);
620 flash_size_in_kb = max_flash_size_in_kb;
621 }
622
623 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
624
625 /* did we assign flash size? */
626 assert(flash_size_in_kb != 0xffff);
627
628 /* get options to for DUAL BANK. */
629 retval = target_read_u32(target, STM32_FLASH_OPTR, &options);
630
631 if (retval != ERROR_OK)
632 return retval;
633
634 /* did we assign flash size? */
635 assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
636
637 /* calculate numbers of pages */
638 int num_pages = flash_size_in_kb / 2;
639
640 /* check that calculation result makes sense */
641 assert(num_pages > 0);
642
643 /* only devices with < 1024 kiB may be set to single bank dual banks */
644 if ((flash_size_in_kb == 1024) || !(options & OPT_DUALBANK))
645 stm32l4_info->bank2_start = 256;
646 else
647 stm32l4_info->bank2_start = num_pages / 2;
648
649 if (bank->sectors) {
650 free(bank->sectors);
651 bank->sectors = NULL;
652 }
653
654 bank->base = base_address;
655 bank->size = num_pages * (1 << 11);
656 bank->num_sectors = num_pages;
657 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
658 if (!bank->sectors)
659 return ERROR_FAIL; /* Checkme: What better error to use?*/
660
661 for (i = 0; i < num_pages; i++) {
662 bank->sectors[i].offset = i << 11;
663 bank->sectors[i].size = 1 << 11;
664 bank->sectors[i].is_erased = -1;
665 bank->sectors[i].is_protected = 1;
666 }
667
668 stm32l4_info->probed = 1;
669
670 return ERROR_OK;
671 }
672
673 static int stm32l4_auto_probe(struct flash_bank *bank)
674 {
675 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
676 if (stm32l4_info->probed)
677 return ERROR_OK;
678 return stm32l4_probe(bank);
679 }
680
681 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
682 {
683 struct target *target = bank->target;
684 uint32_t dbgmcu_idcode;
685
686 /* read stm32 device id register */
687 int retval = target_read_u32(target, DBGMCU_IDCODE, &dbgmcu_idcode);
688 if (retval != ERROR_OK)
689 return retval;
690
691 uint16_t device_id = dbgmcu_idcode & 0xfff;
692 uint8_t rev_id = dbgmcu_idcode >> 28;
693 uint8_t rev_minor = 0;
694 int i;
695
696 for (i = 16; i < 28; i++) {
697 if (dbgmcu_idcode & (1 << i))
698 rev_minor++;
699 else
700 break;
701 }
702
703 const char *device_str;
704
705 switch (device_id) {
706 case 0x461:
707 device_str = "STM32L496/4A6";
708 break;
709
710 case 0x415:
711 device_str = "STM32L475/476/486";
712 break;
713
714 case 0x462:
715 device_str = "STM32L45x/46x";
716 break;
717
718 case 0x435:
719 device_str = "STM32L43x/44x";
720 break;
721
722 default:
723 snprintf(buf, buf_size, "Cannot identify target as a STM32L4\n");
724 return ERROR_FAIL;
725 }
726
727 snprintf(buf, buf_size, "%s - Rev: %1d.%02d",
728 device_str, rev_id, rev_minor);
729
730 return ERROR_OK;
731 }
732
733 static int stm32l4_mass_erase(struct flash_bank *bank, uint32_t action)
734 {
735 int retval;
736 struct target *target = bank->target;
737
738 if (target->state != TARGET_HALTED) {
739 LOG_ERROR("Target not halted");
740 return ERROR_TARGET_NOT_HALTED;
741 }
742
743 retval = stm32l4_unlock_reg(target);
744 if (retval != ERROR_OK)
745 return retval;
746
747 /* mass erase flash memory */
748 retval = target_write_u32(
749 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), action);
750 if (retval != ERROR_OK)
751 return retval;
752 retval = target_write_u32(
753 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR),
754 action | FLASH_STRT);
755 if (retval != ERROR_OK)
756 return retval;
757
758 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
759 if (retval != ERROR_OK)
760 return retval;
761
762 retval = target_write_u32(
763 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
764 if (retval != ERROR_OK)
765 return retval;
766
767 return ERROR_OK;
768 }
769
770 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
771 {
772 int i;
773 uint32_t action;
774
775 if (CMD_ARGC < 1) {
776 command_print(CMD_CTX, "stm32l4x mass_erase <STM32L4 bank>");
777 return ERROR_COMMAND_SYNTAX_ERROR;
778 }
779
780 struct flash_bank *bank;
781 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
782 if (ERROR_OK != retval)
783 return retval;
784
785 action = FLASH_MER1 | FLASH_MER2;
786 retval = stm32l4_mass_erase(bank, action);
787 if (retval == ERROR_OK) {
788 /* set all sectors as erased */
789 for (i = 0; i < bank->num_sectors; i++)
790 bank->sectors[i].is_erased = 1;
791
792 command_print(CMD_CTX, "stm32l4x mass erase complete");
793 } else {
794 command_print(CMD_CTX, "stm32l4x mass erase failed");
795 }
796
797 return retval;
798 }
799
800 COMMAND_HANDLER(stm32l4_handle_option_read_command)
801 {
802 if (CMD_ARGC < 2) {
803 command_print(CMD_CTX, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
804 return ERROR_COMMAND_SYNTAX_ERROR;
805 }
806
807 struct flash_bank *bank;
808 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
809 if (ERROR_OK != retval)
810 return retval;
811
812 uint32_t reg_addr = STM32_FLASH_BASE;
813 uint32_t value = 0;
814
815 reg_addr += strtoul(CMD_ARGV[1], NULL, 16);
816
817 retval = stm32l4_read_option(bank, reg_addr, &value);
818 if (ERROR_OK != retval)
819 return retval;
820
821 command_print(CMD_CTX, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
822
823 return retval;
824 }
825
826 COMMAND_HANDLER(stm32l4_handle_option_write_command)
827 {
828 if (CMD_ARGC < 3) {
829 command_print(CMD_CTX, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
830 return ERROR_COMMAND_SYNTAX_ERROR;
831 }
832
833 struct flash_bank *bank;
834 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
835 if (ERROR_OK != retval)
836 return retval;
837
838 uint32_t reg_addr = STM32_FLASH_BASE;
839 uint32_t value = 0;
840 uint32_t mask = 0xFFFFFFFF;
841
842 reg_addr += strtoul(CMD_ARGV[1], NULL, 16);
843 value = strtoul(CMD_ARGV[2], NULL, 16);
844 if (CMD_ARGC > 3)
845 mask = strtoul(CMD_ARGV[3], NULL, 16);
846
847 command_print(CMD_CTX, "%s Option written.\n"
848 "INFO: a reset or power cycle is required "
849 "for the new settings to take effect.", bank->driver->name);
850
851 retval = stm32l4_write_option(bank, reg_addr, value, mask);
852 return retval;
853 }
854
855 COMMAND_HANDLER(stm32l4_handle_option_load_command)
856 {
857 if (CMD_ARGC < 1)
858 return ERROR_COMMAND_SYNTAX_ERROR;
859
860 struct flash_bank *bank;
861 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
862 if (ERROR_OK != retval)
863 return retval;
864
865 struct target *target = bank->target;
866
867 retval = stm32l4_unlock_reg(target);
868 if (ERROR_OK != retval)
869 return retval;
870
871 retval = stm32l4_unlock_option_reg(target);
872 if (ERROR_OK != retval)
873 return retval;
874
875 /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
876 retval = target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBLLAUNCH);
877
878 command_print(CMD_CTX, "stm32l4x option load (POR) completed.");
879 return retval;
880 }
881
882 COMMAND_HANDLER(stm32l4_handle_lock_command)
883 {
884 struct target *target = NULL;
885
886 if (CMD_ARGC < 1)
887 return ERROR_COMMAND_SYNTAX_ERROR;
888
889 struct flash_bank *bank;
890 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
891 if (ERROR_OK != retval)
892 return retval;
893
894 target = bank->target;
895
896 if (target->state != TARGET_HALTED) {
897 LOG_ERROR("Target not halted");
898 return ERROR_TARGET_NOT_HALTED;
899 }
900
901 /* set readout protection level 1 by erasing the RDP option byte */
902 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
903 command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
904 return ERROR_OK;
905 }
906
907 return ERROR_OK;
908 }
909
910 COMMAND_HANDLER(stm32l4_handle_unlock_command)
911 {
912 struct target *target = NULL;
913
914 if (CMD_ARGC < 1)
915 return ERROR_COMMAND_SYNTAX_ERROR;
916
917 struct flash_bank *bank;
918 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
919 if (ERROR_OK != retval)
920 return retval;
921
922 target = bank->target;
923
924 if (target->state != TARGET_HALTED) {
925 LOG_ERROR("Target not halted");
926 return ERROR_TARGET_NOT_HALTED;
927 }
928
929 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
930 command_print(CMD_CTX, "%s failed to unlock device", bank->driver->name);
931 return ERROR_OK;
932 }
933
934 return ERROR_OK;
935 }
936
937 static const struct command_registration stm32l4_exec_command_handlers[] = {
938 {
939 .name = "lock",
940 .handler = stm32l4_handle_lock_command,
941 .mode = COMMAND_EXEC,
942 .usage = "bank_id",
943 .help = "Lock entire flash device.",
944 },
945 {
946 .name = "unlock",
947 .handler = stm32l4_handle_unlock_command,
948 .mode = COMMAND_EXEC,
949 .usage = "bank_id",
950 .help = "Unlock entire protected flash device.",
951 },
952 {
953 .name = "mass_erase",
954 .handler = stm32l4_handle_mass_erase_command,
955 .mode = COMMAND_EXEC,
956 .usage = "bank_id",
957 .help = "Erase entire flash device.",
958 },
959 {
960 .name = "option_read",
961 .handler = stm32l4_handle_option_read_command,
962 .mode = COMMAND_EXEC,
963 .usage = "bank_id reg_offset",
964 .help = "Read & Display device option bytes.",
965 },
966 {
967 .name = "option_write",
968 .handler = stm32l4_handle_option_write_command,
969 .mode = COMMAND_EXEC,
970 .usage = "bank_id reg_offset value mask",
971 .help = "Write device option bit fields with provided value.",
972 },
973 {
974 .name = "option_load",
975 .handler = stm32l4_handle_option_load_command,
976 .mode = COMMAND_EXEC,
977 .usage = "bank_id",
978 .help = "Force re-load of device options (will cause device reset).",
979 },
980 COMMAND_REGISTRATION_DONE
981 };
982
983 static const struct command_registration stm32l4_command_handlers[] = {
984 {
985 .name = "stm32l4x",
986 .mode = COMMAND_ANY,
987 .help = "stm32l4x flash command group",
988 .usage = "",
989 .chain = stm32l4_exec_command_handlers,
990 },
991 COMMAND_REGISTRATION_DONE
992 };
993
994 struct flash_driver stm32l4x_flash = {
995 .name = "stm32l4x",
996 .commands = stm32l4_command_handlers,
997 .flash_bank_command = stm32l4_flash_bank_command,
998 .erase = stm32l4_erase,
999 .protect = stm32l4_protect,
1000 .write = stm32l4_write,
1001 .read = default_flash_read,
1002 .probe = stm32l4_probe,
1003 .auto_probe = stm32l4_auto_probe,
1004 .erase_check = default_flash_blank_check,
1005 .protect_check = stm32l4_protect_check,
1006 .info = get_stm32l4_info,
1007 .free_driver_priv = default_flash_free_driver_priv,
1008 };