Code Review / openocd.git / blob
? search:


a373f1168690ee08981fe502bd3c238cc6130928
[openocd.git] / src / flash / nor / stm32l4x.c
1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
4 * *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "imp.h"
27 #include <helper/binarybuffer.h>
28 #include <target/algorithm.h>
29 #include <target/armv7m.h>
30 #include "bits.h"
31
32 /* STM32L4xxx series for reference.
33 *
34 * RM0351 (STM32L4x5/STM32L4x6)
35 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
36 *
37 * RM0394 (STM32L43x/44x/45x/46x)
38 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
39 *
40 * RM0432 (STM32L4R/4Sxx)
41 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
42 *
43 * STM32L476RG Datasheet (for erase timing)
44 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
45 *
46 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
47 * an option byte is available to map all sectors to the first bank.
48 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
49 * handlers do!
50 *
51 * RM0394 devices have a single bank only.
52 *
53 * RM0432 devices have single and dual bank operating modes.
54 * The FLASH size is 1Mbyte or 2Mbyte.
55 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
56 *
57 * Bank mode is controlled by two different bits in option bytes register.
58 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
59 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
60 *
61 */
62
63 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
64
65 #define FLASH_ERASE_TIMEOUT 250
66
67 /* Flash registers offsets */
68 #define STM32_FLASH_ACR 0x00
69 #define STM32_FLASH_KEYR 0x08
70 #define STM32_FLASH_OPTKEYR 0x0c
71 #define STM32_FLASH_SR 0x10
72 #define STM32_FLASH_CR 0x14
73 #define STM32_FLASH_OPTR 0x20
74 #define STM32_FLASH_WRP1AR 0x2c
75 #define STM32_FLASH_WRP1BR 0x30
76 #define STM32_FLASH_WRP2AR 0x4c
77 #define STM32_FLASH_WRP2BR 0x50
78
79 /* FLASH_CR register bits */
80 #define FLASH_PG (1 << 0)
81 #define FLASH_PER (1 << 1)
82 #define FLASH_MER1 (1 << 2)
83 #define FLASH_PAGE_SHIFT 3
84 #define FLASH_CR_BKER (1 << 11)
85 #define FLASH_MER2 (1 << 15)
86 #define FLASH_STRT (1 << 16)
87 #define FLASH_OPTSTRT (1 << 17)
88 #define FLASH_EOPIE (1 << 24)
89 #define FLASH_ERRIE (1 << 25)
90 #define FLASH_OBLLAUNCH (1 << 27)
91 #define FLASH_OPTLOCK (1 << 30)
92 #define FLASH_LOCK (1 << 31)
93
94 /* FLASH_SR register bits */
95 #define FLASH_BSY (1 << 16)
96 /* Fast programming not used => related errors not used*/
97 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
98 #define FLASH_SIZERR (1 << 6) /* Size error */
99 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
100 #define FLASH_WRPERR (1 << 4) /* Write protection error */
101 #define FLASH_PROGERR (1 << 3) /* Programming error */
102 #define FLASH_OPERR (1 << 1) /* Operation error */
103 #define FLASH_EOP (1 << 0) /* End of operation */
104 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
105
106 /* register unlock keys */
107 #define KEY1 0x45670123
108 #define KEY2 0xCDEF89AB
109
110 /* option register unlock key */
111 #define OPTKEY1 0x08192A3B
112 #define OPTKEY2 0x4C5D6E7F
113
114 #define RDP_LEVEL_0 0xAA
115 #define RDP_LEVEL_1 0xBB
116 #define RDP_LEVEL_2 0xCC
117
118
119 /* other registers */
120 #define DBGMCU_IDCODE 0xE0042000
121
122
123 struct stm32l4_rev {
124 const uint16_t rev;
125 const char *str;
126 };
127
128 struct stm32l4_part_info {
129 uint16_t id;
130 const char *device_str;
131 const struct stm32l4_rev *revs;
132 const size_t num_revs;
133 const uint16_t max_flash_size_kb;
134 const bool has_dual_bank;
135 const uint32_t flash_regs_base;
136 const uint32_t fsize_addr;
137 };
138
139 struct stm32l4_flash_bank {
140 int probed;
141 uint32_t idcode;
142 int bank1_sectors;
143 bool dual_bank_mode;
144 int hole_sectors;
145 const struct stm32l4_part_info *part_info;
146 };
147
148 static const struct stm32l4_rev stm32_415_revs[] = {
149 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
150 };
151
152 static const struct stm32l4_rev stm32_435_revs[] = {
153 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
154 };
155
156 static const struct stm32l4_rev stm32_461_revs[] = {
157 { 0x1000, "A" }, { 0x2000, "B" },
158 };
159
160 static const struct stm32l4_rev stm32_462_revs[] = {
161 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
162 };
163
164 static const struct stm32l4_rev stm32_464_revs[] = {
165 { 0x1000, "A" },
166 };
167
168 static const struct stm32l4_rev stm32_470_revs[] = {
169 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
170 };
171
172 static const struct stm32l4_rev stm32_495_revs[] = {
173 { 0x2001, "2.1" },
174 };
175
176 static const struct stm32l4_part_info stm32l4_parts[] = {
177 {
178 .id = 0x415,
179 .revs = stm32_415_revs,
180 .num_revs = ARRAY_SIZE(stm32_415_revs),
181 .device_str = "STM32L47/L48xx",
182 .max_flash_size_kb = 1024,
183 .has_dual_bank = true,
184 .flash_regs_base = 0x40022000,
185 .fsize_addr = 0x1FFF75E0,
186 },
187 {
188 .id = 0x435,
189 .revs = stm32_435_revs,
190 .num_revs = ARRAY_SIZE(stm32_435_revs),
191 .device_str = "STM32L43/L44xx",
192 .max_flash_size_kb = 256,
193 .has_dual_bank = false,
194 .flash_regs_base = 0x40022000,
195 .fsize_addr = 0x1FFF75E0,
196 },
197 {
198 .id = 0x461,
199 .revs = stm32_461_revs,
200 .num_revs = ARRAY_SIZE(stm32_461_revs),
201 .device_str = "STM32L49/L4Axx",
202 .max_flash_size_kb = 1024,
203 .has_dual_bank = true,
204 .flash_regs_base = 0x40022000,
205 .fsize_addr = 0x1FFF75E0,
206 },
207 {
208 .id = 0x462,
209 .revs = stm32_462_revs,
210 .num_revs = ARRAY_SIZE(stm32_462_revs),
211 .device_str = "STM32L45/L46xx",
212 .max_flash_size_kb = 512,
213 .has_dual_bank = false,
214 .flash_regs_base = 0x40022000,
215 .fsize_addr = 0x1FFF75E0,
216 },
217 {
218 .id = 0x464,
219 .revs = stm32_464_revs,
220 .num_revs = ARRAY_SIZE(stm32_464_revs),
221 .device_str = "STM32L41/L42xx",
222 .max_flash_size_kb = 128,
223 .has_dual_bank = false,
224 .flash_regs_base = 0x40022000,
225 .fsize_addr = 0x1FFF75E0,
226 },
227 {
228 .id = 0x470,
229 .revs = stm32_470_revs,
230 .num_revs = ARRAY_SIZE(stm32_470_revs),
231 .device_str = "STM32L4R/L4Sxx",
232 .max_flash_size_kb = 2048,
233 .has_dual_bank = true,
234 .flash_regs_base = 0x40022000,
235 .fsize_addr = 0x1FFF75E0,
236 },
237 {
238 .id = 0x495,
239 .revs = stm32_495_revs,
240 .num_revs = ARRAY_SIZE(stm32_495_revs),
241 .device_str = "STM32WB5x",
242 .max_flash_size_kb = 1024,
243 .has_dual_bank = false,
244 .flash_regs_base = 0x58004000,
245 .fsize_addr = 0x1FFF75E0,
246 },
247 };
248
249 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
250 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
251 {
252 struct stm32l4_flash_bank *stm32l4_info;
253
254 if (CMD_ARGC < 6)
255 return ERROR_COMMAND_SYNTAX_ERROR;
256
257 stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
258 if (!stm32l4_info)
259 return ERROR_FAIL; /* Checkme: What better error to use?*/
260 bank->driver_priv = stm32l4_info;
261
262 stm32l4_info->probed = 0;
263
264 return ERROR_OK;
265 }
266
267 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
268 {
269 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
270 return stm32l4_info->part_info->flash_regs_base + reg_offset;
271 }
272
273 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
274 {
275 return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
276 }
277
278 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
279 {
280 return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
281 }
282
283 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
284 {
285 uint32_t status;
286 int retval = ERROR_OK;
287
288 /* wait for busy to clear */
289 for (;;) {
290 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_SR, &status);
291 if (retval != ERROR_OK)
292 return retval;
293 LOG_DEBUG("status: 0x%" PRIx32 "", status);
294 if ((status & FLASH_BSY) == 0)
295 break;
296 if (timeout-- <= 0) {
297 LOG_ERROR("timed out waiting for flash");
298 return ERROR_FAIL;
299 }
300 alive_sleep(1);
301 }
302
303
304 if (status & FLASH_WRPERR) {
305 LOG_ERROR("stm32x device protected");
306 retval = ERROR_FAIL;
307 }
308
309 /* Clear but report errors */
310 if (status & FLASH_ERROR) {
311 if (retval == ERROR_OK)
312 retval = ERROR_FAIL;
313 /* If this operation fails, we ignore it and report the original
314 * retval
315 */
316 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, status & FLASH_ERROR);
317 }
318
319 return retval;
320 }
321
322 static int stm32l4_unlock_reg(struct flash_bank *bank)
323 {
324 uint32_t ctrl;
325
326 /* first check if not already unlocked
327 * otherwise writing on STM32_FLASH_KEYR will fail
328 */
329 int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
330 if (retval != ERROR_OK)
331 return retval;
332
333 if ((ctrl & FLASH_LOCK) == 0)
334 return ERROR_OK;
335
336 /* unlock flash registers */
337 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY1);
338 if (retval != ERROR_OK)
339 return retval;
340
341 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY2);
342 if (retval != ERROR_OK)
343 return retval;
344
345 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
346 if (retval != ERROR_OK)
347 return retval;
348
349 if (ctrl & FLASH_LOCK) {
350 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
351 return ERROR_TARGET_FAILURE;
352 }
353
354 return ERROR_OK;
355 }
356
357 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
358 {
359 uint32_t ctrl;
360
361 int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
362 if (retval != ERROR_OK)
363 return retval;
364
365 if ((ctrl & FLASH_OPTLOCK) == 0)
366 return ERROR_OK;
367
368 /* unlock option registers */
369 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY1);
370 if (retval != ERROR_OK)
371 return retval;
372
373 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY2);
374 if (retval != ERROR_OK)
375 return retval;
376
377 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
378 if (retval != ERROR_OK)
379 return retval;
380
381 if (ctrl & FLASH_OPTLOCK) {
382 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
383 return ERROR_TARGET_FAILURE;
384 }
385
386 return ERROR_OK;
387 }
388
389 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
390 {
391 uint32_t optiondata;
392
393 int retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
394 if (retval != ERROR_OK)
395 return retval;
396
397 retval = stm32l4_unlock_reg(bank);
398 if (retval != ERROR_OK)
399 return retval;
400
401 retval = stm32l4_unlock_option_reg(bank);
402 if (retval != ERROR_OK)
403 return retval;
404
405 optiondata = (optiondata & ~mask) | (value & mask);
406
407 retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
408 if (retval != ERROR_OK)
409 return retval;
410
411 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OPTSTRT);
412 if (retval != ERROR_OK)
413 return retval;
414
415 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
416 if (retval != ERROR_OK)
417 return retval;
418
419 return retval;
420 }
421
422 static int stm32l4_protect_check(struct flash_bank *bank)
423 {
424 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
425
426 uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
427 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar);
428 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br);
429 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
430 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
431
432 const uint8_t wrp1a_start = wrp1ar & 0xFF;
433 const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
434 const uint8_t wrp1b_start = wrp1br & 0xFF;
435 const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
436 const uint8_t wrp2a_start = wrp2ar & 0xFF;
437 const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
438 const uint8_t wrp2b_start = wrp2br & 0xFF;
439 const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
440
441 for (int i = 0; i < bank->num_sectors; i++) {
442 if (i < stm32l4_info->bank1_sectors) {
443 if (((i >= wrp1a_start) &&
444 (i <= wrp1a_end)) ||
445 ((i >= wrp1b_start) &&
446 (i <= wrp1b_end)))
447 bank->sectors[i].is_protected = 1;
448 else
449 bank->sectors[i].is_protected = 0;
450 } else {
451 uint8_t snb;
452 snb = i - stm32l4_info->bank1_sectors;
453 if (((snb >= wrp2a_start) &&
454 (snb <= wrp2a_end)) ||
455 ((snb >= wrp2b_start) &&
456 (snb <= wrp2b_end)))
457 bank->sectors[i].is_protected = 1;
458 else
459 bank->sectors[i].is_protected = 0;
460 }
461 }
462 return ERROR_OK;
463 }
464
465 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
466 {
467 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
468 int i;
469 int retval;
470
471 assert(first < bank->num_sectors);
472 assert(last < bank->num_sectors);
473
474 if (bank->target->state != TARGET_HALTED) {
475 LOG_ERROR("Target not halted");
476 return ERROR_TARGET_NOT_HALTED;
477 }
478
479 retval = stm32l4_unlock_reg(bank);
480 if (retval != ERROR_OK)
481 return retval;
482
483 /*
484 Sector Erase
485 To erase a sector, follow the procedure below:
486 1. Check that no Flash memory operation is ongoing by
487 checking the BSY bit in the FLASH_SR register
488 2. Set the PER bit and select the page and bank
489 you wish to erase in the FLASH_CR register
490 3. Set the STRT bit in the FLASH_CR register
491 4. Wait for the BSY bit to be cleared
492 */
493
494 for (i = first; i <= last; i++) {
495 uint32_t erase_flags;
496 erase_flags = FLASH_PER | FLASH_STRT;
497
498 if (i >= stm32l4_info->bank1_sectors) {
499 uint8_t snb;
500 snb = i - stm32l4_info->bank1_sectors;
501 erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
502 } else
503 erase_flags |= i << FLASH_PAGE_SHIFT;
504 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, erase_flags);
505 if (retval != ERROR_OK)
506 return retval;
507
508 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
509 if (retval != ERROR_OK)
510 return retval;
511
512 bank->sectors[i].is_erased = 1;
513 }
514
515 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
516 if (retval != ERROR_OK)
517 return retval;
518
519 return ERROR_OK;
520 }
521
522 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
523 {
524 struct target *target = bank->target;
525 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
526
527 if (target->state != TARGET_HALTED) {
528 LOG_ERROR("Target not halted");
529 return ERROR_TARGET_NOT_HALTED;
530 }
531
532 int ret = ERROR_OK;
533 /* Bank 2 */
534 uint32_t reg_value = 0xFF; /* Default to bank un-protected */
535 if (last >= stm32l4_info->bank1_sectors) {
536 if (set == 1) {
537 uint8_t begin = first > stm32l4_info->bank1_sectors ? first : 0x00;
538 reg_value = ((last & 0xFF) << 16) | begin;
539 }
540
541 ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
542 }
543 /* Bank 1 */
544 reg_value = 0xFF; /* Default to bank un-protected */
545 if (first < stm32l4_info->bank1_sectors) {
546 if (set == 1) {
547 uint8_t end = last >= stm32l4_info->bank1_sectors ? 0xFF : last;
548 reg_value = (end << 16) | (first & 0xFF);
549 }
550
551 ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
552 }
553
554 return ret;
555 }
556
557 /* Count is in halfwords */
558 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
559 uint32_t offset, uint32_t count)
560 {
561 struct target *target = bank->target;
562 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
563 uint32_t buffer_size = 16384;
564 struct working_area *write_algorithm;
565 struct working_area *source;
566 uint32_t address = bank->base + offset;
567 struct reg_param reg_params[5];
568 struct armv7m_algorithm armv7m_info;
569 int retval = ERROR_OK;
570
571 static const uint8_t stm32l4_flash_write_code[] = {
572 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
573 };
574
575 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
576 &write_algorithm) != ERROR_OK) {
577 LOG_WARNING("no working area available, can't do block memory writes");
578 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
579 }
580
581 retval = target_write_buffer(target, write_algorithm->address,
582 sizeof(stm32l4_flash_write_code),
583 stm32l4_flash_write_code);
584 if (retval != ERROR_OK) {
585 target_free_working_area(target, write_algorithm);
586 return retval;
587 }
588
589 /* memory buffer */
590 while (target_alloc_working_area_try(target, buffer_size, &source) !=
591 ERROR_OK) {
592 buffer_size /= 2;
593 if (buffer_size <= 256) {
594 /* we already allocated the writing code, but failed to get a
595 * buffer, free the algorithm */
596 target_free_working_area(target, write_algorithm);
597
598 LOG_WARNING("large enough working area not available, can't do block memory writes");
599 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
600 }
601 }
602
603 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
604 armv7m_info.core_mode = ARM_MODE_THREAD;
605
606 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
607 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
608 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
609 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
610 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* flash base */
611
612 buf_set_u32(reg_params[0].value, 0, 32, source->address);
613 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
614 buf_set_u32(reg_params[2].value, 0, 32, address);
615 buf_set_u32(reg_params[3].value, 0, 32, count / 4);
616 buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base);
617
618 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
619 0, NULL,
620 5, reg_params,
621 source->address, source->size,
622 write_algorithm->address, 0,
623 &armv7m_info);
624
625 if (retval == ERROR_FLASH_OPERATION_FAILED) {
626 LOG_ERROR("error executing stm32l4 flash write algorithm");
627
628 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
629
630 if (error & FLASH_WRPERR)
631 LOG_ERROR("flash memory write protected");
632
633 if (error != 0) {
634 LOG_ERROR("flash write failed = %08" PRIx32, error);
635 /* Clear but report errors */
636 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, error);
637 retval = ERROR_FAIL;
638 }
639 }
640
641 target_free_working_area(target, source);
642 target_free_working_area(target, write_algorithm);
643
644 destroy_reg_param(&reg_params[0]);
645 destroy_reg_param(&reg_params[1]);
646 destroy_reg_param(&reg_params[2]);
647 destroy_reg_param(&reg_params[3]);
648 destroy_reg_param(&reg_params[4]);
649
650 return retval;
651 }
652
653 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
654 uint32_t offset, uint32_t count)
655 {
656 int retval;
657
658 if (bank->target->state != TARGET_HALTED) {
659 LOG_ERROR("Target not halted");
660 return ERROR_TARGET_NOT_HALTED;
661 }
662
663 if (offset & 0x7) {
664 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment",
665 offset);
666 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
667 }
668
669 if (count & 0x7) {
670 LOG_WARNING("Padding %d bytes to keep 8-byte write size",
671 count & 7);
672 count = (count + 7) & ~7;
673 /* This pads the write chunk with random bytes by overrunning the
674 * write buffer. Padding with the erased pattern 0xff is purely
675 * cosmetical, as 8-byte flash words are ECC secured and the first
676 * write will program the ECC bits. A second write would need
677 * to reprogramm these ECC bits.
678 * But this can only be done after erase!
679 */
680 }
681
682 retval = stm32l4_unlock_reg(bank);
683 if (retval != ERROR_OK)
684 return retval;
685
686 /* Only full double words (8-byte) can be programmed*/
687 retval = stm32l4_write_block(bank, buffer, offset, count / 2);
688 if (retval != ERROR_OK) {
689 LOG_WARNING("block write failed");
690 return retval;
691 }
692
693 LOG_WARNING("block write succeeded");
694 return stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
695 }
696
697 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
698 {
699 int retval = target_read_u32(bank->target, DBGMCU_IDCODE, id);
700 if (retval != ERROR_OK)
701 return retval;
702
703 return retval;
704 }
705
706 static int stm32l4_probe(struct flash_bank *bank)
707 {
708 struct target *target = bank->target;
709 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
710 const struct stm32l4_part_info *part_info;
711 int i;
712 uint16_t flash_size_in_kb = 0xffff;
713 uint32_t device_id;
714 uint32_t options;
715
716 stm32l4_info->probed = 0;
717
718 /* read stm32 device id register */
719 int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
720 if (retval != ERROR_OK)
721 return retval;
722
723 device_id = stm32l4_info->idcode & 0xFFF;
724
725 for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
726 if (device_id == stm32l4_parts[n].id)
727 stm32l4_info->part_info = &stm32l4_parts[n];
728 }
729
730 if (!stm32l4_info->part_info) {
731 LOG_WARNING("Cannot identify target as an STM32 L4 or WB family device.");
732 return ERROR_FAIL;
733 }
734
735 part_info = stm32l4_info->part_info;
736
737 char device_info[1024];
738 retval = bank->driver->info(bank, device_info, sizeof(device_info));
739 if (retval != ERROR_OK)
740 return retval;
741
742 LOG_INFO("device idcode = 0x%08" PRIx32 " (%s)", stm32l4_info->idcode, device_info);
743
744 /* get flash size from target. */
745 retval = target_read_u16(target, part_info->fsize_addr, &flash_size_in_kb);
746
747 /* failed reading flash size or flash size invalid (early silicon),
748 * default to max target family */
749 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0
750 || flash_size_in_kb > part_info->max_flash_size_kb) {
751 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
752 part_info->max_flash_size_kb);
753 flash_size_in_kb = part_info->max_flash_size_kb;
754 }
755
756 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
757
758 /* did we assign a flash size? */
759 assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
760
761 /* read flash option register */
762 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options);
763 if (retval != ERROR_OK)
764 return retval;
765
766 stm32l4_info->bank1_sectors = 0;
767 stm32l4_info->hole_sectors = 0;
768
769 int num_pages = 0;
770 int page_size = 0;
771
772 stm32l4_info->dual_bank_mode = false;
773
774 switch (device_id) {
775 case 0x415:
776 case 0x461:
777 /* if flash size is max (1M) the device is always dual bank
778 * 0x415: has variants with 512K
779 * 0x461: has variants with 512 and 256
780 * for these variants:
781 * if DUAL_BANK = 0 -> single bank
782 * else -> dual bank without gap
783 * note: the page size is invariant
784 */
785 page_size = 2048;
786 num_pages = flash_size_in_kb / 2;
787 stm32l4_info->bank1_sectors = num_pages;
788
789 /* check DUAL_BANK bit[21] if the flash is less than 1M */
790 if (flash_size_in_kb == 1024 || (options & BIT(21))) {
791 stm32l4_info->dual_bank_mode = true;
792 stm32l4_info->bank1_sectors = num_pages / 2;
793 }
794 break;
795 case 0x435:
796 case 0x462:
797 case 0x464:
798 /* single bank flash */
799 page_size = 2048;
800 num_pages = flash_size_in_kb / 2;
801 stm32l4_info->bank1_sectors = num_pages;
802 break;
803 case 0x470:
804 /* STM32L4R/S can be single/dual bank:
805 * if size = 2M check DBANK bit(22)
806 * if size = 1M check DB1M bit(21)
807 * in single bank configuration the page size is 8K
808 * else (dual bank) the page size is 4K without gap between banks
809 */
810 page_size = 8192;
811 num_pages = flash_size_in_kb / 8;
812 stm32l4_info->bank1_sectors = num_pages;
813 if ((flash_size_in_kb == 2048 && (options & BIT(22))) ||
814 (flash_size_in_kb == 1024 && (options & BIT(21)))) {
815 stm32l4_info->dual_bank_mode = true;
816 page_size = 4096;
817 num_pages = flash_size_in_kb / 4;
818 stm32l4_info->bank1_sectors = num_pages / 2;
819 }
820 break;
821 case 0x495:
822 /* single bank flash */
823 page_size = 4096;
824 num_pages = flash_size_in_kb / 4;
825 stm32l4_info->bank1_sectors = num_pages;
826 break;
827 default:
828 LOG_ERROR("unsupported device");
829 return ERROR_FAIL;
830 }
831
832 LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
833
834 const int gap_size = stm32l4_info->hole_sectors * page_size;
835
836 if (stm32l4_info->dual_bank_mode & gap_size) {
837 LOG_INFO("gap detected starting from %0x08" PRIx32 " to %0x08" PRIx32,
838 0x8000000 + stm32l4_info->bank1_sectors * page_size,
839 0x8000000 + stm32l4_info->bank1_sectors * page_size + gap_size);
840 }
841
842 if (bank->sectors) {
843 free(bank->sectors);
844 bank->sectors = NULL;
845 }
846
847 bank->size = flash_size_in_kb * 1024 + gap_size;
848 bank->base = 0x08000000;
849 bank->num_sectors = num_pages;
850 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
851 if (bank->sectors == NULL) {
852 LOG_ERROR("failed to allocate bank sectors");
853 return ERROR_FAIL;
854 }
855
856 for (i = 0; i < bank->num_sectors; i++) {
857 bank->sectors[i].offset = i * page_size;
858 /* in dual bank configuration, if there is a gap between banks
859 * we fix up the sector offset to consider this gap */
860 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
861 bank->sectors[i].offset += gap_size;
862 bank->sectors[i].size = page_size;
863 bank->sectors[i].is_erased = -1;
864 bank->sectors[i].is_protected = 1;
865 }
866
867 stm32l4_info->probed = 1;
868 return ERROR_OK;
869 }
870
871 static int stm32l4_auto_probe(struct flash_bank *bank)
872 {
873 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
874 if (stm32l4_info->probed)
875 return ERROR_OK;
876
877 return stm32l4_probe(bank);
878 }
879
880 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
881 {
882 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
883 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
884
885 if (part_info) {
886 const char *rev_str = NULL;
887 uint16_t rev_id = stm32l4_info->idcode >> 16;
888 for (unsigned int i = 0; i < part_info->num_revs; i++) {
889 if (rev_id == part_info->revs[i].rev) {
890 rev_str = part_info->revs[i].str;
891
892 if (rev_str != NULL) {
893 snprintf(buf, buf_size, "%s - Rev: %s",
894 part_info->device_str, rev_str);
895 return ERROR_OK;
896 }
897 }
898 }
899
900 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)",
901 part_info->device_str, rev_id);
902 return ERROR_OK;
903 } else {
904 snprintf(buf, buf_size, "Cannot identify target as an STM32 L4 or WB device");
905 return ERROR_FAIL;
906 }
907
908 return ERROR_OK;
909 }
910
911 static int stm32l4_mass_erase(struct flash_bank *bank)
912 {
913 int retval;
914 struct target *target = bank->target;
915 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
916
917 uint32_t action = FLASH_MER1;
918
919 if (stm32l4_info->part_info->has_dual_bank)
920 action |= FLASH_MER2;
921
922 if (target->state != TARGET_HALTED) {
923 LOG_ERROR("Target not halted");
924 return ERROR_TARGET_NOT_HALTED;
925 }
926
927 retval = stm32l4_unlock_reg(bank);
928 if (retval != ERROR_OK)
929 return retval;
930
931 /* mass erase flash memory */
932 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
933 if (retval != ERROR_OK)
934 return retval;
935
936 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action);
937 if (retval != ERROR_OK)
938 return retval;
939 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action | FLASH_STRT);
940 if (retval != ERROR_OK)
941 return retval;
942
943 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
944 if (retval != ERROR_OK)
945 return retval;
946
947 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
948 if (retval != ERROR_OK)
949 return retval;
950
951 return ERROR_OK;
952 }
953
954 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
955 {
956 int i;
957
958 if (CMD_ARGC < 1) {
959 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
960 return ERROR_COMMAND_SYNTAX_ERROR;
961 }
962
963 struct flash_bank *bank;
964 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
965 if (ERROR_OK != retval)
966 return retval;
967
968 retval = stm32l4_mass_erase(bank);
969 if (retval == ERROR_OK) {
970 /* set all sectors as erased */
971 for (i = 0; i < bank->num_sectors; i++)
972 bank->sectors[i].is_erased = 1;
973
974 command_print(CMD, "stm32l4x mass erase complete");
975 } else {
976 command_print(CMD, "stm32l4x mass erase failed");
977 }
978
979 return retval;
980 }
981
982 COMMAND_HANDLER(stm32l4_handle_option_read_command)
983 {
984 if (CMD_ARGC < 2) {
985 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
986 return ERROR_COMMAND_SYNTAX_ERROR;
987 }
988
989 struct flash_bank *bank;
990 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
991 if (ERROR_OK != retval)
992 return retval;
993
994 uint32_t reg_offset, reg_addr;
995 uint32_t value = 0;
996
997 reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
998 reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
999
1000 retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
1001 if (ERROR_OK != retval)
1002 return retval;
1003
1004 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
1005
1006 return retval;
1007 }
1008
1009 COMMAND_HANDLER(stm32l4_handle_option_write_command)
1010 {
1011 if (CMD_ARGC < 3) {
1012 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
1013 return ERROR_COMMAND_SYNTAX_ERROR;
1014 }
1015
1016 struct flash_bank *bank;
1017 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1018 if (ERROR_OK != retval)
1019 return retval;
1020
1021 uint32_t reg_offset;
1022 uint32_t value = 0;
1023 uint32_t mask = 0xFFFFFFFF;
1024
1025 reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
1026 value = strtoul(CMD_ARGV[2], NULL, 16);
1027 if (CMD_ARGC > 3)
1028 mask = strtoul(CMD_ARGV[3], NULL, 16);
1029
1030 command_print(CMD, "%s Option written.\n"
1031 "INFO: a reset or power cycle is required "
1032 "for the new settings to take effect.", bank->driver->name);
1033
1034 retval = stm32l4_write_option(bank, reg_offset, value, mask);
1035 return retval;
1036 }
1037
1038 COMMAND_HANDLER(stm32l4_handle_option_load_command)
1039 {
1040 if (CMD_ARGC < 1)
1041 return ERROR_COMMAND_SYNTAX_ERROR;
1042
1043 struct flash_bank *bank;
1044 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1045 if (ERROR_OK != retval)
1046 return retval;
1047
1048 retval = stm32l4_unlock_reg(bank);
1049 if (ERROR_OK != retval)
1050 return retval;
1051
1052 retval = stm32l4_unlock_option_reg(bank);
1053 if (ERROR_OK != retval)
1054 return retval;
1055
1056 /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
1057 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBLLAUNCH);
1058
1059 command_print(CMD, "stm32l4x option load (POR) completed.");
1060 return retval;
1061 }
1062
1063 COMMAND_HANDLER(stm32l4_handle_lock_command)
1064 {
1065 struct target *target = NULL;
1066
1067 if (CMD_ARGC < 1)
1068 return ERROR_COMMAND_SYNTAX_ERROR;
1069
1070 struct flash_bank *bank;
1071 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1072 if (ERROR_OK != retval)
1073 return retval;
1074
1075 target = bank->target;
1076
1077 if (target->state != TARGET_HALTED) {
1078 LOG_ERROR("Target not halted");
1079 return ERROR_TARGET_NOT_HALTED;
1080 }
1081
1082 /* set readout protection level 1 by erasing the RDP option byte */
1083 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
1084 command_print(CMD, "%s failed to lock device", bank->driver->name);
1085 return ERROR_OK;
1086 }
1087
1088 return ERROR_OK;
1089 }
1090
1091 COMMAND_HANDLER(stm32l4_handle_unlock_command)
1092 {
1093 struct target *target = NULL;
1094
1095 if (CMD_ARGC < 1)
1096 return ERROR_COMMAND_SYNTAX_ERROR;
1097
1098 struct flash_bank *bank;
1099 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1100 if (ERROR_OK != retval)
1101 return retval;
1102
1103 target = bank->target;
1104
1105 if (target->state != TARGET_HALTED) {
1106 LOG_ERROR("Target not halted");
1107 return ERROR_TARGET_NOT_HALTED;
1108 }
1109
1110 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
1111 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1112 return ERROR_OK;
1113 }
1114
1115 return ERROR_OK;
1116 }
1117
1118 static const struct command_registration stm32l4_exec_command_handlers[] = {
1119 {
1120 .name = "lock",
1121 .handler = stm32l4_handle_lock_command,
1122 .mode = COMMAND_EXEC,
1123 .usage = "bank_id",
1124 .help = "Lock entire flash device.",
1125 },
1126 {
1127 .name = "unlock",
1128 .handler = stm32l4_handle_unlock_command,
1129 .mode = COMMAND_EXEC,
1130 .usage = "bank_id",
1131 .help = "Unlock entire protected flash device.",
1132 },
1133 {
1134 .name = "mass_erase",
1135 .handler = stm32l4_handle_mass_erase_command,
1136 .mode = COMMAND_EXEC,
1137 .usage = "bank_id",
1138 .help = "Erase entire flash device.",
1139 },
1140 {
1141 .name = "option_read",
1142 .handler = stm32l4_handle_option_read_command,
1143 .mode = COMMAND_EXEC,
1144 .usage = "bank_id reg_offset",
1145 .help = "Read & Display device option bytes.",
1146 },
1147 {
1148 .name = "option_write",
1149 .handler = stm32l4_handle_option_write_command,
1150 .mode = COMMAND_EXEC,
1151 .usage = "bank_id reg_offset value mask",
1152 .help = "Write device option bit fields with provided value.",
1153 },
1154 {
1155 .name = "option_load",
1156 .handler = stm32l4_handle_option_load_command,
1157 .mode = COMMAND_EXEC,
1158 .usage = "bank_id",
1159 .help = "Force re-load of device options (will cause device reset).",
1160 },
1161 COMMAND_REGISTRATION_DONE
1162 };
1163
1164 static const struct command_registration stm32l4_command_handlers[] = {
1165 {
1166 .name = "stm32l4x",
1167 .mode = COMMAND_ANY,
1168 .help = "stm32l4x flash command group",
1169 .usage = "",
1170 .chain = stm32l4_exec_command_handlers,
1171 },
1172 COMMAND_REGISTRATION_DONE
1173 };
1174
1175 const struct flash_driver stm32l4x_flash = {
1176 .name = "stm32l4x",
1177 .commands = stm32l4_command_handlers,
1178 .flash_bank_command = stm32l4_flash_bank_command,
1179 .erase = stm32l4_erase,
1180 .protect = stm32l4_protect,
1181 .write = stm32l4_write,
1182 .read = default_flash_read,
1183 .probe = stm32l4_probe,
1184 .auto_probe = stm32l4_auto_probe,
1185 .erase_check = default_flash_blank_check,
1186 .protect_check = stm32l4_protect_check,
1187 .info = get_stm32l4_info,
1188 .free_driver_priv = default_flash_free_driver_priv,
1189 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)