1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
27 #include <helper/binarybuffer.h>
28 #include <target/algorithm.h>
29 #include <target/armv7m.h>
32 /* STM32L4xxx series for reference.
34 * RM0351 (STM32L4x5/STM32L4x6)
35 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
37 * RM0394 (STM32L43x/44x/45x/46x)
38 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
40 * RM0432 (STM32L4R/4Sxx)
41 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
43 * STM32L476RG Datasheet (for erase timing)
44 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
46 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
47 * an option byte is available to map all sectors to the first bank.
48 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
51 * RM0394 devices have a single bank only.
53 * RM0432 devices have single and dual bank operating modes.
54 * The FLASH size is 1Mbyte or 2Mbyte.
55 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
57 * Bank mode is controlled by two different bits in option bytes register.
58 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
59 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
63 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
65 #define FLASH_ERASE_TIMEOUT 250
67 /* Flash registers offsets */
68 #define STM32_FLASH_ACR 0x00
69 #define STM32_FLASH_KEYR 0x08
70 #define STM32_FLASH_OPTKEYR 0x0c
71 #define STM32_FLASH_SR 0x10
72 #define STM32_FLASH_CR 0x14
73 #define STM32_FLASH_OPTR 0x20
74 #define STM32_FLASH_WRP1AR 0x2c
75 #define STM32_FLASH_WRP1BR 0x30
76 #define STM32_FLASH_WRP2AR 0x4c
77 #define STM32_FLASH_WRP2BR 0x50
79 /* FLASH_CR register bits */
80 #define FLASH_PG (1 << 0)
81 #define FLASH_PER (1 << 1)
82 #define FLASH_MER1 (1 << 2)
83 #define FLASH_PAGE_SHIFT 3
84 #define FLASH_CR_BKER (1 << 11)
85 #define FLASH_MER2 (1 << 15)
86 #define FLASH_STRT (1 << 16)
87 #define FLASH_OPTSTRT (1 << 17)
88 #define FLASH_EOPIE (1 << 24)
89 #define FLASH_ERRIE (1 << 25)
90 #define FLASH_OBLLAUNCH (1 << 27)
91 #define FLASH_OPTLOCK (1 << 30)
92 #define FLASH_LOCK (1 << 31)
94 /* FLASH_SR register bits */
95 #define FLASH_BSY (1 << 16)
96 /* Fast programming not used => related errors not used*/
97 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
98 #define FLASH_SIZERR (1 << 6) /* Size error */
99 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
100 #define FLASH_WRPERR (1 << 4) /* Write protection error */
101 #define FLASH_PROGERR (1 << 3) /* Programming error */
102 #define FLASH_OPERR (1 << 1) /* Operation error */
103 #define FLASH_EOP (1 << 0) /* End of operation */
104 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
106 /* register unlock keys */
107 #define KEY1 0x45670123
108 #define KEY2 0xCDEF89AB
110 /* option register unlock key */
111 #define OPTKEY1 0x08192A3B
112 #define OPTKEY2 0x4C5D6E7F
114 #define RDP_LEVEL_0 0xAA
115 #define RDP_LEVEL_1 0xBB
116 #define RDP_LEVEL_2 0xCC
119 /* other registers */
120 #define DBGMCU_IDCODE 0xE0042000
128 struct stm32l4_part_info
{
130 const char *device_str
;
131 const struct stm32l4_rev
*revs
;
132 const size_t num_revs
;
133 const uint16_t max_flash_size_kb
;
134 const bool has_dual_bank
;
135 const uint32_t flash_regs_base
;
136 const uint32_t fsize_addr
;
139 struct stm32l4_flash_bank
{
145 const struct stm32l4_part_info
*part_info
;
148 static const struct stm32l4_rev stm32_415_revs
[] = {
149 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
152 static const struct stm32l4_rev stm32_435_revs
[] = {
153 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
156 static const struct stm32l4_rev stm32_461_revs
[] = {
157 { 0x1000, "A" }, { 0x2000, "B" },
160 static const struct stm32l4_rev stm32_462_revs
[] = {
161 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
164 static const struct stm32l4_rev stm32_464_revs
[] = {
168 static const struct stm32l4_rev stm32_470_revs
[] = {
169 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
172 static const struct stm32l4_part_info stm32l4_parts
[] = {
175 .revs
= stm32_415_revs
,
176 .num_revs
= ARRAY_SIZE(stm32_415_revs
),
177 .device_str
= "STM32L47/L48xx",
178 .max_flash_size_kb
= 1024,
179 .has_dual_bank
= true,
180 .flash_regs_base
= 0x40022000,
181 .fsize_addr
= 0x1FFF75E0,
185 .revs
= stm32_435_revs
,
186 .num_revs
= ARRAY_SIZE(stm32_435_revs
),
187 .device_str
= "STM32L43/L44xx",
188 .max_flash_size_kb
= 256,
189 .has_dual_bank
= false,
190 .flash_regs_base
= 0x40022000,
191 .fsize_addr
= 0x1FFF75E0,
195 .revs
= stm32_461_revs
,
196 .num_revs
= ARRAY_SIZE(stm32_461_revs
),
197 .device_str
= "STM32L49/L4Axx",
198 .max_flash_size_kb
= 1024,
199 .has_dual_bank
= true,
200 .flash_regs_base
= 0x40022000,
201 .fsize_addr
= 0x1FFF75E0,
205 .revs
= stm32_462_revs
,
206 .num_revs
= ARRAY_SIZE(stm32_462_revs
),
207 .device_str
= "STM32L45/L46xx",
208 .max_flash_size_kb
= 512,
209 .has_dual_bank
= false,
210 .flash_regs_base
= 0x40022000,
211 .fsize_addr
= 0x1FFF75E0,
215 .revs
= stm32_464_revs
,
216 .num_revs
= ARRAY_SIZE(stm32_464_revs
),
217 .device_str
= "STM32L41/L42xx",
218 .max_flash_size_kb
= 128,
219 .has_dual_bank
= false,
220 .flash_regs_base
= 0x40022000,
221 .fsize_addr
= 0x1FFF75E0,
225 .revs
= stm32_470_revs
,
226 .num_revs
= ARRAY_SIZE(stm32_470_revs
),
227 .device_str
= "STM32L4R/L4Sxx",
228 .max_flash_size_kb
= 2048,
229 .has_dual_bank
= true,
230 .flash_regs_base
= 0x40022000,
231 .fsize_addr
= 0x1FFF75E0,
235 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
236 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command
)
238 struct stm32l4_flash_bank
*stm32l4_info
;
241 return ERROR_COMMAND_SYNTAX_ERROR
;
243 stm32l4_info
= malloc(sizeof(struct stm32l4_flash_bank
));
245 return ERROR_FAIL
; /* Checkme: What better error to use?*/
246 bank
->driver_priv
= stm32l4_info
;
248 stm32l4_info
->probed
= 0;
253 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
)
255 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
256 return stm32l4_info
->part_info
->flash_regs_base
+ reg_offset
;
259 static inline int stm32l4_read_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t *value
)
261 return target_read_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
264 static inline int stm32l4_write_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
)
266 return target_write_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
269 static int stm32l4_wait_status_busy(struct flash_bank
*bank
, int timeout
)
272 int retval
= ERROR_OK
;
274 /* wait for busy to clear */
276 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_SR
, &status
);
277 if (retval
!= ERROR_OK
)
279 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
280 if ((status
& FLASH_BSY
) == 0)
282 if (timeout
-- <= 0) {
283 LOG_ERROR("timed out waiting for flash");
290 if (status
& FLASH_WRPERR
) {
291 LOG_ERROR("stm32x device protected");
295 /* Clear but report errors */
296 if (status
& FLASH_ERROR
) {
297 if (retval
== ERROR_OK
)
299 /* If this operation fails, we ignore it and report the original
302 stm32l4_write_flash_reg(bank
, STM32_FLASH_SR
, status
& FLASH_ERROR
);
308 static int stm32l4_unlock_reg(struct flash_bank
*bank
)
312 /* first check if not already unlocked
313 * otherwise writing on STM32_FLASH_KEYR will fail
315 int retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
316 if (retval
!= ERROR_OK
)
319 if ((ctrl
& FLASH_LOCK
) == 0)
322 /* unlock flash registers */
323 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_KEYR
, KEY1
);
324 if (retval
!= ERROR_OK
)
327 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_KEYR
, KEY2
);
328 if (retval
!= ERROR_OK
)
331 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
332 if (retval
!= ERROR_OK
)
335 if (ctrl
& FLASH_LOCK
) {
336 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
337 return ERROR_TARGET_FAILURE
;
343 static int stm32l4_unlock_option_reg(struct flash_bank
*bank
)
347 int retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
348 if (retval
!= ERROR_OK
)
351 if ((ctrl
& FLASH_OPTLOCK
) == 0)
354 /* unlock option registers */
355 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_OPTKEYR
, OPTKEY1
);
356 if (retval
!= ERROR_OK
)
359 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_OPTKEYR
, OPTKEY2
);
360 if (retval
!= ERROR_OK
)
363 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
364 if (retval
!= ERROR_OK
)
367 if (ctrl
& FLASH_OPTLOCK
) {
368 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
369 return ERROR_TARGET_FAILURE
;
375 static int stm32l4_write_option(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
, uint32_t mask
)
379 int retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &optiondata
);
380 if (retval
!= ERROR_OK
)
383 retval
= stm32l4_unlock_reg(bank
);
384 if (retval
!= ERROR_OK
)
387 retval
= stm32l4_unlock_option_reg(bank
);
388 if (retval
!= ERROR_OK
)
391 optiondata
= (optiondata
& ~mask
) | (value
& mask
);
393 retval
= stm32l4_write_flash_reg(bank
, reg_offset
, optiondata
);
394 if (retval
!= ERROR_OK
)
397 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_OPTSTRT
);
398 if (retval
!= ERROR_OK
)
401 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
402 if (retval
!= ERROR_OK
)
408 static int stm32l4_protect_check(struct flash_bank
*bank
)
410 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
412 uint32_t wrp1ar
, wrp1br
, wrp2ar
, wrp2br
;
413 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP1AR
, &wrp1ar
);
414 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP1BR
, &wrp1br
);
415 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP2AR
, &wrp2ar
);
416 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP2BR
, &wrp2br
);
418 const uint8_t wrp1a_start
= wrp1ar
& 0xFF;
419 const uint8_t wrp1a_end
= (wrp1ar
>> 16) & 0xFF;
420 const uint8_t wrp1b_start
= wrp1br
& 0xFF;
421 const uint8_t wrp1b_end
= (wrp1br
>> 16) & 0xFF;
422 const uint8_t wrp2a_start
= wrp2ar
& 0xFF;
423 const uint8_t wrp2a_end
= (wrp2ar
>> 16) & 0xFF;
424 const uint8_t wrp2b_start
= wrp2br
& 0xFF;
425 const uint8_t wrp2b_end
= (wrp2br
>> 16) & 0xFF;
427 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
428 if (i
< stm32l4_info
->bank1_sectors
) {
429 if (((i
>= wrp1a_start
) &&
431 ((i
>= wrp1b_start
) &&
433 bank
->sectors
[i
].is_protected
= 1;
435 bank
->sectors
[i
].is_protected
= 0;
438 snb
= i
- stm32l4_info
->bank1_sectors
;
439 if (((snb
>= wrp2a_start
) &&
440 (snb
<= wrp2a_end
)) ||
441 ((snb
>= wrp2b_start
) &&
443 bank
->sectors
[i
].is_protected
= 1;
445 bank
->sectors
[i
].is_protected
= 0;
451 static int stm32l4_erase(struct flash_bank
*bank
, int first
, int last
)
453 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
457 assert(first
< bank
->num_sectors
);
458 assert(last
< bank
->num_sectors
);
460 if (bank
->target
->state
!= TARGET_HALTED
) {
461 LOG_ERROR("Target not halted");
462 return ERROR_TARGET_NOT_HALTED
;
465 retval
= stm32l4_unlock_reg(bank
);
466 if (retval
!= ERROR_OK
)
471 To erase a sector, follow the procedure below:
472 1. Check that no Flash memory operation is ongoing by
473 checking the BSY bit in the FLASH_SR register
474 2. Set the PER bit and select the page and bank
475 you wish to erase in the FLASH_CR register
476 3. Set the STRT bit in the FLASH_CR register
477 4. Wait for the BSY bit to be cleared
480 for (i
= first
; i
<= last
; i
++) {
481 uint32_t erase_flags
;
482 erase_flags
= FLASH_PER
| FLASH_STRT
;
484 if (i
>= stm32l4_info
->bank1_sectors
) {
486 snb
= i
- stm32l4_info
->bank1_sectors
;
487 erase_flags
|= snb
<< FLASH_PAGE_SHIFT
| FLASH_CR_BKER
;
489 erase_flags
|= i
<< FLASH_PAGE_SHIFT
;
490 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, erase_flags
);
491 if (retval
!= ERROR_OK
)
494 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
495 if (retval
!= ERROR_OK
)
498 bank
->sectors
[i
].is_erased
= 1;
501 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
);
502 if (retval
!= ERROR_OK
)
508 static int stm32l4_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
510 struct target
*target
= bank
->target
;
511 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
513 if (target
->state
!= TARGET_HALTED
) {
514 LOG_ERROR("Target not halted");
515 return ERROR_TARGET_NOT_HALTED
;
520 uint32_t reg_value
= 0xFF; /* Default to bank un-protected */
521 if (last
>= stm32l4_info
->bank1_sectors
) {
523 uint8_t begin
= first
> stm32l4_info
->bank1_sectors
? first
: 0x00;
524 reg_value
= ((last
& 0xFF) << 16) | begin
;
527 ret
= stm32l4_write_option(bank
, STM32_FLASH_WRP2AR
, reg_value
, 0xffffffff);
530 reg_value
= 0xFF; /* Default to bank un-protected */
531 if (first
< stm32l4_info
->bank1_sectors
) {
533 uint8_t end
= last
>= stm32l4_info
->bank1_sectors
? 0xFF : last
;
534 reg_value
= (end
<< 16) | (first
& 0xFF);
537 ret
= stm32l4_write_option(bank
, STM32_FLASH_WRP1AR
, reg_value
, 0xffffffff);
543 /* Count is in halfwords */
544 static int stm32l4_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
545 uint32_t offset
, uint32_t count
)
547 struct target
*target
= bank
->target
;
548 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
549 uint32_t buffer_size
= 16384;
550 struct working_area
*write_algorithm
;
551 struct working_area
*source
;
552 uint32_t address
= bank
->base
+ offset
;
553 struct reg_param reg_params
[5];
554 struct armv7m_algorithm armv7m_info
;
555 int retval
= ERROR_OK
;
557 static const uint8_t stm32l4_flash_write_code
[] = {
558 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
561 if (target_alloc_working_area(target
, sizeof(stm32l4_flash_write_code
),
562 &write_algorithm
) != ERROR_OK
) {
563 LOG_WARNING("no working area available, can't do block memory writes");
564 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
567 retval
= target_write_buffer(target
, write_algorithm
->address
,
568 sizeof(stm32l4_flash_write_code
),
569 stm32l4_flash_write_code
);
570 if (retval
!= ERROR_OK
) {
571 target_free_working_area(target
, write_algorithm
);
576 while (target_alloc_working_area_try(target
, buffer_size
, &source
) !=
579 if (buffer_size
<= 256) {
580 /* we already allocated the writing code, but failed to get a
581 * buffer, free the algorithm */
582 target_free_working_area(target
, write_algorithm
);
584 LOG_WARNING("large enough working area not available, can't do block memory writes");
585 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
589 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
590 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
592 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
593 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
594 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
595 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (double word-64bit) */
596 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
); /* flash base */
598 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
599 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
600 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
601 buf_set_u32(reg_params
[3].value
, 0, 32, count
/ 4);
602 buf_set_u32(reg_params
[4].value
, 0, 32, stm32l4_info
->part_info
->flash_regs_base
);
604 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
607 source
->address
, source
->size
,
608 write_algorithm
->address
, 0,
611 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
612 LOG_ERROR("error executing stm32l4 flash write algorithm");
614 uint32_t error
= buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_ERROR
;
616 if (error
& FLASH_WRPERR
)
617 LOG_ERROR("flash memory write protected");
620 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
621 /* Clear but report errors */
622 stm32l4_write_flash_reg(bank
, STM32_FLASH_SR
, error
);
627 target_free_working_area(target
, source
);
628 target_free_working_area(target
, write_algorithm
);
630 destroy_reg_param(®_params
[0]);
631 destroy_reg_param(®_params
[1]);
632 destroy_reg_param(®_params
[2]);
633 destroy_reg_param(®_params
[3]);
634 destroy_reg_param(®_params
[4]);
639 static int stm32l4_write(struct flash_bank
*bank
, const uint8_t *buffer
,
640 uint32_t offset
, uint32_t count
)
644 if (bank
->target
->state
!= TARGET_HALTED
) {
645 LOG_ERROR("Target not halted");
646 return ERROR_TARGET_NOT_HALTED
;
650 LOG_WARNING("offset 0x%" PRIx32
" breaks required 8-byte alignment",
652 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
656 LOG_WARNING("Padding %d bytes to keep 8-byte write size",
658 count
= (count
+ 7) & ~7;
659 /* This pads the write chunk with random bytes by overrunning the
660 * write buffer. Padding with the erased pattern 0xff is purely
661 * cosmetical, as 8-byte flash words are ECC secured and the first
662 * write will program the ECC bits. A second write would need
663 * to reprogramm these ECC bits.
664 * But this can only be done after erase!
668 retval
= stm32l4_unlock_reg(bank
);
669 if (retval
!= ERROR_OK
)
672 /* Only full double words (8-byte) can be programmed*/
673 retval
= stm32l4_write_block(bank
, buffer
, offset
, count
/ 2);
674 if (retval
!= ERROR_OK
) {
675 LOG_WARNING("block write failed");
679 LOG_WARNING("block write succeeded");
680 return stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
);
683 static int stm32l4_read_idcode(struct flash_bank
*bank
, uint32_t *id
)
685 int retval
= target_read_u32(bank
->target
, DBGMCU_IDCODE
, id
);
686 if (retval
!= ERROR_OK
)
692 static int stm32l4_probe(struct flash_bank
*bank
)
694 struct target
*target
= bank
->target
;
695 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
696 const struct stm32l4_part_info
*part_info
;
698 uint16_t flash_size_in_kb
= 0xffff;
702 stm32l4_info
->probed
= 0;
704 /* read stm32 device id register */
705 int retval
= stm32l4_read_idcode(bank
, &stm32l4_info
->idcode
);
706 if (retval
!= ERROR_OK
)
709 device_id
= stm32l4_info
->idcode
& 0xFFF;
711 for (unsigned int n
= 0; n
< ARRAY_SIZE(stm32l4_parts
); n
++) {
712 if (device_id
== stm32l4_parts
[n
].id
)
713 stm32l4_info
->part_info
= &stm32l4_parts
[n
];
716 if (!stm32l4_info
->part_info
) {
717 LOG_WARNING("Cannot identify target as an STM32L4 family device.");
721 part_info
= stm32l4_info
->part_info
;
723 char device_info
[1024];
724 retval
= bank
->driver
->info(bank
, device_info
, sizeof(device_info
));
725 if (retval
!= ERROR_OK
)
728 LOG_INFO("device idcode = 0x%08" PRIx32
" (%s)", stm32l4_info
->idcode
, device_info
);
730 /* get flash size from target. */
731 retval
= target_read_u16(target
, part_info
->fsize_addr
, &flash_size_in_kb
);
733 /* failed reading flash size or flash size invalid (early silicon),
734 * default to max target family */
735 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0
736 || flash_size_in_kb
> part_info
->max_flash_size_kb
) {
737 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
738 part_info
->max_flash_size_kb
);
739 flash_size_in_kb
= part_info
->max_flash_size_kb
;
742 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
744 /* did we assign a flash size? */
745 assert((flash_size_in_kb
!= 0xffff) && flash_size_in_kb
);
747 /* read flash option register */
748 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_OPTR
, &options
);
749 if (retval
!= ERROR_OK
)
752 stm32l4_info
->bank1_sectors
= 0;
753 stm32l4_info
->hole_sectors
= 0;
758 stm32l4_info
->dual_bank_mode
= false;
763 /* if flash size is max (1M) the device is always dual bank
764 * 0x415: has variants with 512K
765 * 0x461: has variants with 512 and 256
766 * for these variants:
767 * if DUAL_BANK = 0 -> single bank
768 * else -> dual bank without gap
769 * note: the page size is invariant
772 num_pages
= flash_size_in_kb
/ 2;
773 stm32l4_info
->bank1_sectors
= num_pages
;
775 /* check DUAL_BANK bit[21] if the flash is less than 1M */
776 if (flash_size_in_kb
== 1024 || (options
& BIT(21))) {
777 stm32l4_info
->dual_bank_mode
= true;
778 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
784 /* single bank flash */
786 num_pages
= flash_size_in_kb
/ 2;
787 stm32l4_info
->bank1_sectors
= num_pages
;
790 /* STM32L4R/S can be single/dual bank:
791 * if size = 2M check DBANK bit(22)
792 * if size = 1M check DB1M bit(21)
793 * in single bank configuration the page size is 8K
794 * else (dual bank) the page size is 4K without gap between banks
797 num_pages
= flash_size_in_kb
/ 8;
798 stm32l4_info
->bank1_sectors
= num_pages
;
799 if ((flash_size_in_kb
== 2048 && (options
& BIT(22))) ||
800 (flash_size_in_kb
== 1024 && (options
& BIT(21)))) {
801 stm32l4_info
->dual_bank_mode
= true;
803 num_pages
= flash_size_in_kb
/ 4;
804 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
808 LOG_ERROR("unsupported device");
812 LOG_INFO("flash mode : %s-bank", stm32l4_info
->dual_bank_mode
? "dual" : "single");
814 const int gap_size
= stm32l4_info
->hole_sectors
* page_size
;
816 if (stm32l4_info
->dual_bank_mode
& gap_size
) {
817 LOG_INFO("gap detected starting from %0x08" PRIx32
" to %0x08" PRIx32
,
818 0x8000000 + stm32l4_info
->bank1_sectors
* page_size
,
819 0x8000000 + stm32l4_info
->bank1_sectors
* page_size
+ gap_size
);
824 bank
->sectors
= NULL
;
827 bank
->size
= flash_size_in_kb
* 1024 + gap_size
;
828 bank
->base
= 0x08000000;
829 bank
->num_sectors
= num_pages
;
830 bank
->sectors
= malloc(sizeof(struct flash_sector
) * bank
->num_sectors
);
831 if (bank
->sectors
== NULL
) {
832 LOG_ERROR("failed to allocate bank sectors");
836 for (i
= 0; i
< bank
->num_sectors
; i
++) {
837 bank
->sectors
[i
].offset
= i
* page_size
;
838 /* in dual bank configuration, if there is a gap between banks
839 * we fix up the sector offset to consider this gap */
840 if (i
>= stm32l4_info
->bank1_sectors
&& stm32l4_info
->hole_sectors
)
841 bank
->sectors
[i
].offset
+= gap_size
;
842 bank
->sectors
[i
].size
= page_size
;
843 bank
->sectors
[i
].is_erased
= -1;
844 bank
->sectors
[i
].is_protected
= 1;
847 stm32l4_info
->probed
= 1;
851 static int stm32l4_auto_probe(struct flash_bank
*bank
)
853 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
854 if (stm32l4_info
->probed
)
857 return stm32l4_probe(bank
);
860 static int get_stm32l4_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
862 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
863 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
866 const char *rev_str
= NULL
;
867 uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
868 for (unsigned int i
= 0; i
< part_info
->num_revs
; i
++) {
869 if (rev_id
== part_info
->revs
[i
].rev
) {
870 rev_str
= part_info
->revs
[i
].str
;
872 if (rev_str
!= NULL
) {
873 snprintf(buf
, buf_size
, "%s - Rev: %s",
874 part_info
->device_str
, rev_str
);
880 snprintf(buf
, buf_size
, "%s - Rev: unknown (0x%04x)",
881 part_info
->device_str
, rev_id
);
884 snprintf(buf
, buf_size
, "Cannot identify target as a STM32L4x device");
891 static int stm32l4_mass_erase(struct flash_bank
*bank
)
894 struct target
*target
= bank
->target
;
895 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
897 uint32_t action
= FLASH_MER1
;
899 if (stm32l4_info
->part_info
->has_dual_bank
)
900 action
|= FLASH_MER2
;
902 if (target
->state
!= TARGET_HALTED
) {
903 LOG_ERROR("Target not halted");
904 return ERROR_TARGET_NOT_HALTED
;
907 retval
= stm32l4_unlock_reg(bank
);
908 if (retval
!= ERROR_OK
)
911 /* mass erase flash memory */
912 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
/ 10);
913 if (retval
!= ERROR_OK
)
916 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, action
);
917 if (retval
!= ERROR_OK
)
919 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, action
| FLASH_STRT
);
920 if (retval
!= ERROR_OK
)
923 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
924 if (retval
!= ERROR_OK
)
927 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
);
928 if (retval
!= ERROR_OK
)
934 COMMAND_HANDLER(stm32l4_handle_mass_erase_command
)
939 command_print(CMD
, "stm32l4x mass_erase <STM32L4 bank>");
940 return ERROR_COMMAND_SYNTAX_ERROR
;
943 struct flash_bank
*bank
;
944 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
945 if (ERROR_OK
!= retval
)
948 retval
= stm32l4_mass_erase(bank
);
949 if (retval
== ERROR_OK
) {
950 /* set all sectors as erased */
951 for (i
= 0; i
< bank
->num_sectors
; i
++)
952 bank
->sectors
[i
].is_erased
= 1;
954 command_print(CMD
, "stm32l4x mass erase complete");
956 command_print(CMD
, "stm32l4x mass erase failed");
962 COMMAND_HANDLER(stm32l4_handle_option_read_command
)
965 command_print(CMD
, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
966 return ERROR_COMMAND_SYNTAX_ERROR
;
969 struct flash_bank
*bank
;
970 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
971 if (ERROR_OK
!= retval
)
974 uint32_t reg_offset
, reg_addr
;
977 reg_offset
= strtoul(CMD_ARGV
[1], NULL
, 16);
978 reg_addr
= stm32l4_get_flash_reg(bank
, reg_offset
);
980 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &value
);
981 if (ERROR_OK
!= retval
)
984 command_print(CMD
, "Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"", reg_addr
, value
);
989 COMMAND_HANDLER(stm32l4_handle_option_write_command
)
992 command_print(CMD
, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
993 return ERROR_COMMAND_SYNTAX_ERROR
;
996 struct flash_bank
*bank
;
997 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
998 if (ERROR_OK
!= retval
)
1001 uint32_t reg_offset
;
1003 uint32_t mask
= 0xFFFFFFFF;
1005 reg_offset
= strtoul(CMD_ARGV
[1], NULL
, 16);
1006 value
= strtoul(CMD_ARGV
[2], NULL
, 16);
1008 mask
= strtoul(CMD_ARGV
[3], NULL
, 16);
1010 command_print(CMD
, "%s Option written.\n"
1011 "INFO: a reset or power cycle is required "
1012 "for the new settings to take effect.", bank
->driver
->name
);
1014 retval
= stm32l4_write_option(bank
, reg_offset
, value
, mask
);
1018 COMMAND_HANDLER(stm32l4_handle_option_load_command
)
1021 return ERROR_COMMAND_SYNTAX_ERROR
;
1023 struct flash_bank
*bank
;
1024 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1025 if (ERROR_OK
!= retval
)
1028 retval
= stm32l4_unlock_reg(bank
);
1029 if (ERROR_OK
!= retval
)
1032 retval
= stm32l4_unlock_option_reg(bank
);
1033 if (ERROR_OK
!= retval
)
1036 /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
1037 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_OBLLAUNCH
);
1039 command_print(CMD
, "stm32l4x option load (POR) completed.");
1043 COMMAND_HANDLER(stm32l4_handle_lock_command
)
1045 struct target
*target
= NULL
;
1048 return ERROR_COMMAND_SYNTAX_ERROR
;
1050 struct flash_bank
*bank
;
1051 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1052 if (ERROR_OK
!= retval
)
1055 target
= bank
->target
;
1057 if (target
->state
!= TARGET_HALTED
) {
1058 LOG_ERROR("Target not halted");
1059 return ERROR_TARGET_NOT_HALTED
;
1062 /* set readout protection level 1 by erasing the RDP option byte */
1063 if (stm32l4_write_option(bank
, STM32_FLASH_OPTR
, 0, 0x000000FF) != ERROR_OK
) {
1064 command_print(CMD
, "%s failed to lock device", bank
->driver
->name
);
1071 COMMAND_HANDLER(stm32l4_handle_unlock_command
)
1073 struct target
*target
= NULL
;
1076 return ERROR_COMMAND_SYNTAX_ERROR
;
1078 struct flash_bank
*bank
;
1079 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1080 if (ERROR_OK
!= retval
)
1083 target
= bank
->target
;
1085 if (target
->state
!= TARGET_HALTED
) {
1086 LOG_ERROR("Target not halted");
1087 return ERROR_TARGET_NOT_HALTED
;
1090 if (stm32l4_write_option(bank
, STM32_FLASH_OPTR
, RDP_LEVEL_0
, 0x000000FF) != ERROR_OK
) {
1091 command_print(CMD
, "%s failed to unlock device", bank
->driver
->name
);
1098 static const struct command_registration stm32l4_exec_command_handlers
[] = {
1101 .handler
= stm32l4_handle_lock_command
,
1102 .mode
= COMMAND_EXEC
,
1104 .help
= "Lock entire flash device.",
1108 .handler
= stm32l4_handle_unlock_command
,
1109 .mode
= COMMAND_EXEC
,
1111 .help
= "Unlock entire protected flash device.",
1114 .name
= "mass_erase",
1115 .handler
= stm32l4_handle_mass_erase_command
,
1116 .mode
= COMMAND_EXEC
,
1118 .help
= "Erase entire flash device.",
1121 .name
= "option_read",
1122 .handler
= stm32l4_handle_option_read_command
,
1123 .mode
= COMMAND_EXEC
,
1124 .usage
= "bank_id reg_offset",
1125 .help
= "Read & Display device option bytes.",
1128 .name
= "option_write",
1129 .handler
= stm32l4_handle_option_write_command
,
1130 .mode
= COMMAND_EXEC
,
1131 .usage
= "bank_id reg_offset value mask",
1132 .help
= "Write device option bit fields with provided value.",
1135 .name
= "option_load",
1136 .handler
= stm32l4_handle_option_load_command
,
1137 .mode
= COMMAND_EXEC
,
1139 .help
= "Force re-load of device options (will cause device reset).",
1141 COMMAND_REGISTRATION_DONE
1144 static const struct command_registration stm32l4_command_handlers
[] = {
1147 .mode
= COMMAND_ANY
,
1148 .help
= "stm32l4x flash command group",
1150 .chain
= stm32l4_exec_command_handlers
,
1152 COMMAND_REGISTRATION_DONE
1155 const struct flash_driver stm32l4x_flash
= {
1157 .commands
= stm32l4_command_handlers
,
1158 .flash_bank_command
= stm32l4_flash_bank_command
,
1159 .erase
= stm32l4_erase
,
1160 .protect
= stm32l4_protect
,
1161 .write
= stm32l4_write
,
1162 .read
= default_flash_read
,
1163 .probe
= stm32l4_probe
,
1164 .auto_probe
= stm32l4_auto_probe
,
1165 .erase_check
= default_flash_blank_check
,
1166 .protect_check
= stm32l4_protect_check
,
1167 .info
= get_stm32l4_info
,
1168 .free_driver_priv
= default_flash_free_driver_priv
,
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