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flash/nor: Rename flash_address() to cfi_flash_address()
[openocd.git] / src / flash / nor / stm32l4x.c
1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
4 * *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "imp.h"
27 #include <helper/binarybuffer.h>
28 #include <target/algorithm.h>
29 #include <target/armv7m.h>
30 #include "bits.h"
31
32 /* STM32L4xxx series for reference.
33 *
34 * RM0351 (STM32L4x5/STM32L4x6)
35 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
36 *
37 * RM0394 (STM32L43x/44x/45x/46x)
38 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
39 *
40 * RM0432 (STM32L4R/4Sxx)
41 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
42 *
43 * STM32L476RG Datasheet (for erase timing)
44 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
45 *
46 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
47 * an option byte is available to map all sectors to the first bank.
48 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
49 * handlers do!
50 *
51 * RM0394 devices have a single bank only.
52 *
53 * RM0432 devices have single and dual bank operating modes.
54 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
55 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
56 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
57 *
58 * Bank mode is controlled by two different bits in option bytes register.
59 * - for STM32L4R/Sxx
60 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
61 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
62 * - for STM32L4P5/Q5x
63 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
64 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
65 *
66 */
67
68 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
69
70 #define FLASH_ERASE_TIMEOUT 250
71
72 /* Flash registers offsets */
73 #define STM32_FLASH_ACR 0x00
74 #define STM32_FLASH_KEYR 0x08
75 #define STM32_FLASH_OPTKEYR 0x0c
76 #define STM32_FLASH_SR 0x10
77 #define STM32_FLASH_CR 0x14
78 #define STM32_FLASH_OPTR 0x20
79 #define STM32_FLASH_WRP1AR 0x2c
80 #define STM32_FLASH_WRP1BR 0x30
81 #define STM32_FLASH_WRP2AR 0x4c
82 #define STM32_FLASH_WRP2BR 0x50
83
84 /* FLASH_CR register bits */
85 #define FLASH_PG (1 << 0)
86 #define FLASH_PER (1 << 1)
87 #define FLASH_MER1 (1 << 2)
88 #define FLASH_PAGE_SHIFT 3
89 #define FLASH_CR_BKER (1 << 11)
90 #define FLASH_MER2 (1 << 15)
91 #define FLASH_STRT (1 << 16)
92 #define FLASH_OPTSTRT (1 << 17)
93 #define FLASH_EOPIE (1 << 24)
94 #define FLASH_ERRIE (1 << 25)
95 #define FLASH_OBLLAUNCH (1 << 27)
96 #define FLASH_OPTLOCK (1 << 30)
97 #define FLASH_LOCK (1 << 31)
98
99 /* FLASH_SR register bits */
100 #define FLASH_BSY (1 << 16)
101 /* Fast programming not used => related errors not used*/
102 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
103 #define FLASH_SIZERR (1 << 6) /* Size error */
104 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
105 #define FLASH_WRPERR (1 << 4) /* Write protection error */
106 #define FLASH_PROGERR (1 << 3) /* Programming error */
107 #define FLASH_OPERR (1 << 1) /* Operation error */
108 #define FLASH_EOP (1 << 0) /* End of operation */
109 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
110
111 /* register unlock keys */
112 #define KEY1 0x45670123
113 #define KEY2 0xCDEF89AB
114
115 /* option register unlock key */
116 #define OPTKEY1 0x08192A3B
117 #define OPTKEY2 0x4C5D6E7F
118
119 #define RDP_LEVEL_0 0xAA
120 #define RDP_LEVEL_1 0xBB
121 #define RDP_LEVEL_2 0xCC
122
123
124 /* other registers */
125 #define DBGMCU_IDCODE 0xE0042000
126
127
128 struct stm32l4_rev {
129 const uint16_t rev;
130 const char *str;
131 };
132
133 struct stm32l4_part_info {
134 uint16_t id;
135 const char *device_str;
136 const struct stm32l4_rev *revs;
137 const size_t num_revs;
138 const uint16_t max_flash_size_kb;
139 const bool has_dual_bank;
140 const uint32_t flash_regs_base;
141 const uint32_t fsize_addr;
142 };
143
144 struct stm32l4_flash_bank {
145 int probed;
146 uint32_t idcode;
147 int bank1_sectors;
148 bool dual_bank_mode;
149 int hole_sectors;
150 const struct stm32l4_part_info *part_info;
151 };
152
153 static const struct stm32l4_rev stm32_415_revs[] = {
154 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
155 };
156
157 static const struct stm32l4_rev stm32_435_revs[] = {
158 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
159 };
160
161 static const struct stm32l4_rev stm32_461_revs[] = {
162 { 0x1000, "A" }, { 0x2000, "B" },
163 };
164
165 static const struct stm32l4_rev stm32_462_revs[] = {
166 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
167 };
168
169 static const struct stm32l4_rev stm32_464_revs[] = {
170 { 0x1000, "A" },
171 };
172
173 static const struct stm32l4_rev stm32_470_revs[] = {
174 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
175 };
176
177 static const struct stm32l4_rev stm32_471_revs[] = {
178 { 0x1000, "1" },
179 };
180
181 static const struct stm32l4_rev stm32_495_revs[] = {
182 { 0x2001, "2.1" },
183 };
184
185 static const struct stm32l4_part_info stm32l4_parts[] = {
186 {
187 .id = 0x415,
188 .revs = stm32_415_revs,
189 .num_revs = ARRAY_SIZE(stm32_415_revs),
190 .device_str = "STM32L47/L48xx",
191 .max_flash_size_kb = 1024,
192 .has_dual_bank = true,
193 .flash_regs_base = 0x40022000,
194 .fsize_addr = 0x1FFF75E0,
195 },
196 {
197 .id = 0x435,
198 .revs = stm32_435_revs,
199 .num_revs = ARRAY_SIZE(stm32_435_revs),
200 .device_str = "STM32L43/L44xx",
201 .max_flash_size_kb = 256,
202 .has_dual_bank = false,
203 .flash_regs_base = 0x40022000,
204 .fsize_addr = 0x1FFF75E0,
205 },
206 {
207 .id = 0x461,
208 .revs = stm32_461_revs,
209 .num_revs = ARRAY_SIZE(stm32_461_revs),
210 .device_str = "STM32L49/L4Axx",
211 .max_flash_size_kb = 1024,
212 .has_dual_bank = true,
213 .flash_regs_base = 0x40022000,
214 .fsize_addr = 0x1FFF75E0,
215 },
216 {
217 .id = 0x462,
218 .revs = stm32_462_revs,
219 .num_revs = ARRAY_SIZE(stm32_462_revs),
220 .device_str = "STM32L45/L46xx",
221 .max_flash_size_kb = 512,
222 .has_dual_bank = false,
223 .flash_regs_base = 0x40022000,
224 .fsize_addr = 0x1FFF75E0,
225 },
226 {
227 .id = 0x464,
228 .revs = stm32_464_revs,
229 .num_revs = ARRAY_SIZE(stm32_464_revs),
230 .device_str = "STM32L41/L42xx",
231 .max_flash_size_kb = 128,
232 .has_dual_bank = false,
233 .flash_regs_base = 0x40022000,
234 .fsize_addr = 0x1FFF75E0,
235 },
236 {
237 .id = 0x470,
238 .revs = stm32_470_revs,
239 .num_revs = ARRAY_SIZE(stm32_470_revs),
240 .device_str = "STM32L4R/L4Sxx",
241 .max_flash_size_kb = 2048,
242 .has_dual_bank = true,
243 .flash_regs_base = 0x40022000,
244 .fsize_addr = 0x1FFF75E0,
245 },
246 {
247 .id = 0x471,
248 .revs = stm32_471_revs,
249 .num_revs = ARRAY_SIZE(stm32_471_revs),
250 .device_str = "STM32L4P5/L4Q5x",
251 .max_flash_size_kb = 1024,
252 .has_dual_bank = true,
253 .flash_regs_base = 0x40022000,
254 .fsize_addr = 0x1FFF75E0,
255 },
256 {
257 .id = 0x495,
258 .revs = stm32_495_revs,
259 .num_revs = ARRAY_SIZE(stm32_495_revs),
260 .device_str = "STM32WB5x",
261 .max_flash_size_kb = 1024,
262 .has_dual_bank = false,
263 .flash_regs_base = 0x58004000,
264 .fsize_addr = 0x1FFF75E0,
265 },
266 };
267
268 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
269 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
270 {
271 struct stm32l4_flash_bank *stm32l4_info;
272
273 if (CMD_ARGC < 6)
274 return ERROR_COMMAND_SYNTAX_ERROR;
275
276 stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
277 if (!stm32l4_info)
278 return ERROR_FAIL; /* Checkme: What better error to use?*/
279 bank->driver_priv = stm32l4_info;
280
281 stm32l4_info->probed = 0;
282
283 return ERROR_OK;
284 }
285
286 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
287 {
288 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
289 return stm32l4_info->part_info->flash_regs_base + reg_offset;
290 }
291
292 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
293 {
294 return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
295 }
296
297 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
298 {
299 return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
300 }
301
302 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
303 {
304 uint32_t status;
305 int retval = ERROR_OK;
306
307 /* wait for busy to clear */
308 for (;;) {
309 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_SR, &status);
310 if (retval != ERROR_OK)
311 return retval;
312 LOG_DEBUG("status: 0x%" PRIx32 "", status);
313 if ((status & FLASH_BSY) == 0)
314 break;
315 if (timeout-- <= 0) {
316 LOG_ERROR("timed out waiting for flash");
317 return ERROR_FAIL;
318 }
319 alive_sleep(1);
320 }
321
322
323 if (status & FLASH_WRPERR) {
324 LOG_ERROR("stm32x device protected");
325 retval = ERROR_FAIL;
326 }
327
328 /* Clear but report errors */
329 if (status & FLASH_ERROR) {
330 if (retval == ERROR_OK)
331 retval = ERROR_FAIL;
332 /* If this operation fails, we ignore it and report the original
333 * retval
334 */
335 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, status & FLASH_ERROR);
336 }
337
338 return retval;
339 }
340
341 static int stm32l4_unlock_reg(struct flash_bank *bank)
342 {
343 uint32_t ctrl;
344
345 /* first check if not already unlocked
346 * otherwise writing on STM32_FLASH_KEYR will fail
347 */
348 int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
349 if (retval != ERROR_OK)
350 return retval;
351
352 if ((ctrl & FLASH_LOCK) == 0)
353 return ERROR_OK;
354
355 /* unlock flash registers */
356 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY1);
357 if (retval != ERROR_OK)
358 return retval;
359
360 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY2);
361 if (retval != ERROR_OK)
362 return retval;
363
364 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
365 if (retval != ERROR_OK)
366 return retval;
367
368 if (ctrl & FLASH_LOCK) {
369 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
370 return ERROR_TARGET_FAILURE;
371 }
372
373 return ERROR_OK;
374 }
375
376 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
377 {
378 uint32_t ctrl;
379
380 int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
381 if (retval != ERROR_OK)
382 return retval;
383
384 if ((ctrl & FLASH_OPTLOCK) == 0)
385 return ERROR_OK;
386
387 /* unlock option registers */
388 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY1);
389 if (retval != ERROR_OK)
390 return retval;
391
392 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY2);
393 if (retval != ERROR_OK)
394 return retval;
395
396 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
397 if (retval != ERROR_OK)
398 return retval;
399
400 if (ctrl & FLASH_OPTLOCK) {
401 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
402 return ERROR_TARGET_FAILURE;
403 }
404
405 return ERROR_OK;
406 }
407
408 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
409 {
410 uint32_t optiondata;
411
412 int retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
413 if (retval != ERROR_OK)
414 return retval;
415
416 retval = stm32l4_unlock_reg(bank);
417 if (retval != ERROR_OK)
418 return retval;
419
420 retval = stm32l4_unlock_option_reg(bank);
421 if (retval != ERROR_OK)
422 return retval;
423
424 optiondata = (optiondata & ~mask) | (value & mask);
425
426 retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
427 if (retval != ERROR_OK)
428 return retval;
429
430 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OPTSTRT);
431 if (retval != ERROR_OK)
432 return retval;
433
434 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
435 if (retval != ERROR_OK)
436 return retval;
437
438 return retval;
439 }
440
441 static int stm32l4_protect_check(struct flash_bank *bank)
442 {
443 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
444
445 uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
446 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar);
447 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br);
448 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
449 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
450
451 const uint8_t wrp1a_start = wrp1ar & 0xFF;
452 const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
453 const uint8_t wrp1b_start = wrp1br & 0xFF;
454 const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
455 const uint8_t wrp2a_start = wrp2ar & 0xFF;
456 const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
457 const uint8_t wrp2b_start = wrp2br & 0xFF;
458 const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
459
460 for (int i = 0; i < bank->num_sectors; i++) {
461 if (i < stm32l4_info->bank1_sectors) {
462 if (((i >= wrp1a_start) &&
463 (i <= wrp1a_end)) ||
464 ((i >= wrp1b_start) &&
465 (i <= wrp1b_end)))
466 bank->sectors[i].is_protected = 1;
467 else
468 bank->sectors[i].is_protected = 0;
469 } else {
470 uint8_t snb;
471 snb = i - stm32l4_info->bank1_sectors;
472 if (((snb >= wrp2a_start) &&
473 (snb <= wrp2a_end)) ||
474 ((snb >= wrp2b_start) &&
475 (snb <= wrp2b_end)))
476 bank->sectors[i].is_protected = 1;
477 else
478 bank->sectors[i].is_protected = 0;
479 }
480 }
481 return ERROR_OK;
482 }
483
484 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
485 {
486 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
487 int i;
488 int retval;
489
490 assert(first < bank->num_sectors);
491 assert(last < bank->num_sectors);
492
493 if (bank->target->state != TARGET_HALTED) {
494 LOG_ERROR("Target not halted");
495 return ERROR_TARGET_NOT_HALTED;
496 }
497
498 retval = stm32l4_unlock_reg(bank);
499 if (retval != ERROR_OK)
500 return retval;
501
502 /*
503 Sector Erase
504 To erase a sector, follow the procedure below:
505 1. Check that no Flash memory operation is ongoing by
506 checking the BSY bit in the FLASH_SR register
507 2. Set the PER bit and select the page and bank
508 you wish to erase in the FLASH_CR register
509 3. Set the STRT bit in the FLASH_CR register
510 4. Wait for the BSY bit to be cleared
511 */
512
513 for (i = first; i <= last; i++) {
514 uint32_t erase_flags;
515 erase_flags = FLASH_PER | FLASH_STRT;
516
517 if (i >= stm32l4_info->bank1_sectors) {
518 uint8_t snb;
519 snb = i - stm32l4_info->bank1_sectors;
520 erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
521 } else
522 erase_flags |= i << FLASH_PAGE_SHIFT;
523 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, erase_flags);
524 if (retval != ERROR_OK)
525 return retval;
526
527 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
528 if (retval != ERROR_OK)
529 return retval;
530
531 bank->sectors[i].is_erased = 1;
532 }
533
534 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
535 if (retval != ERROR_OK)
536 return retval;
537
538 return ERROR_OK;
539 }
540
541 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
542 {
543 struct target *target = bank->target;
544 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
545
546 if (target->state != TARGET_HALTED) {
547 LOG_ERROR("Target not halted");
548 return ERROR_TARGET_NOT_HALTED;
549 }
550
551 int ret = ERROR_OK;
552 /* Bank 2 */
553 uint32_t reg_value = 0xFF; /* Default to bank un-protected */
554 if (last >= stm32l4_info->bank1_sectors) {
555 if (set == 1) {
556 uint8_t begin = first > stm32l4_info->bank1_sectors ? first : 0x00;
557 reg_value = ((last & 0xFF) << 16) | begin;
558 }
559
560 ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
561 }
562 /* Bank 1 */
563 reg_value = 0xFF; /* Default to bank un-protected */
564 if (first < stm32l4_info->bank1_sectors) {
565 if (set == 1) {
566 uint8_t end = last >= stm32l4_info->bank1_sectors ? 0xFF : last;
567 reg_value = (end << 16) | (first & 0xFF);
568 }
569
570 ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
571 }
572
573 return ret;
574 }
575
576 /* Count is in halfwords */
577 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
578 uint32_t offset, uint32_t count)
579 {
580 struct target *target = bank->target;
581 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
582 uint32_t buffer_size = 16384;
583 struct working_area *write_algorithm;
584 struct working_area *source;
585 uint32_t address = bank->base + offset;
586 struct reg_param reg_params[5];
587 struct armv7m_algorithm armv7m_info;
588 int retval = ERROR_OK;
589
590 static const uint8_t stm32l4_flash_write_code[] = {
591 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
592 };
593
594 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
595 &write_algorithm) != ERROR_OK) {
596 LOG_WARNING("no working area available, can't do block memory writes");
597 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
598 }
599
600 retval = target_write_buffer(target, write_algorithm->address,
601 sizeof(stm32l4_flash_write_code),
602 stm32l4_flash_write_code);
603 if (retval != ERROR_OK) {
604 target_free_working_area(target, write_algorithm);
605 return retval;
606 }
607
608 /* memory buffer */
609 while (target_alloc_working_area_try(target, buffer_size, &source) !=
610 ERROR_OK) {
611 buffer_size /= 2;
612 if (buffer_size <= 256) {
613 /* we already allocated the writing code, but failed to get a
614 * buffer, free the algorithm */
615 target_free_working_area(target, write_algorithm);
616
617 LOG_WARNING("large enough working area not available, can't do block memory writes");
618 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
619 }
620 }
621
622 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
623 armv7m_info.core_mode = ARM_MODE_THREAD;
624
625 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
626 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
627 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
628 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
629 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* flash base */
630
631 buf_set_u32(reg_params[0].value, 0, 32, source->address);
632 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
633 buf_set_u32(reg_params[2].value, 0, 32, address);
634 buf_set_u32(reg_params[3].value, 0, 32, count / 4);
635 buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base);
636
637 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
638 0, NULL,
639 5, reg_params,
640 source->address, source->size,
641 write_algorithm->address, 0,
642 &armv7m_info);
643
644 if (retval == ERROR_FLASH_OPERATION_FAILED) {
645 LOG_ERROR("error executing stm32l4 flash write algorithm");
646
647 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
648
649 if (error & FLASH_WRPERR)
650 LOG_ERROR("flash memory write protected");
651
652 if (error != 0) {
653 LOG_ERROR("flash write failed = %08" PRIx32, error);
654 /* Clear but report errors */
655 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, error);
656 retval = ERROR_FAIL;
657 }
658 }
659
660 target_free_working_area(target, source);
661 target_free_working_area(target, write_algorithm);
662
663 destroy_reg_param(&reg_params[0]);
664 destroy_reg_param(&reg_params[1]);
665 destroy_reg_param(&reg_params[2]);
666 destroy_reg_param(&reg_params[3]);
667 destroy_reg_param(&reg_params[4]);
668
669 return retval;
670 }
671
672 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
673 uint32_t offset, uint32_t count)
674 {
675 int retval;
676
677 if (bank->target->state != TARGET_HALTED) {
678 LOG_ERROR("Target not halted");
679 return ERROR_TARGET_NOT_HALTED;
680 }
681
682 if (offset & 0x7) {
683 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment",
684 offset);
685 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
686 }
687
688 if (count & 0x7) {
689 LOG_WARNING("Padding %d bytes to keep 8-byte write size",
690 count & 7);
691 count = (count + 7) & ~7;
692 /* This pads the write chunk with random bytes by overrunning the
693 * write buffer. Padding with the erased pattern 0xff is purely
694 * cosmetical, as 8-byte flash words are ECC secured and the first
695 * write will program the ECC bits. A second write would need
696 * to reprogramm these ECC bits.
697 * But this can only be done after erase!
698 */
699 }
700
701 retval = stm32l4_unlock_reg(bank);
702 if (retval != ERROR_OK)
703 return retval;
704
705 /* Only full double words (8-byte) can be programmed*/
706 retval = stm32l4_write_block(bank, buffer, offset, count / 2);
707 if (retval != ERROR_OK) {
708 LOG_WARNING("block write failed");
709 return retval;
710 }
711
712 LOG_WARNING("block write succeeded");
713 return stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
714 }
715
716 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
717 {
718 int retval = target_read_u32(bank->target, DBGMCU_IDCODE, id);
719 if (retval != ERROR_OK)
720 return retval;
721
722 return retval;
723 }
724
725 static int stm32l4_probe(struct flash_bank *bank)
726 {
727 struct target *target = bank->target;
728 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
729 const struct stm32l4_part_info *part_info;
730 int i;
731 uint16_t flash_size_in_kb = 0xffff;
732 uint32_t device_id;
733 uint32_t options;
734
735 stm32l4_info->probed = 0;
736
737 /* read stm32 device id register */
738 int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
739 if (retval != ERROR_OK)
740 return retval;
741
742 device_id = stm32l4_info->idcode & 0xFFF;
743
744 for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
745 if (device_id == stm32l4_parts[n].id)
746 stm32l4_info->part_info = &stm32l4_parts[n];
747 }
748
749 if (!stm32l4_info->part_info) {
750 LOG_WARNING("Cannot identify target as an STM32 L4 or WB family device.");
751 return ERROR_FAIL;
752 }
753
754 part_info = stm32l4_info->part_info;
755
756 char device_info[1024];
757 retval = bank->driver->info(bank, device_info, sizeof(device_info));
758 if (retval != ERROR_OK)
759 return retval;
760
761 LOG_INFO("device idcode = 0x%08" PRIx32 " (%s)", stm32l4_info->idcode, device_info);
762
763 /* get flash size from target. */
764 retval = target_read_u16(target, part_info->fsize_addr, &flash_size_in_kb);
765
766 /* failed reading flash size or flash size invalid (early silicon),
767 * default to max target family */
768 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0
769 || flash_size_in_kb > part_info->max_flash_size_kb) {
770 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
771 part_info->max_flash_size_kb);
772 flash_size_in_kb = part_info->max_flash_size_kb;
773 }
774
775 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
776
777 /* did we assign a flash size? */
778 assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
779
780 /* read flash option register */
781 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options);
782 if (retval != ERROR_OK)
783 return retval;
784
785 stm32l4_info->bank1_sectors = 0;
786 stm32l4_info->hole_sectors = 0;
787
788 int num_pages = 0;
789 int page_size = 0;
790
791 stm32l4_info->dual_bank_mode = false;
792
793 switch (device_id) {
794 case 0x415:
795 case 0x461:
796 /* if flash size is max (1M) the device is always dual bank
797 * 0x415: has variants with 512K
798 * 0x461: has variants with 512 and 256
799 * for these variants:
800 * if DUAL_BANK = 0 -> single bank
801 * else -> dual bank without gap
802 * note: the page size is invariant
803 */
804 page_size = 2048;
805 num_pages = flash_size_in_kb / 2;
806 stm32l4_info->bank1_sectors = num_pages;
807
808 /* check DUAL_BANK bit[21] if the flash is less than 1M */
809 if (flash_size_in_kb == 1024 || (options & BIT(21))) {
810 stm32l4_info->dual_bank_mode = true;
811 stm32l4_info->bank1_sectors = num_pages / 2;
812 }
813 break;
814 case 0x435:
815 case 0x462:
816 case 0x464:
817 /* single bank flash */
818 page_size = 2048;
819 num_pages = flash_size_in_kb / 2;
820 stm32l4_info->bank1_sectors = num_pages;
821 break;
822 case 0x470:
823 case 0x471:
824 /* STM32L4R/S can be single/dual bank:
825 * if size = 2M check DBANK bit(22)
826 * if size = 1M check DB1M bit(21)
827 * STM32L4P/Q can be single/dual bank
828 * if size = 1M check DBANK bit(22)
829 * if size = 512K check DB512K bit(21)
830 * in single bank configuration the page size is 8K
831 * else (dual bank) the page size is 4K without gap between banks
832 */
833 page_size = 8192;
834 num_pages = flash_size_in_kb / 8;
835 stm32l4_info->bank1_sectors = num_pages;
836 const bool use_dbank_bit = flash_size_in_kb == part_info->max_flash_size_kb;
837 if ((use_dbank_bit && (options & BIT(22))) ||
838 (!use_dbank_bit && (options & BIT(21)))) {
839 stm32l4_info->dual_bank_mode = true;
840 page_size = 4096;
841 num_pages = flash_size_in_kb / 4;
842 stm32l4_info->bank1_sectors = num_pages / 2;
843 }
844 break;
845 case 0x495:
846 /* single bank flash */
847 page_size = 4096;
848 num_pages = flash_size_in_kb / 4;
849 stm32l4_info->bank1_sectors = num_pages;
850 break;
851 default:
852 LOG_ERROR("unsupported device");
853 return ERROR_FAIL;
854 }
855
856 LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
857
858 const int gap_size = stm32l4_info->hole_sectors * page_size;
859
860 if (stm32l4_info->dual_bank_mode & gap_size) {
861 LOG_INFO("gap detected starting from %0x08" PRIx32 " to %0x08" PRIx32,
862 0x8000000 + stm32l4_info->bank1_sectors * page_size,
863 0x8000000 + stm32l4_info->bank1_sectors * page_size + gap_size);
864 }
865
866 if (bank->sectors) {
867 free(bank->sectors);
868 bank->sectors = NULL;
869 }
870
871 bank->size = flash_size_in_kb * 1024 + gap_size;
872 bank->base = 0x08000000;
873 bank->num_sectors = num_pages;
874 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
875 if (bank->sectors == NULL) {
876 LOG_ERROR("failed to allocate bank sectors");
877 return ERROR_FAIL;
878 }
879
880 for (i = 0; i < bank->num_sectors; i++) {
881 bank->sectors[i].offset = i * page_size;
882 /* in dual bank configuration, if there is a gap between banks
883 * we fix up the sector offset to consider this gap */
884 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
885 bank->sectors[i].offset += gap_size;
886 bank->sectors[i].size = page_size;
887 bank->sectors[i].is_erased = -1;
888 bank->sectors[i].is_protected = 1;
889 }
890
891 stm32l4_info->probed = 1;
892 return ERROR_OK;
893 }
894
895 static int stm32l4_auto_probe(struct flash_bank *bank)
896 {
897 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
898 if (stm32l4_info->probed)
899 return ERROR_OK;
900
901 return stm32l4_probe(bank);
902 }
903
904 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
905 {
906 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
907 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
908
909 if (part_info) {
910 const char *rev_str = NULL;
911 uint16_t rev_id = stm32l4_info->idcode >> 16;
912 for (unsigned int i = 0; i < part_info->num_revs; i++) {
913 if (rev_id == part_info->revs[i].rev) {
914 rev_str = part_info->revs[i].str;
915
916 if (rev_str != NULL) {
917 snprintf(buf, buf_size, "%s - Rev: %s",
918 part_info->device_str, rev_str);
919 return ERROR_OK;
920 }
921 }
922 }
923
924 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)",
925 part_info->device_str, rev_id);
926 return ERROR_OK;
927 } else {
928 snprintf(buf, buf_size, "Cannot identify target as an STM32 L4 or WB device");
929 return ERROR_FAIL;
930 }
931
932 return ERROR_OK;
933 }
934
935 static int stm32l4_mass_erase(struct flash_bank *bank)
936 {
937 int retval;
938 struct target *target = bank->target;
939 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
940
941 uint32_t action = FLASH_MER1;
942
943 if (stm32l4_info->part_info->has_dual_bank)
944 action |= FLASH_MER2;
945
946 if (target->state != TARGET_HALTED) {
947 LOG_ERROR("Target not halted");
948 return ERROR_TARGET_NOT_HALTED;
949 }
950
951 retval = stm32l4_unlock_reg(bank);
952 if (retval != ERROR_OK)
953 return retval;
954
955 /* mass erase flash memory */
956 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
957 if (retval != ERROR_OK)
958 return retval;
959
960 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action);
961 if (retval != ERROR_OK)
962 return retval;
963 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action | FLASH_STRT);
964 if (retval != ERROR_OK)
965 return retval;
966
967 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
968 if (retval != ERROR_OK)
969 return retval;
970
971 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
972 if (retval != ERROR_OK)
973 return retval;
974
975 return ERROR_OK;
976 }
977
978 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
979 {
980 int i;
981
982 if (CMD_ARGC < 1) {
983 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
984 return ERROR_COMMAND_SYNTAX_ERROR;
985 }
986
987 struct flash_bank *bank;
988 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
989 if (ERROR_OK != retval)
990 return retval;
991
992 retval = stm32l4_mass_erase(bank);
993 if (retval == ERROR_OK) {
994 /* set all sectors as erased */
995 for (i = 0; i < bank->num_sectors; i++)
996 bank->sectors[i].is_erased = 1;
997
998 command_print(CMD, "stm32l4x mass erase complete");
999 } else {
1000 command_print(CMD, "stm32l4x mass erase failed");
1001 }
1002
1003 return retval;
1004 }
1005
1006 COMMAND_HANDLER(stm32l4_handle_option_read_command)
1007 {
1008 if (CMD_ARGC < 2) {
1009 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
1010 return ERROR_COMMAND_SYNTAX_ERROR;
1011 }
1012
1013 struct flash_bank *bank;
1014 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1015 if (ERROR_OK != retval)
1016 return retval;
1017
1018 uint32_t reg_offset, reg_addr;
1019 uint32_t value = 0;
1020
1021 reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
1022 reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
1023
1024 retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
1025 if (ERROR_OK != retval)
1026 return retval;
1027
1028 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
1029
1030 return retval;
1031 }
1032
1033 COMMAND_HANDLER(stm32l4_handle_option_write_command)
1034 {
1035 if (CMD_ARGC < 3) {
1036 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
1037 return ERROR_COMMAND_SYNTAX_ERROR;
1038 }
1039
1040 struct flash_bank *bank;
1041 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1042 if (ERROR_OK != retval)
1043 return retval;
1044
1045 uint32_t reg_offset;
1046 uint32_t value = 0;
1047 uint32_t mask = 0xFFFFFFFF;
1048
1049 reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
1050 value = strtoul(CMD_ARGV[2], NULL, 16);
1051 if (CMD_ARGC > 3)
1052 mask = strtoul(CMD_ARGV[3], NULL, 16);
1053
1054 command_print(CMD, "%s Option written.\n"
1055 "INFO: a reset or power cycle is required "
1056 "for the new settings to take effect.", bank->driver->name);
1057
1058 retval = stm32l4_write_option(bank, reg_offset, value, mask);
1059 return retval;
1060 }
1061
1062 COMMAND_HANDLER(stm32l4_handle_option_load_command)
1063 {
1064 if (CMD_ARGC < 1)
1065 return ERROR_COMMAND_SYNTAX_ERROR;
1066
1067 struct flash_bank *bank;
1068 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1069 if (ERROR_OK != retval)
1070 return retval;
1071
1072 retval = stm32l4_unlock_reg(bank);
1073 if (ERROR_OK != retval)
1074 return retval;
1075
1076 retval = stm32l4_unlock_option_reg(bank);
1077 if (ERROR_OK != retval)
1078 return retval;
1079
1080 /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
1081 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBLLAUNCH);
1082
1083 command_print(CMD, "stm32l4x option load (POR) completed.");
1084 return retval;
1085 }
1086
1087 COMMAND_HANDLER(stm32l4_handle_lock_command)
1088 {
1089 struct target *target = NULL;
1090
1091 if (CMD_ARGC < 1)
1092 return ERROR_COMMAND_SYNTAX_ERROR;
1093
1094 struct flash_bank *bank;
1095 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1096 if (ERROR_OK != retval)
1097 return retval;
1098
1099 target = bank->target;
1100
1101 if (target->state != TARGET_HALTED) {
1102 LOG_ERROR("Target not halted");
1103 return ERROR_TARGET_NOT_HALTED;
1104 }
1105
1106 /* set readout protection level 1 by erasing the RDP option byte */
1107 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
1108 command_print(CMD, "%s failed to lock device", bank->driver->name);
1109 return ERROR_OK;
1110 }
1111
1112 return ERROR_OK;
1113 }
1114
1115 COMMAND_HANDLER(stm32l4_handle_unlock_command)
1116 {
1117 struct target *target = NULL;
1118
1119 if (CMD_ARGC < 1)
1120 return ERROR_COMMAND_SYNTAX_ERROR;
1121
1122 struct flash_bank *bank;
1123 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1124 if (ERROR_OK != retval)
1125 return retval;
1126
1127 target = bank->target;
1128
1129 if (target->state != TARGET_HALTED) {
1130 LOG_ERROR("Target not halted");
1131 return ERROR_TARGET_NOT_HALTED;
1132 }
1133
1134 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
1135 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1136 return ERROR_OK;
1137 }
1138
1139 return ERROR_OK;
1140 }
1141
1142 static const struct command_registration stm32l4_exec_command_handlers[] = {
1143 {
1144 .name = "lock",
1145 .handler = stm32l4_handle_lock_command,
1146 .mode = COMMAND_EXEC,
1147 .usage = "bank_id",
1148 .help = "Lock entire flash device.",
1149 },
1150 {
1151 .name = "unlock",
1152 .handler = stm32l4_handle_unlock_command,
1153 .mode = COMMAND_EXEC,
1154 .usage = "bank_id",
1155 .help = "Unlock entire protected flash device.",
1156 },
1157 {
1158 .name = "mass_erase",
1159 .handler = stm32l4_handle_mass_erase_command,
1160 .mode = COMMAND_EXEC,
1161 .usage = "bank_id",
1162 .help = "Erase entire flash device.",
1163 },
1164 {
1165 .name = "option_read",
1166 .handler = stm32l4_handle_option_read_command,
1167 .mode = COMMAND_EXEC,
1168 .usage = "bank_id reg_offset",
1169 .help = "Read & Display device option bytes.",
1170 },
1171 {
1172 .name = "option_write",
1173 .handler = stm32l4_handle_option_write_command,
1174 .mode = COMMAND_EXEC,
1175 .usage = "bank_id reg_offset value mask",
1176 .help = "Write device option bit fields with provided value.",
1177 },
1178 {
1179 .name = "option_load",
1180 .handler = stm32l4_handle_option_load_command,
1181 .mode = COMMAND_EXEC,
1182 .usage = "bank_id",
1183 .help = "Force re-load of device options (will cause device reset).",
1184 },
1185 COMMAND_REGISTRATION_DONE
1186 };
1187
1188 static const struct command_registration stm32l4_command_handlers[] = {
1189 {
1190 .name = "stm32l4x",
1191 .mode = COMMAND_ANY,
1192 .help = "stm32l4x flash command group",
1193 .usage = "",
1194 .chain = stm32l4_exec_command_handlers,
1195 },
1196 COMMAND_REGISTRATION_DONE
1197 };
1198
1199 const struct flash_driver stm32l4x_flash = {
1200 .name = "stm32l4x",
1201 .commands = stm32l4_command_handlers,
1202 .flash_bank_command = stm32l4_flash_bank_command,
1203 .erase = stm32l4_erase,
1204 .protect = stm32l4_protect,
1205 .write = stm32l4_write,
1206 .read = default_flash_read,
1207 .probe = stm32l4_probe,
1208 .auto_probe = stm32l4_auto_probe,
1209 .erase_check = default_flash_blank_check,
1210 .protect_check = stm32l4_protect_check,
1211 .info = get_stm32l4_info,
1212 .free_driver_priv = default_flash_free_driver_priv,
1213 };
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