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[openocd.git] / src / flash / nor / stm32l4x.c
1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
4 * *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "imp.h"
27 #include <helper/binarybuffer.h>
28 #include <target/algorithm.h>
29 #include <target/armv7m.h>
30 #include "bits.h"
31
32 /* STM32L4xxx series for reference.
33 *
34 * RM0351 (STM32L4x5/STM32L4x6)
35 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
36 *
37 * RM0394 (STM32L43x/44x/45x/46x)
38 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
39 *
40 * RM0432 (STM32L4R/4Sxx)
41 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
42 *
43 * STM32L476RG Datasheet (for erase timing)
44 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
45 *
46 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
47 * an option byte is available to map all sectors to the first bank.
48 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
49 * handlers do!
50 *
51 * RM0394 devices have a single bank only.
52 *
53 * RM0432 devices have single and dual bank operating modes.
54 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
55 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
56 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
57 *
58 * Bank mode is controlled by two different bits in option bytes register.
59 * - for STM32L4R/Sxx
60 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
61 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
62 * - for STM32L4P5/Q5x
63 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
64 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
65 *
66 */
67
68 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
69
70 #define FLASH_ERASE_TIMEOUT 250
71
72 /* Flash registers offsets */
73 #define STM32_FLASH_ACR 0x00
74 #define STM32_FLASH_KEYR 0x08
75 #define STM32_FLASH_OPTKEYR 0x0c
76 #define STM32_FLASH_SR 0x10
77 #define STM32_FLASH_CR 0x14
78 #define STM32_FLASH_OPTR 0x20
79 #define STM32_FLASH_WRP1AR 0x2c
80 #define STM32_FLASH_WRP1BR 0x30
81 #define STM32_FLASH_WRP2AR 0x4c
82 #define STM32_FLASH_WRP2BR 0x50
83
84 /* FLASH_CR register bits */
85 #define FLASH_PG (1 << 0)
86 #define FLASH_PER (1 << 1)
87 #define FLASH_MER1 (1 << 2)
88 #define FLASH_PAGE_SHIFT 3
89 #define FLASH_CR_BKER (1 << 11)
90 #define FLASH_MER2 (1 << 15)
91 #define FLASH_STRT (1 << 16)
92 #define FLASH_OPTSTRT (1 << 17)
93 #define FLASH_EOPIE (1 << 24)
94 #define FLASH_ERRIE (1 << 25)
95 #define FLASH_OBLLAUNCH (1 << 27)
96 #define FLASH_OPTLOCK (1 << 30)
97 #define FLASH_LOCK (1 << 31)
98
99 /* FLASH_SR register bits */
100 #define FLASH_BSY (1 << 16)
101 /* Fast programming not used => related errors not used*/
102 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
103 #define FLASH_SIZERR (1 << 6) /* Size error */
104 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
105 #define FLASH_WRPERR (1 << 4) /* Write protection error */
106 #define FLASH_PROGERR (1 << 3) /* Programming error */
107 #define FLASH_OPERR (1 << 1) /* Operation error */
108 #define FLASH_EOP (1 << 0) /* End of operation */
109 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
110
111 /* register unlock keys */
112 #define KEY1 0x45670123
113 #define KEY2 0xCDEF89AB
114
115 /* option register unlock key */
116 #define OPTKEY1 0x08192A3B
117 #define OPTKEY2 0x4C5D6E7F
118
119 #define RDP_LEVEL_0 0xAA
120 #define RDP_LEVEL_1 0xBB
121 #define RDP_LEVEL_2 0xCC
122
123
124 /* other registers */
125 #define DBGMCU_IDCODE 0xE0042000
126
127
128 struct stm32l4_rev {
129 const uint16_t rev;
130 const char *str;
131 };
132
133 struct stm32l4_part_info {
134 uint16_t id;
135 const char *device_str;
136 const struct stm32l4_rev *revs;
137 const size_t num_revs;
138 const uint16_t max_flash_size_kb;
139 const bool has_dual_bank;
140 const uint32_t flash_regs_base;
141 const uint32_t fsize_addr;
142 };
143
144 struct stm32l4_flash_bank {
145 int probed;
146 uint32_t idcode;
147 int bank1_sectors;
148 bool dual_bank_mode;
149 int hole_sectors;
150 const struct stm32l4_part_info *part_info;
151 };
152
153 static const struct stm32l4_rev stm32_415_revs[] = {
154 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
155 };
156
157 static const struct stm32l4_rev stm32_435_revs[] = {
158 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
159 };
160
161 static const struct stm32l4_rev stm32_461_revs[] = {
162 { 0x1000, "A" }, { 0x2000, "B" },
163 };
164
165 static const struct stm32l4_rev stm32_462_revs[] = {
166 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
167 };
168
169 static const struct stm32l4_rev stm32_464_revs[] = {
170 { 0x1000, "A" },
171 };
172
173 static const struct stm32l4_rev stm32_470_revs[] = {
174 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
175 };
176
177 static const struct stm32l4_rev stm32_471_revs[] = {
178 { 0x1000, "1" },
179 };
180
181 static const struct stm32l4_rev stm32_495_revs[] = {
182 { 0x2001, "2.1" },
183 };
184
185 static const struct stm32l4_part_info stm32l4_parts[] = {
186 {
187 .id = 0x415,
188 .revs = stm32_415_revs,
189 .num_revs = ARRAY_SIZE(stm32_415_revs),
190 .device_str = "STM32L47/L48xx",
191 .max_flash_size_kb = 1024,
192 .has_dual_bank = true,
193 .flash_regs_base = 0x40022000,
194 .fsize_addr = 0x1FFF75E0,
195 },
196 {
197 .id = 0x435,
198 .revs = stm32_435_revs,
199 .num_revs = ARRAY_SIZE(stm32_435_revs),
200 .device_str = "STM32L43/L44xx",
201 .max_flash_size_kb = 256,
202 .has_dual_bank = false,
203 .flash_regs_base = 0x40022000,
204 .fsize_addr = 0x1FFF75E0,
205 },
206 {
207 .id = 0x461,
208 .revs = stm32_461_revs,
209 .num_revs = ARRAY_SIZE(stm32_461_revs),
210 .device_str = "STM32L49/L4Axx",
211 .max_flash_size_kb = 1024,
212 .has_dual_bank = true,
213 .flash_regs_base = 0x40022000,
214 .fsize_addr = 0x1FFF75E0,
215 },
216 {
217 .id = 0x462,
218 .revs = stm32_462_revs,
219 .num_revs = ARRAY_SIZE(stm32_462_revs),
220 .device_str = "STM32L45/L46xx",
221 .max_flash_size_kb = 512,
222 .has_dual_bank = false,
223 .flash_regs_base = 0x40022000,
224 .fsize_addr = 0x1FFF75E0,
225 },
226 {
227 .id = 0x464,
228 .revs = stm32_464_revs,
229 .num_revs = ARRAY_SIZE(stm32_464_revs),
230 .device_str = "STM32L41/L42xx",
231 .max_flash_size_kb = 128,
232 .has_dual_bank = false,
233 .flash_regs_base = 0x40022000,
234 .fsize_addr = 0x1FFF75E0,
235 },
236 {
237 .id = 0x470,
238 .revs = stm32_470_revs,
239 .num_revs = ARRAY_SIZE(stm32_470_revs),
240 .device_str = "STM32L4R/L4Sxx",
241 .max_flash_size_kb = 2048,
242 .has_dual_bank = true,
243 .flash_regs_base = 0x40022000,
244 .fsize_addr = 0x1FFF75E0,
245 },
246 {
247 .id = 0x471,
248 .revs = stm32_471_revs,
249 .num_revs = ARRAY_SIZE(stm32_471_revs),
250 .device_str = "STM32L4P5/L4Q5x",
251 .max_flash_size_kb = 1024,
252 .has_dual_bank = true,
253 .flash_regs_base = 0x40022000,
254 .fsize_addr = 0x1FFF75E0,
255 },
256 {
257 .id = 0x495,
258 .revs = stm32_495_revs,
259 .num_revs = ARRAY_SIZE(stm32_495_revs),
260 .device_str = "STM32WB5x",
261 .max_flash_size_kb = 1024,
262 .has_dual_bank = false,
263 .flash_regs_base = 0x58004000,
264 .fsize_addr = 0x1FFF75E0,
265 },
266 };
267
268 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
269 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
270 {
271 struct stm32l4_flash_bank *stm32l4_info;
272
273 if (CMD_ARGC < 6)
274 return ERROR_COMMAND_SYNTAX_ERROR;
275
276 stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
277 if (!stm32l4_info)
278 return ERROR_FAIL; /* Checkme: What better error to use?*/
279 bank->driver_priv = stm32l4_info;
280
281 /* The flash write must be aligned to a double word (8-bytes) boundary.
282 * Ask the flash infrastructure to ensure required alignment */
283 bank->write_start_alignment = bank->write_end_alignment = 8;
284
285 stm32l4_info->probed = 0;
286
287 return ERROR_OK;
288 }
289
290 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
291 {
292 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
293 return stm32l4_info->part_info->flash_regs_base + reg_offset;
294 }
295
296 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
297 {
298 return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
299 }
300
301 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
302 {
303 return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
304 }
305
306 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
307 {
308 uint32_t status;
309 int retval = ERROR_OK;
310
311 /* wait for busy to clear */
312 for (;;) {
313 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_SR, &status);
314 if (retval != ERROR_OK)
315 return retval;
316 LOG_DEBUG("status: 0x%" PRIx32 "", status);
317 if ((status & FLASH_BSY) == 0)
318 break;
319 if (timeout-- <= 0) {
320 LOG_ERROR("timed out waiting for flash");
321 return ERROR_FAIL;
322 }
323 alive_sleep(1);
324 }
325
326
327 if (status & FLASH_WRPERR) {
328 LOG_ERROR("stm32x device protected");
329 retval = ERROR_FAIL;
330 }
331
332 /* Clear but report errors */
333 if (status & FLASH_ERROR) {
334 if (retval == ERROR_OK)
335 retval = ERROR_FAIL;
336 /* If this operation fails, we ignore it and report the original
337 * retval
338 */
339 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, status & FLASH_ERROR);
340 }
341
342 return retval;
343 }
344
345 static int stm32l4_unlock_reg(struct flash_bank *bank)
346 {
347 uint32_t ctrl;
348
349 /* first check if not already unlocked
350 * otherwise writing on STM32_FLASH_KEYR will fail
351 */
352 int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
353 if (retval != ERROR_OK)
354 return retval;
355
356 if ((ctrl & FLASH_LOCK) == 0)
357 return ERROR_OK;
358
359 /* unlock flash registers */
360 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY1);
361 if (retval != ERROR_OK)
362 return retval;
363
364 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY2);
365 if (retval != ERROR_OK)
366 return retval;
367
368 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
369 if (retval != ERROR_OK)
370 return retval;
371
372 if (ctrl & FLASH_LOCK) {
373 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
374 return ERROR_TARGET_FAILURE;
375 }
376
377 return ERROR_OK;
378 }
379
380 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
381 {
382 uint32_t ctrl;
383
384 int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
385 if (retval != ERROR_OK)
386 return retval;
387
388 if ((ctrl & FLASH_OPTLOCK) == 0)
389 return ERROR_OK;
390
391 /* unlock option registers */
392 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY1);
393 if (retval != ERROR_OK)
394 return retval;
395
396 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY2);
397 if (retval != ERROR_OK)
398 return retval;
399
400 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
401 if (retval != ERROR_OK)
402 return retval;
403
404 if (ctrl & FLASH_OPTLOCK) {
405 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
406 return ERROR_TARGET_FAILURE;
407 }
408
409 return ERROR_OK;
410 }
411
412 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
413 {
414 uint32_t optiondata;
415
416 int retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
417 if (retval != ERROR_OK)
418 return retval;
419
420 retval = stm32l4_unlock_reg(bank);
421 if (retval != ERROR_OK)
422 return retval;
423
424 retval = stm32l4_unlock_option_reg(bank);
425 if (retval != ERROR_OK)
426 return retval;
427
428 optiondata = (optiondata & ~mask) | (value & mask);
429
430 retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
431 if (retval != ERROR_OK)
432 return retval;
433
434 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OPTSTRT);
435 if (retval != ERROR_OK)
436 return retval;
437
438 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
439 if (retval != ERROR_OK)
440 return retval;
441
442 return retval;
443 }
444
445 static int stm32l4_protect_check(struct flash_bank *bank)
446 {
447 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
448
449 uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
450 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar);
451 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br);
452 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
453 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
454
455 const uint8_t wrp1a_start = wrp1ar & 0xFF;
456 const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
457 const uint8_t wrp1b_start = wrp1br & 0xFF;
458 const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
459 const uint8_t wrp2a_start = wrp2ar & 0xFF;
460 const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
461 const uint8_t wrp2b_start = wrp2br & 0xFF;
462 const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
463
464 for (int i = 0; i < bank->num_sectors; i++) {
465 if (i < stm32l4_info->bank1_sectors) {
466 if (((i >= wrp1a_start) &&
467 (i <= wrp1a_end)) ||
468 ((i >= wrp1b_start) &&
469 (i <= wrp1b_end)))
470 bank->sectors[i].is_protected = 1;
471 else
472 bank->sectors[i].is_protected = 0;
473 } else {
474 uint8_t snb;
475 snb = i - stm32l4_info->bank1_sectors;
476 if (((snb >= wrp2a_start) &&
477 (snb <= wrp2a_end)) ||
478 ((snb >= wrp2b_start) &&
479 (snb <= wrp2b_end)))
480 bank->sectors[i].is_protected = 1;
481 else
482 bank->sectors[i].is_protected = 0;
483 }
484 }
485 return ERROR_OK;
486 }
487
488 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
489 {
490 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
491 int i;
492 int retval;
493
494 assert(first < bank->num_sectors);
495 assert(last < bank->num_sectors);
496
497 if (bank->target->state != TARGET_HALTED) {
498 LOG_ERROR("Target not halted");
499 return ERROR_TARGET_NOT_HALTED;
500 }
501
502 retval = stm32l4_unlock_reg(bank);
503 if (retval != ERROR_OK)
504 return retval;
505
506 /*
507 Sector Erase
508 To erase a sector, follow the procedure below:
509 1. Check that no Flash memory operation is ongoing by
510 checking the BSY bit in the FLASH_SR register
511 2. Set the PER bit and select the page and bank
512 you wish to erase in the FLASH_CR register
513 3. Set the STRT bit in the FLASH_CR register
514 4. Wait for the BSY bit to be cleared
515 */
516
517 for (i = first; i <= last; i++) {
518 uint32_t erase_flags;
519 erase_flags = FLASH_PER | FLASH_STRT;
520
521 if (i >= stm32l4_info->bank1_sectors) {
522 uint8_t snb;
523 snb = i - stm32l4_info->bank1_sectors;
524 erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
525 } else
526 erase_flags |= i << FLASH_PAGE_SHIFT;
527 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, erase_flags);
528 if (retval != ERROR_OK)
529 return retval;
530
531 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
532 if (retval != ERROR_OK)
533 return retval;
534
535 bank->sectors[i].is_erased = 1;
536 }
537
538 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
539 if (retval != ERROR_OK)
540 return retval;
541
542 return ERROR_OK;
543 }
544
545 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
546 {
547 struct target *target = bank->target;
548 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
549
550 if (target->state != TARGET_HALTED) {
551 LOG_ERROR("Target not halted");
552 return ERROR_TARGET_NOT_HALTED;
553 }
554
555 int ret = ERROR_OK;
556 /* Bank 2 */
557 uint32_t reg_value = 0xFF; /* Default to bank un-protected */
558 if (last >= stm32l4_info->bank1_sectors) {
559 if (set == 1) {
560 uint8_t begin = first > stm32l4_info->bank1_sectors ? first : 0x00;
561 reg_value = ((last & 0xFF) << 16) | begin;
562 }
563
564 ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
565 }
566 /* Bank 1 */
567 reg_value = 0xFF; /* Default to bank un-protected */
568 if (first < stm32l4_info->bank1_sectors) {
569 if (set == 1) {
570 uint8_t end = last >= stm32l4_info->bank1_sectors ? 0xFF : last;
571 reg_value = (end << 16) | (first & 0xFF);
572 }
573
574 ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
575 }
576
577 return ret;
578 }
579
580 /* Count is in halfwords */
581 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
582 uint32_t offset, uint32_t count)
583 {
584 struct target *target = bank->target;
585 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
586 uint32_t buffer_size = 16384;
587 struct working_area *write_algorithm;
588 struct working_area *source;
589 uint32_t address = bank->base + offset;
590 struct reg_param reg_params[5];
591 struct armv7m_algorithm armv7m_info;
592 int retval = ERROR_OK;
593
594 static const uint8_t stm32l4_flash_write_code[] = {
595 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
596 };
597
598 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
599 &write_algorithm) != ERROR_OK) {
600 LOG_WARNING("no working area available, can't do block memory writes");
601 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
602 }
603
604 retval = target_write_buffer(target, write_algorithm->address,
605 sizeof(stm32l4_flash_write_code),
606 stm32l4_flash_write_code);
607 if (retval != ERROR_OK) {
608 target_free_working_area(target, write_algorithm);
609 return retval;
610 }
611
612 /* memory buffer */
613 while (target_alloc_working_area_try(target, buffer_size, &source) !=
614 ERROR_OK) {
615 buffer_size /= 2;
616 if (buffer_size <= 256) {
617 /* we already allocated the writing code, but failed to get a
618 * buffer, free the algorithm */
619 target_free_working_area(target, write_algorithm);
620
621 LOG_WARNING("large enough working area not available, can't do block memory writes");
622 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
623 }
624 }
625
626 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
627 armv7m_info.core_mode = ARM_MODE_THREAD;
628
629 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
630 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
631 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
632 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
633 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* flash base */
634
635 buf_set_u32(reg_params[0].value, 0, 32, source->address);
636 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
637 buf_set_u32(reg_params[2].value, 0, 32, address);
638 buf_set_u32(reg_params[3].value, 0, 32, count / 4);
639 buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base);
640
641 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
642 0, NULL,
643 5, reg_params,
644 source->address, source->size,
645 write_algorithm->address, 0,
646 &armv7m_info);
647
648 if (retval == ERROR_FLASH_OPERATION_FAILED) {
649 LOG_ERROR("error executing stm32l4 flash write algorithm");
650
651 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
652
653 if (error & FLASH_WRPERR)
654 LOG_ERROR("flash memory write protected");
655
656 if (error != 0) {
657 LOG_ERROR("flash write failed = %08" PRIx32, error);
658 /* Clear but report errors */
659 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, error);
660 retval = ERROR_FAIL;
661 }
662 }
663
664 target_free_working_area(target, source);
665 target_free_working_area(target, write_algorithm);
666
667 destroy_reg_param(&reg_params[0]);
668 destroy_reg_param(&reg_params[1]);
669 destroy_reg_param(&reg_params[2]);
670 destroy_reg_param(&reg_params[3]);
671 destroy_reg_param(&reg_params[4]);
672
673 return retval;
674 }
675
676 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
677 uint32_t offset, uint32_t count)
678 {
679 int retval;
680
681 if (bank->target->state != TARGET_HALTED) {
682 LOG_ERROR("Target not halted");
683 return ERROR_TARGET_NOT_HALTED;
684 }
685
686 /* The flash write must be aligned to a double word (8-bytes) boundary.
687 * The flash infrastructure ensures it, do just a security check */
688 assert(offset % 8 == 0);
689 assert(count % 8 == 0);
690
691 retval = stm32l4_unlock_reg(bank);
692 if (retval != ERROR_OK)
693 return retval;
694
695 retval = stm32l4_write_block(bank, buffer, offset, count / 2);
696 if (retval != ERROR_OK) {
697 LOG_WARNING("block write failed");
698 return retval;
699 }
700
701 LOG_WARNING("block write succeeded");
702 return stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
703 }
704
705 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
706 {
707 int retval = target_read_u32(bank->target, DBGMCU_IDCODE, id);
708 if (retval != ERROR_OK)
709 return retval;
710
711 return retval;
712 }
713
714 static int stm32l4_probe(struct flash_bank *bank)
715 {
716 struct target *target = bank->target;
717 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
718 const struct stm32l4_part_info *part_info;
719 int i;
720 uint16_t flash_size_in_kb = 0xffff;
721 uint32_t device_id;
722 uint32_t options;
723
724 stm32l4_info->probed = 0;
725
726 /* read stm32 device id register */
727 int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
728 if (retval != ERROR_OK)
729 return retval;
730
731 device_id = stm32l4_info->idcode & 0xFFF;
732
733 for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
734 if (device_id == stm32l4_parts[n].id)
735 stm32l4_info->part_info = &stm32l4_parts[n];
736 }
737
738 if (!stm32l4_info->part_info) {
739 LOG_WARNING("Cannot identify target as an STM32 L4 or WB family device.");
740 return ERROR_FAIL;
741 }
742
743 part_info = stm32l4_info->part_info;
744
745 char device_info[1024];
746 retval = bank->driver->info(bank, device_info, sizeof(device_info));
747 if (retval != ERROR_OK)
748 return retval;
749
750 LOG_INFO("device idcode = 0x%08" PRIx32 " (%s)", stm32l4_info->idcode, device_info);
751
752 /* get flash size from target. */
753 retval = target_read_u16(target, part_info->fsize_addr, &flash_size_in_kb);
754
755 /* failed reading flash size or flash size invalid (early silicon),
756 * default to max target family */
757 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0
758 || flash_size_in_kb > part_info->max_flash_size_kb) {
759 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
760 part_info->max_flash_size_kb);
761 flash_size_in_kb = part_info->max_flash_size_kb;
762 }
763
764 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
765
766 /* did we assign a flash size? */
767 assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
768
769 /* read flash option register */
770 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options);
771 if (retval != ERROR_OK)
772 return retval;
773
774 stm32l4_info->bank1_sectors = 0;
775 stm32l4_info->hole_sectors = 0;
776
777 int num_pages = 0;
778 int page_size = 0;
779
780 stm32l4_info->dual_bank_mode = false;
781
782 switch (device_id) {
783 case 0x415:
784 case 0x461:
785 /* if flash size is max (1M) the device is always dual bank
786 * 0x415: has variants with 512K
787 * 0x461: has variants with 512 and 256
788 * for these variants:
789 * if DUAL_BANK = 0 -> single bank
790 * else -> dual bank without gap
791 * note: the page size is invariant
792 */
793 page_size = 2048;
794 num_pages = flash_size_in_kb / 2;
795 stm32l4_info->bank1_sectors = num_pages;
796
797 /* check DUAL_BANK bit[21] if the flash is less than 1M */
798 if (flash_size_in_kb == 1024 || (options & BIT(21))) {
799 stm32l4_info->dual_bank_mode = true;
800 stm32l4_info->bank1_sectors = num_pages / 2;
801 }
802 break;
803 case 0x435:
804 case 0x462:
805 case 0x464:
806 /* single bank flash */
807 page_size = 2048;
808 num_pages = flash_size_in_kb / 2;
809 stm32l4_info->bank1_sectors = num_pages;
810 break;
811 case 0x470:
812 case 0x471:
813 /* STM32L4R/S can be single/dual bank:
814 * if size = 2M check DBANK bit(22)
815 * if size = 1M check DB1M bit(21)
816 * STM32L4P/Q can be single/dual bank
817 * if size = 1M check DBANK bit(22)
818 * if size = 512K check DB512K bit(21)
819 * in single bank configuration the page size is 8K
820 * else (dual bank) the page size is 4K without gap between banks
821 */
822 page_size = 8192;
823 num_pages = flash_size_in_kb / 8;
824 stm32l4_info->bank1_sectors = num_pages;
825 const bool use_dbank_bit = flash_size_in_kb == part_info->max_flash_size_kb;
826 if ((use_dbank_bit && (options & BIT(22))) ||
827 (!use_dbank_bit && (options & BIT(21)))) {
828 stm32l4_info->dual_bank_mode = true;
829 page_size = 4096;
830 num_pages = flash_size_in_kb / 4;
831 stm32l4_info->bank1_sectors = num_pages / 2;
832 }
833 break;
834 case 0x495:
835 /* single bank flash */
836 page_size = 4096;
837 num_pages = flash_size_in_kb / 4;
838 stm32l4_info->bank1_sectors = num_pages;
839 break;
840 default:
841 LOG_ERROR("unsupported device");
842 return ERROR_FAIL;
843 }
844
845 LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
846
847 const int gap_size = stm32l4_info->hole_sectors * page_size;
848
849 if (stm32l4_info->dual_bank_mode & gap_size) {
850 LOG_INFO("gap detected starting from %0x08" PRIx32 " to %0x08" PRIx32,
851 0x8000000 + stm32l4_info->bank1_sectors * page_size,
852 0x8000000 + stm32l4_info->bank1_sectors * page_size + gap_size);
853 }
854
855 if (bank->sectors) {
856 free(bank->sectors);
857 bank->sectors = NULL;
858 }
859
860 bank->size = flash_size_in_kb * 1024 + gap_size;
861 bank->base = 0x08000000;
862 bank->num_sectors = num_pages;
863 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
864 if (bank->sectors == NULL) {
865 LOG_ERROR("failed to allocate bank sectors");
866 return ERROR_FAIL;
867 }
868
869 for (i = 0; i < bank->num_sectors; i++) {
870 bank->sectors[i].offset = i * page_size;
871 /* in dual bank configuration, if there is a gap between banks
872 * we fix up the sector offset to consider this gap */
873 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
874 bank->sectors[i].offset += gap_size;
875 bank->sectors[i].size = page_size;
876 bank->sectors[i].is_erased = -1;
877 bank->sectors[i].is_protected = 1;
878 }
879
880 stm32l4_info->probed = 1;
881 return ERROR_OK;
882 }
883
884 static int stm32l4_auto_probe(struct flash_bank *bank)
885 {
886 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
887 if (stm32l4_info->probed)
888 return ERROR_OK;
889
890 return stm32l4_probe(bank);
891 }
892
893 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
894 {
895 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
896 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
897
898 if (part_info) {
899 const char *rev_str = NULL;
900 uint16_t rev_id = stm32l4_info->idcode >> 16;
901 for (unsigned int i = 0; i < part_info->num_revs; i++) {
902 if (rev_id == part_info->revs[i].rev) {
903 rev_str = part_info->revs[i].str;
904
905 if (rev_str != NULL) {
906 snprintf(buf, buf_size, "%s - Rev: %s",
907 part_info->device_str, rev_str);
908 return ERROR_OK;
909 }
910 }
911 }
912
913 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)",
914 part_info->device_str, rev_id);
915 return ERROR_OK;
916 } else {
917 snprintf(buf, buf_size, "Cannot identify target as an STM32 L4 or WB device");
918 return ERROR_FAIL;
919 }
920
921 return ERROR_OK;
922 }
923
924 static int stm32l4_mass_erase(struct flash_bank *bank)
925 {
926 int retval;
927 struct target *target = bank->target;
928 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
929
930 uint32_t action = FLASH_MER1;
931
932 if (stm32l4_info->part_info->has_dual_bank)
933 action |= FLASH_MER2;
934
935 if (target->state != TARGET_HALTED) {
936 LOG_ERROR("Target not halted");
937 return ERROR_TARGET_NOT_HALTED;
938 }
939
940 retval = stm32l4_unlock_reg(bank);
941 if (retval != ERROR_OK)
942 return retval;
943
944 /* mass erase flash memory */
945 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
946 if (retval != ERROR_OK)
947 return retval;
948
949 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action);
950 if (retval != ERROR_OK)
951 return retval;
952 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action | FLASH_STRT);
953 if (retval != ERROR_OK)
954 return retval;
955
956 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
957 if (retval != ERROR_OK)
958 return retval;
959
960 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
961 if (retval != ERROR_OK)
962 return retval;
963
964 return ERROR_OK;
965 }
966
967 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
968 {
969 int i;
970
971 if (CMD_ARGC < 1) {
972 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
973 return ERROR_COMMAND_SYNTAX_ERROR;
974 }
975
976 struct flash_bank *bank;
977 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
978 if (ERROR_OK != retval)
979 return retval;
980
981 retval = stm32l4_mass_erase(bank);
982 if (retval == ERROR_OK) {
983 /* set all sectors as erased */
984 for (i = 0; i < bank->num_sectors; i++)
985 bank->sectors[i].is_erased = 1;
986
987 command_print(CMD, "stm32l4x mass erase complete");
988 } else {
989 command_print(CMD, "stm32l4x mass erase failed");
990 }
991
992 return retval;
993 }
994
995 COMMAND_HANDLER(stm32l4_handle_option_read_command)
996 {
997 if (CMD_ARGC < 2) {
998 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
999 return ERROR_COMMAND_SYNTAX_ERROR;
1000 }
1001
1002 struct flash_bank *bank;
1003 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1004 if (ERROR_OK != retval)
1005 return retval;
1006
1007 uint32_t reg_offset, reg_addr;
1008 uint32_t value = 0;
1009
1010 reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
1011 reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
1012
1013 retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
1014 if (ERROR_OK != retval)
1015 return retval;
1016
1017 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
1018
1019 return retval;
1020 }
1021
1022 COMMAND_HANDLER(stm32l4_handle_option_write_command)
1023 {
1024 if (CMD_ARGC < 3) {
1025 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
1026 return ERROR_COMMAND_SYNTAX_ERROR;
1027 }
1028
1029 struct flash_bank *bank;
1030 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1031 if (ERROR_OK != retval)
1032 return retval;
1033
1034 uint32_t reg_offset;
1035 uint32_t value = 0;
1036 uint32_t mask = 0xFFFFFFFF;
1037
1038 reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
1039 value = strtoul(CMD_ARGV[2], NULL, 16);
1040 if (CMD_ARGC > 3)
1041 mask = strtoul(CMD_ARGV[3], NULL, 16);
1042
1043 command_print(CMD, "%s Option written.\n"
1044 "INFO: a reset or power cycle is required "
1045 "for the new settings to take effect.", bank->driver->name);
1046
1047 retval = stm32l4_write_option(bank, reg_offset, value, mask);
1048 return retval;
1049 }
1050
1051 COMMAND_HANDLER(stm32l4_handle_option_load_command)
1052 {
1053 if (CMD_ARGC < 1)
1054 return ERROR_COMMAND_SYNTAX_ERROR;
1055
1056 struct flash_bank *bank;
1057 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1058 if (ERROR_OK != retval)
1059 return retval;
1060
1061 retval = stm32l4_unlock_reg(bank);
1062 if (ERROR_OK != retval)
1063 return retval;
1064
1065 retval = stm32l4_unlock_option_reg(bank);
1066 if (ERROR_OK != retval)
1067 return retval;
1068
1069 /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
1070 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBLLAUNCH);
1071
1072 command_print(CMD, "stm32l4x option load (POR) completed.");
1073 return retval;
1074 }
1075
1076 COMMAND_HANDLER(stm32l4_handle_lock_command)
1077 {
1078 struct target *target = NULL;
1079
1080 if (CMD_ARGC < 1)
1081 return ERROR_COMMAND_SYNTAX_ERROR;
1082
1083 struct flash_bank *bank;
1084 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1085 if (ERROR_OK != retval)
1086 return retval;
1087
1088 target = bank->target;
1089
1090 if (target->state != TARGET_HALTED) {
1091 LOG_ERROR("Target not halted");
1092 return ERROR_TARGET_NOT_HALTED;
1093 }
1094
1095 /* set readout protection level 1 by erasing the RDP option byte */
1096 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
1097 command_print(CMD, "%s failed to lock device", bank->driver->name);
1098 return ERROR_OK;
1099 }
1100
1101 return ERROR_OK;
1102 }
1103
1104 COMMAND_HANDLER(stm32l4_handle_unlock_command)
1105 {
1106 struct target *target = NULL;
1107
1108 if (CMD_ARGC < 1)
1109 return ERROR_COMMAND_SYNTAX_ERROR;
1110
1111 struct flash_bank *bank;
1112 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1113 if (ERROR_OK != retval)
1114 return retval;
1115
1116 target = bank->target;
1117
1118 if (target->state != TARGET_HALTED) {
1119 LOG_ERROR("Target not halted");
1120 return ERROR_TARGET_NOT_HALTED;
1121 }
1122
1123 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
1124 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1125 return ERROR_OK;
1126 }
1127
1128 return ERROR_OK;
1129 }
1130
1131 static const struct command_registration stm32l4_exec_command_handlers[] = {
1132 {
1133 .name = "lock",
1134 .handler = stm32l4_handle_lock_command,
1135 .mode = COMMAND_EXEC,
1136 .usage = "bank_id",
1137 .help = "Lock entire flash device.",
1138 },
1139 {
1140 .name = "unlock",
1141 .handler = stm32l4_handle_unlock_command,
1142 .mode = COMMAND_EXEC,
1143 .usage = "bank_id",
1144 .help = "Unlock entire protected flash device.",
1145 },
1146 {
1147 .name = "mass_erase",
1148 .handler = stm32l4_handle_mass_erase_command,
1149 .mode = COMMAND_EXEC,
1150 .usage = "bank_id",
1151 .help = "Erase entire flash device.",
1152 },
1153 {
1154 .name = "option_read",
1155 .handler = stm32l4_handle_option_read_command,
1156 .mode = COMMAND_EXEC,
1157 .usage = "bank_id reg_offset",
1158 .help = "Read & Display device option bytes.",
1159 },
1160 {
1161 .name = "option_write",
1162 .handler = stm32l4_handle_option_write_command,
1163 .mode = COMMAND_EXEC,
1164 .usage = "bank_id reg_offset value mask",
1165 .help = "Write device option bit fields with provided value.",
1166 },
1167 {
1168 .name = "option_load",
1169 .handler = stm32l4_handle_option_load_command,
1170 .mode = COMMAND_EXEC,
1171 .usage = "bank_id",
1172 .help = "Force re-load of device options (will cause device reset).",
1173 },
1174 COMMAND_REGISTRATION_DONE
1175 };
1176
1177 static const struct command_registration stm32l4_command_handlers[] = {
1178 {
1179 .name = "stm32l4x",
1180 .mode = COMMAND_ANY,
1181 .help = "stm32l4x flash command group",
1182 .usage = "",
1183 .chain = stm32l4_exec_command_handlers,
1184 },
1185 COMMAND_REGISTRATION_DONE
1186 };
1187
1188 const struct flash_driver stm32l4x_flash = {
1189 .name = "stm32l4x",
1190 .commands = stm32l4_command_handlers,
1191 .flash_bank_command = stm32l4_flash_bank_command,
1192 .erase = stm32l4_erase,
1193 .protect = stm32l4_protect,
1194 .write = stm32l4_write,
1195 .read = default_flash_read,
1196 .probe = stm32l4_probe,
1197 .auto_probe = stm32l4_auto_probe,
1198 .erase_check = default_flash_blank_check,
1199 .protect_check = stm32l4_protect_check,
1200 .info = get_stm32l4_info,
1201 .free_driver_priv = default_flash_free_driver_priv,
1202 };
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