Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
flash/nor/stm32h7x: remove stm32x_options.protection2
[openocd.git] / src / flash / nor / stm32h7x.c
1 /***************************************************************************
2 * Copyright (C) 2017 by STMicroelectronics *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
17 #ifdef HAVE_CONFIG_H
18 #include "config.h"
19 #endif
20
21 #include "imp.h"
22 #include <helper/binarybuffer.h>
23 #include <target/algorithm.h>
24 #include <target/armv7m.h>
25
26
27 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
28 #define FLASH_ERASE_TIMEOUT 10000
29 #define FLASH_WRITE_TIMEOUT 5
30
31 /* RM 433 */
32 /* Same Flash registers for both banks, */
33 /* access depends on Flash Base address */
34 #define FLASH_ACR 0x00
35 #define FLASH_KEYR 0x04
36 #define FLASH_OPTKEYR 0x08
37 #define FLASH_CR 0x0C
38 #define FLASH_SR 0x10
39 #define FLASH_CCR 0x14
40 #define FLASH_OPTCR 0x18
41 #define FLASH_OPTSR_CUR 0x1C
42 #define FLASH_OPTSR_PRG 0x20
43 #define FLASH_OPTCCR 0x24
44 #define FLASH_WPSN_CUR 0x38
45 #define FLASH_WPSN_PRG 0x3C
46
47
48 /* FLASH_CR register bits */
49 #define FLASH_LOCK (1 << 0)
50 #define FLASH_PG (1 << 1)
51 #define FLASH_SER (1 << 2)
52 #define FLASH_BER (1 << 3)
53 #define FLASH_PSIZE_8 (0 << 4)
54 #define FLASH_PSIZE_16 (1 << 4)
55 #define FLASH_PSIZE_32 (2 << 4)
56 #define FLASH_PSIZE_64 (3 << 4)
57 #define FLASH_FW (1 << 6)
58 #define FLASH_START (1 << 7)
59
60 #define FLASH_SNB(a) ((a) << 8)
61
62 /* FLASH_SR register bits */
63 #define FLASH_BSY (1 << 0) /* Operation in progress */
64 #define FLASH_QW (1 << 2) /* Operation queue in progress */
65 #define FLASH_WRPERR (1 << 17) /* Write protection error */
66 #define FLASH_PGSERR (1 << 18) /* Programming sequence error */
67 #define FLASH_STRBERR (1 << 19) /* Strobe error */
68 #define FLASH_INCERR (1 << 21) /* Inconsistency error */
69 #define FLASH_OPERR (1 << 22) /* Operation error */
70 #define FLASH_RDPERR (1 << 23) /* Read Protection error */
71 #define FLASH_RDSERR (1 << 24) /* Secure Protection error */
72 #define FLASH_SNECCERR (1 << 25) /* Single ECC error */
73 #define FLASH_DBECCERR (1 << 26) /* Double ECC error */
74
75 #define FLASH_ERROR (FLASH_WRPERR | FLASH_PGSERR | FLASH_STRBERR | FLASH_INCERR | FLASH_OPERR | \
76 FLASH_RDPERR | FLASH_RDSERR | FLASH_SNECCERR | FLASH_DBECCERR)
77
78 /* FLASH_OPTCR register bits */
79 #define OPT_LOCK (1 << 0)
80 #define OPT_START (1 << 1)
81
82 /* register unlock keys */
83 #define KEY1 0x45670123
84 #define KEY2 0xCDEF89AB
85
86 /* option register unlock key */
87 #define OPTKEY1 0x08192A3B
88 #define OPTKEY2 0x4C5D6E7F
89
90 #define DBGMCU_IDCODE_REGISTER 0x5C001000
91 #define FLASH_BANK0_ADDRESS 0x08000000
92 #define FLASH_BANK1_ADDRESS 0x08100000
93 #define FLASH_REG_BASE_B0 0x52002000
94 #define FLASH_REG_BASE_B1 0x52002100
95 #define FLASH_SIZE_ADDRESS 0x1FF1E880
96 #define FLASH_BLOCK_SIZE 32
97
98 struct stm32h7x_rev {
99 uint16_t rev;
100 const char *str;
101 };
102
103 struct stm32x_options {
104 uint8_t RDP;
105 uint32_t protection; /* bank sectors's write protection (WPSN register) */
106 uint8_t user_options;
107 uint8_t user2_options;
108 uint8_t user3_options;
109 };
110
111 struct stm32h7x_part_info {
112 uint16_t id;
113 const char *device_str;
114 const struct stm32h7x_rev *revs;
115 size_t num_revs;
116 unsigned int page_size;
117 uint16_t max_flash_size_kb;
118 uint8_t has_dual_bank;
119 uint16_t first_bank_size_kb; /* Used when has_dual_bank is true */
120 uint32_t flash_base; /* Flash controller registers location */
121 uint32_t fsize_base; /* Location of FSIZE register */
122 };
123
124 struct stm32h7x_flash_bank {
125 int probed;
126 uint32_t idcode;
127 uint32_t user_bank_size;
128 uint32_t flash_base; /* Address of flash reg controller */
129 struct stm32x_options option_bytes;
130 const struct stm32h7x_part_info *part_info;
131 };
132
133 static const struct stm32h7x_rev stm32_450_revs[] = {
134 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X" },
135 };
136
137 static const struct stm32h7x_part_info stm32h7x_parts[] = {
138 {
139 .id = 0x450,
140 .revs = stm32_450_revs,
141 .num_revs = ARRAY_SIZE(stm32_450_revs),
142 .device_str = "STM32H74x/75x",
143 .page_size = 128, /* 128 KB */
144 .max_flash_size_kb = 2048,
145 .first_bank_size_kb = 1024,
146 .has_dual_bank = 1,
147 .flash_base = FLASH_REG_BASE_B0,
148 .fsize_base = FLASH_SIZE_ADDRESS,
149 },
150 };
151
152 static int stm32x_unlock_reg(struct flash_bank *bank);
153 static int stm32x_lock_reg(struct flash_bank *bank);
154 static int stm32x_probe(struct flash_bank *bank);
155
156 /* flash bank stm32x <base> <size> 0 0 <target#> */
157
158 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
159 {
160 struct stm32h7x_flash_bank *stm32x_info;
161
162 if (CMD_ARGC < 6)
163 return ERROR_COMMAND_SYNTAX_ERROR;
164
165 stm32x_info = malloc(sizeof(struct stm32h7x_flash_bank));
166 bank->driver_priv = stm32x_info;
167
168 stm32x_info->probed = 0;
169 stm32x_info->user_bank_size = bank->size;
170
171 return ERROR_OK;
172 }
173
174 static inline uint32_t stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
175 {
176 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
177 return reg + stm32x_info->flash_base;
178 }
179
180 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
181 {
182 struct target *target = bank->target;
183 return target_read_u32(target, stm32x_get_flash_reg(bank, FLASH_SR), status);
184 }
185
186 static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
187 {
188 struct target *target = bank->target;
189 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
190 uint32_t status;
191 int retval;
192
193 /* wait for flash operations completion */
194 for (;;) {
195 retval = stm32x_get_flash_status(bank, &status);
196 if (retval != ERROR_OK) {
197 LOG_INFO("wait_flash_op_queue, target_read_u32 : error : remote address 0x%x", stm32x_info->flash_base);
198 return retval;
199 }
200
201 if ((status & FLASH_QW) == 0)
202 break;
203
204 if (timeout-- <= 0) {
205 LOG_INFO("wait_flash_op_queue, time out expired, status: 0x%" PRIx32 "", status);
206 return ERROR_FAIL;
207 }
208 alive_sleep(1);
209 }
210
211 if (status & FLASH_WRPERR) {
212 LOG_INFO("wait_flash_op_queue, WRPERR : error : remote address 0x%x", stm32x_info->flash_base);
213 retval = ERROR_FAIL;
214 }
215
216 /* Clear error + EOP flags but report errors */
217 if (status & FLASH_ERROR) {
218 if (retval == ERROR_OK)
219 retval = ERROR_FAIL;
220 /* If this operation fails, we ignore it and report the original retval */
221 target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_CCR), status);
222 }
223 return retval;
224 }
225
226 static int stm32x_unlock_reg(struct flash_bank *bank)
227 {
228 uint32_t ctrl;
229 struct target *target = bank->target;
230
231 /* first check if not already unlocked
232 * otherwise writing on FLASH_KEYR will fail
233 */
234 int retval = target_read_u32(target, stm32x_get_flash_reg(bank, FLASH_CR), &ctrl);
235 if (retval != ERROR_OK)
236 return retval;
237
238 if ((ctrl & FLASH_LOCK) == 0)
239 return ERROR_OK;
240
241 /* unlock flash registers for bank */
242 retval = target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_KEYR), KEY1);
243 if (retval != ERROR_OK)
244 return retval;
245
246 retval = target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_KEYR), KEY2);
247 if (retval != ERROR_OK)
248 return retval;
249
250 retval = target_read_u32(target, stm32x_get_flash_reg(bank, FLASH_CR), &ctrl);
251 if (retval != ERROR_OK)
252 return retval;
253
254 if (ctrl & FLASH_LOCK) {
255 LOG_ERROR("flash not unlocked STM32_FLASH_CRx: %" PRIx32, ctrl);
256 return ERROR_TARGET_FAILURE;
257 }
258 return ERROR_OK;
259 }
260
261 static int stm32x_unlock_option_reg(struct flash_bank *bank)
262 {
263 uint32_t ctrl;
264 struct target *target = bank->target;
265
266 int retval = target_read_u32(target, FLASH_REG_BASE_B0 + FLASH_OPTCR, &ctrl);
267 if (retval != ERROR_OK)
268 return retval;
269
270 if ((ctrl & OPT_LOCK) == 0)
271 return ERROR_OK;
272
273 /* unlock option registers */
274 retval = target_write_u32(target, FLASH_REG_BASE_B0 + FLASH_OPTKEYR, OPTKEY1);
275 if (retval != ERROR_OK)
276 return retval;
277
278 retval = target_write_u32(target, FLASH_REG_BASE_B0 + FLASH_OPTKEYR, OPTKEY2);
279 if (retval != ERROR_OK)
280 return retval;
281
282 retval = target_read_u32(target, FLASH_REG_BASE_B0 + FLASH_OPTCR, &ctrl);
283 if (retval != ERROR_OK)
284 return retval;
285
286 if (ctrl & OPT_LOCK) {
287 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
288 return ERROR_TARGET_FAILURE;
289 }
290
291 return ERROR_OK;
292 }
293
294 static int stm32x_lock_reg(struct flash_bank *bank)
295 {
296 struct target *target = bank->target;
297
298 /* Lock bank reg */
299 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_CR), FLASH_LOCK);
300 if (retval != ERROR_OK)
301 return retval;
302
303 return ERROR_OK;
304 }
305
306 static int stm32x_read_options(struct flash_bank *bank)
307 {
308 uint32_t optiondata;
309 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
310 struct target *target = bank->target;
311
312 /* read current option bytes */
313 int retval = target_read_u32(target, FLASH_REG_BASE_B0 + FLASH_OPTSR_CUR, &optiondata);
314 if (retval != ERROR_OK)
315 return retval;
316
317 /* decode option data */
318 stm32x_info->option_bytes.user_options = optiondata & 0xfc;
319 stm32x_info->option_bytes.RDP = (optiondata >> 8) & 0xff;
320 stm32x_info->option_bytes.user2_options = (optiondata >> 16) & 0xff;
321 stm32x_info->option_bytes.user3_options = (optiondata >> 24) & 0xa3;
322
323 if (stm32x_info->option_bytes.RDP != 0xAA)
324 LOG_INFO("Device Security Bit Set");
325
326 /* read current WPSN option bytes */
327 retval = target_read_u32(target, stm32x_get_flash_reg(bank, FLASH_WPSN_CUR), &optiondata);
328 if (retval != ERROR_OK)
329 return retval;
330 stm32x_info->option_bytes.protection = optiondata & 0xff;
331
332 return ERROR_OK;
333 }
334
335 static int stm32x_write_options(struct flash_bank *bank)
336 {
337 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
338 struct target *target = bank->target;
339 uint32_t optiondata;
340
341 int retval = stm32x_unlock_option_reg(bank);
342 if (retval != ERROR_OK)
343 return retval;
344
345 /* rebuild option data */
346 optiondata = stm32x_info->option_bytes.user_options;
347 optiondata |= (stm32x_info->option_bytes.RDP << 8);
348 optiondata |= (stm32x_info->option_bytes.user2_options & 0xff) << 16;
349 optiondata |= (stm32x_info->option_bytes.user3_options & 0xa3) << 24;
350
351 /* program options */
352 retval = target_write_u32(target, FLASH_REG_BASE_B0 + FLASH_OPTSR_PRG, optiondata);
353 if (retval != ERROR_OK)
354 return retval;
355
356 optiondata = stm32x_info->option_bytes.protection & 0xff;
357 /* Program protection WPSNPRG */
358 retval = target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_WPSN_PRG), optiondata);
359 if (retval != ERROR_OK)
360 return retval;
361
362 optiondata = 0x40000000;
363 /* Remove OPT error flag before programming */
364 retval = target_write_u32(target, FLASH_REG_BASE_B0 + FLASH_OPTCCR, optiondata);
365 if (retval != ERROR_OK)
366 return retval;
367
368 /* start programming cycle */
369 retval = target_write_u32(target, FLASH_REG_BASE_B0 + FLASH_OPTCR, OPT_START);
370 if (retval != ERROR_OK)
371 return retval;
372
373 /* wait for completion */
374 int timeout = FLASH_ERASE_TIMEOUT;
375 for (;;) {
376 uint32_t status;
377 retval = target_read_u32(target, FLASH_REG_BASE_B0 + FLASH_SR, &status);
378 if (retval != ERROR_OK) {
379 LOG_INFO("stm32x_write_options: wait_flash_op_queue : error");
380 return retval;
381 }
382 if ((status & FLASH_QW) == 0)
383 break;
384
385 if (timeout-- <= 0) {
386 LOG_INFO("wait_flash_op_queue, time out expired, status: 0x%" PRIx32 "", status);
387 return ERROR_FAIL;
388 }
389 alive_sleep(1);
390 }
391
392 /* relock option registers */
393 retval = target_write_u32(target, FLASH_REG_BASE_B0 + FLASH_OPTCR, OPT_LOCK);
394 if (retval != ERROR_OK)
395 return retval;
396
397 return ERROR_OK;
398 }
399
400 static int stm32x_protect_check(struct flash_bank *bank)
401 {
402 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
403
404 /* read 'write protection' settings */
405 int retval = stm32x_read_options(bank);
406 if (retval != ERROR_OK) {
407 LOG_DEBUG("unable to read option bytes");
408 return retval;
409 }
410
411 for (int i = 0; i < bank->num_sectors; i++) {
412 bank->sectors[i].is_protected = stm32x_info->option_bytes.protection & (1 << i) ? 0 : 1;
413 }
414 return ERROR_OK;
415 }
416
417 static int stm32x_erase(struct flash_bank *bank, int first, int last)
418 {
419 struct target *target = bank->target;
420 int retval;
421
422 assert(first < bank->num_sectors);
423 assert(last < bank->num_sectors);
424
425 if (bank->target->state != TARGET_HALTED)
426 return ERROR_TARGET_NOT_HALTED;
427
428 retval = stm32x_unlock_reg(bank);
429 if (retval != ERROR_OK)
430 return retval;
431
432 /*
433 Sector Erase
434 To erase a sector, follow the procedure below:
435 1. Check that no Flash memory operation is ongoing by checking the QW bit in the
436 FLASH_SR register
437 2. Set the SER bit and select the sector
438 you wish to erase (SNB) in the FLASH_CR register
439 3. Set the STRT bit in the FLASH_CR register
440 4. Wait for flash operations completion
441 */
442 for (int i = first; i <= last; i++) {
443 LOG_DEBUG("erase sector %d", i);
444 retval = target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_CR),
445 FLASH_SER | FLASH_SNB(i) | FLASH_PSIZE_64);
446 if (retval != ERROR_OK) {
447 LOG_ERROR("Error erase sector %d", i);
448 return retval;
449 }
450 retval = target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_CR),
451 FLASH_SER | FLASH_SNB(i) | FLASH_PSIZE_64 | FLASH_START);
452 if (retval != ERROR_OK) {
453 LOG_ERROR("Error erase sector %d", i);
454 return retval;
455 }
456 retval = stm32x_wait_flash_op_queue(bank, FLASH_ERASE_TIMEOUT);
457
458 if (retval != ERROR_OK) {
459 LOG_ERROR("erase time-out or operation error sector %d", i);
460 return retval;
461 }
462 bank->sectors[i].is_erased = 1;
463 }
464
465 retval = stm32x_lock_reg(bank);
466 if (retval != ERROR_OK) {
467 LOG_ERROR("error during the lock of flash");
468 return retval;
469 }
470
471 return ERROR_OK;
472 }
473
474 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
475 {
476 struct target *target = bank->target;
477 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
478
479 if (target->state != TARGET_HALTED) {
480 LOG_ERROR("Target not halted");
481 return ERROR_TARGET_NOT_HALTED;
482 }
483 /* read protection settings */
484 int retval = stm32x_read_options(bank);
485 if (retval != ERROR_OK) {
486 LOG_DEBUG("unable to read option bytes");
487 return retval;
488 }
489
490 for (int i = first; i <= last; i++) {
491 if (set)
492 stm32x_info->option_bytes.protection &= ~(1 << i);
493 else
494 stm32x_info->option_bytes.protection |= (1 << i);
495 }
496
497 LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%x",
498 (stm32x_info->option_bytes.protection & 0xff));
499
500 retval = stm32x_write_options(bank);
501 if (retval != ERROR_OK)
502 return retval;
503
504 return ERROR_OK;
505 }
506
507 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
508 uint32_t offset, uint32_t count)
509 {
510 struct target *target = bank->target;
511 /*
512 * If the size of the data part of the buffer is not a multiple of FLASH_BLOCK_SIZE, we get
513 * "corrupted fifo read" pointer in target_run_flash_async_algorithm()
514 */
515 uint32_t data_size = 512 * FLASH_BLOCK_SIZE; /* 16384 */
516 uint32_t buffer_size = 8 + data_size;
517 struct working_area *write_algorithm;
518 struct working_area *source;
519 uint32_t address = bank->base + offset;
520 struct reg_param reg_params[5];
521 struct armv7m_algorithm armv7m_info;
522 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
523 int retval = ERROR_OK;
524
525 static const uint8_t stm32x_flash_write_code[] = {
526 #include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
527 };
528
529 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
530 &write_algorithm) != ERROR_OK) {
531 LOG_WARNING("no working area available, can't do block memory writes");
532 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
533 }
534
535 retval = target_write_buffer(target, write_algorithm->address,
536 sizeof(stm32x_flash_write_code),
537 stm32x_flash_write_code);
538 if (retval != ERROR_OK) {
539 target_free_working_area(target, write_algorithm);
540 return retval;
541 }
542
543 /* memory buffer */
544 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
545 data_size /= 2;
546 buffer_size = 8 + data_size;
547 if (data_size <= 256) {
548 /* we already allocated the writing code, but failed to get a
549 * buffer, free the algorithm */
550 target_free_working_area(target, write_algorithm);
551
552 LOG_WARNING("no large enough working area available, can't do block memory writes");
553 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
554 }
555 }
556
557 LOG_DEBUG("target_alloc_working_area_try : buffer_size -> 0x%x", buffer_size);
558
559 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
560 armv7m_info.core_mode = ARM_MODE_THREAD;
561
562 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
563 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
564 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
565 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (word-256 bits) */
566 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* flash reg base */
567
568 buf_set_u32(reg_params[0].value, 0, 32, source->address);
569 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
570 buf_set_u32(reg_params[2].value, 0, 32, address);
571 buf_set_u32(reg_params[3].value, 0, 32, count);
572 buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->flash_base);
573
574 retval = target_run_flash_async_algorithm(target,
575 buffer,
576 count,
577 FLASH_BLOCK_SIZE,
578 0, NULL,
579 5, reg_params,
580 source->address, source->size,
581 write_algorithm->address, 0,
582 &armv7m_info);
583
584 if (retval == ERROR_FLASH_OPERATION_FAILED) {
585 LOG_INFO("error executing stm32h7x flash write algorithm");
586
587 uint32_t flash_sr = buf_get_u32(reg_params[0].value, 0, 32);
588
589 if (flash_sr & FLASH_WRPERR)
590 LOG_ERROR("flash memory write protected");
591
592 if ((flash_sr & FLASH_ERROR) != 0) {
593 LOG_ERROR("flash write failed, FLASH_SR = %08" PRIx32, flash_sr);
594 /* Clear error + EOP flags but report errors */
595 target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_CCR), flash_sr);
596 retval = ERROR_FAIL;
597 }
598 }
599
600 target_free_working_area(target, source);
601 target_free_working_area(target, write_algorithm);
602
603 destroy_reg_param(&reg_params[0]);
604 destroy_reg_param(&reg_params[1]);
605 destroy_reg_param(&reg_params[2]);
606 destroy_reg_param(&reg_params[3]);
607 destroy_reg_param(&reg_params[4]);
608 return retval;
609 }
610
611 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
612 uint32_t offset, uint32_t count)
613 {
614 struct target *target = bank->target;
615 uint32_t address = bank->base + offset;
616 int retval, retval2;
617
618 if (bank->target->state != TARGET_HALTED) {
619 LOG_ERROR("Target not halted");
620 return ERROR_TARGET_NOT_HALTED;
621 }
622
623 if (offset % FLASH_BLOCK_SIZE) {
624 LOG_WARNING("offset 0x%" PRIx32 " breaks required 32-byte alignment", offset);
625 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
626 }
627
628 retval = stm32x_unlock_reg(bank);
629 if (retval != ERROR_OK)
630 return retval;
631
632 uint32_t blocks_remaining = count / FLASH_BLOCK_SIZE;
633 uint32_t bytes_remaining = count % FLASH_BLOCK_SIZE;
634
635 /* multiple words (32-bytes) to be programmed in block */
636 if (blocks_remaining) {
637 retval = stm32x_write_block(bank, buffer, offset, blocks_remaining);
638 if (retval != ERROR_OK) {
639 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
640 /* if block write failed (no sufficient working area),
641 * we use normal (slow) dword accesses */
642 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
643 }
644 } else {
645 buffer += blocks_remaining * FLASH_BLOCK_SIZE;
646 address += blocks_remaining * FLASH_BLOCK_SIZE;
647 blocks_remaining = 0;
648 }
649 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
650 goto flash_lock;
651 }
652
653 /*
654 Standard programming
655 The Flash memory programming sequence is as follows:
656 1. Check that no main Flash memory operation is ongoing by checking the QW bit in the
657 FLASH_SR register.
658 2. Set the PG bit in the FLASH_CR register
659 3. 8 x Word access (or Force Write FW)
660 4. Wait for flash operations completion
661 */
662 while (blocks_remaining > 0) {
663 retval = target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_CR), FLASH_PG | FLASH_PSIZE_64);
664 if (retval != ERROR_OK)
665 goto flash_lock;
666
667 retval = target_write_buffer(target, address, FLASH_BLOCK_SIZE, buffer);
668 if (retval != ERROR_OK)
669 goto flash_lock;
670
671 retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
672 if (retval != ERROR_OK)
673 goto flash_lock;
674
675 buffer += FLASH_BLOCK_SIZE;
676 address += FLASH_BLOCK_SIZE;
677 blocks_remaining--;
678 }
679
680 if (bytes_remaining) {
681 retval = target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_CR), FLASH_PG | FLASH_PSIZE_64);
682 if (retval != ERROR_OK)
683 goto flash_lock;
684
685 retval = target_write_buffer(target, address, bytes_remaining, buffer);
686 if (retval != ERROR_OK)
687 goto flash_lock;
688
689 /* Force Write buffer of FLASH_BLOCK_SIZE = 32 bytes */
690 retval = target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_CR), FLASH_PG | FLASH_PSIZE_64 | FLASH_FW);
691 if (retval != ERROR_OK)
692 goto flash_lock;
693
694 retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
695 if (retval != ERROR_OK)
696 goto flash_lock;
697 }
698
699 flash_lock:
700 retval2 = stm32x_lock_reg(bank);
701 if (retval2 != ERROR_OK)
702 LOG_ERROR("error during the lock of flash");
703
704 if (retval == ERROR_OK)
705 retval = retval2;
706
707 return retval;
708 }
709
710 static void setup_sector(struct flash_bank *bank, int start, int num, int size)
711 {
712 for (int i = start; i < (start + num) ; i++) {
713 assert(i < bank->num_sectors);
714 bank->sectors[i].offset = bank->size;
715 bank->sectors[i].size = size;
716 bank->size += bank->sectors[i].size;
717 }
718 }
719
720 static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
721 {
722 /* read stm32 device id register */
723 int retval = target_read_u32(bank->target, DBGMCU_IDCODE_REGISTER, id);
724 if (retval != ERROR_OK)
725 return retval;
726 return ERROR_OK;
727 }
728
729 static int stm32x_probe(struct flash_bank *bank)
730 {
731 struct target *target = bank->target;
732 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
733 int i;
734 uint16_t flash_size_in_kb;
735 uint32_t device_id;
736 uint32_t base_address = FLASH_BANK0_ADDRESS;
737 uint32_t second_bank_base;
738
739 stm32x_info->probed = 0;
740 stm32x_info->part_info = NULL;
741
742 int retval = stm32x_read_id_code(bank, &stm32x_info->idcode);
743 if (retval != ERROR_OK)
744 return retval;
745
746 LOG_DEBUG("device id = 0x%08" PRIx32 "", stm32x_info->idcode);
747
748 device_id = stm32x_info->idcode & 0xfff;
749
750 for (unsigned int n = 0; n < ARRAY_SIZE(stm32h7x_parts); n++) {
751 if (device_id == stm32h7x_parts[n].id)
752 stm32x_info->part_info = &stm32h7x_parts[n];
753 }
754 if (!stm32x_info->part_info) {
755 LOG_WARNING("Cannot identify target as a STM32H7xx family.");
756 return ERROR_FAIL;
757 } else {
758 LOG_INFO("Device: %s", stm32x_info->part_info->device_str);
759 }
760
761 /* update the address of controller from data base */
762 stm32x_info->flash_base = stm32x_info->part_info->flash_base;
763
764 /* get flash size from target */
765 retval = target_read_u16(target, stm32x_info->part_info->fsize_base, &flash_size_in_kb);
766 if (retval != ERROR_OK) {
767 /* read error when device has invalid value, set max flash size */
768 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
769 } else
770 LOG_INFO("flash size probed value %d", flash_size_in_kb);
771
772 /* Lower flash size devices are single bank */
773 if (stm32x_info->part_info->has_dual_bank && (flash_size_in_kb > stm32x_info->part_info->first_bank_size_kb)) {
774 /* Use the configured base address to determine if this is the first or second flash bank.
775 * Verify that the base address is reasonably correct and determine the flash bank size
776 */
777 second_bank_base = base_address + stm32x_info->part_info->first_bank_size_kb * 1024;
778 if (bank->base == second_bank_base) {
779 /* This is the second bank */
780 base_address = second_bank_base;
781 flash_size_in_kb = flash_size_in_kb - stm32x_info->part_info->first_bank_size_kb;
782 /* bank1 also uses a register offset */
783 stm32x_info->flash_base = FLASH_REG_BASE_B1;
784 } else if (bank->base == base_address) {
785 /* This is the first bank */
786 flash_size_in_kb = stm32x_info->part_info->first_bank_size_kb;
787 } else {
788 LOG_WARNING("STM32H flash bank base address config is incorrect. "
789 TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
790 bank->base, base_address, second_bank_base);
791 return ERROR_FAIL;
792 }
793 LOG_INFO("STM32H flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32,
794 bank->bank_number, flash_size_in_kb, base_address);
795 } else {
796 LOG_INFO("STM32H flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
797 }
798
799 /* if the user sets the size manually then ignore the probed value
800 * this allows us to work around devices that have an invalid flash size register value */
801 if (stm32x_info->user_bank_size) {
802 LOG_INFO("ignoring flash probed value, using configured bank size");
803 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
804 } else if (flash_size_in_kb == 0xffff) {
805 /* die flash size */
806 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
807 }
808
809 /* did we assign flash size? */
810 assert(flash_size_in_kb != 0xffff);
811
812 /* calculate numbers of pages */
813 int num_pages = flash_size_in_kb / stm32x_info->part_info->page_size;
814
815 /* check that calculation result makes sense */
816 assert(num_pages > 0);
817
818 if (bank->sectors) {
819 free(bank->sectors);
820 bank->sectors = NULL;
821 }
822
823 bank->base = base_address;
824 bank->num_sectors = num_pages;
825 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
826 if (bank->sectors == NULL) {
827 LOG_ERROR("failed to allocate bank sectors");
828 return ERROR_FAIL;
829 }
830 bank->size = 0;
831
832 /* fixed memory */
833 setup_sector(bank, 0, num_pages, stm32x_info->part_info->page_size * 1024);
834
835 for (i = 0; i < num_pages; i++) {
836 bank->sectors[i].is_erased = -1;
837 bank->sectors[i].is_protected = 0;
838 }
839
840 stm32x_info->probed = 1;
841 return ERROR_OK;
842 }
843
844 static int stm32x_auto_probe(struct flash_bank *bank)
845 {
846 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
847
848 if (stm32x_info->probed)
849 return ERROR_OK;
850
851 return stm32x_probe(bank);
852 }
853
854 /* This method must return a string displaying information about the bank */
855 static int stm32x_get_info(struct flash_bank *bank, char *buf, int buf_size)
856 {
857 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
858 const struct stm32h7x_part_info *info = stm32x_info->part_info;
859
860 if (!stm32x_info->probed) {
861 int retval = stm32x_probe(bank);
862 if (retval != ERROR_OK) {
863 snprintf(buf, buf_size, "Unable to find bank information.");
864 return retval;
865 }
866 }
867
868 if (info) {
869 const char *rev_str = NULL;
870 uint16_t rev_id = stm32x_info->idcode >> 16;
871
872 for (unsigned int i = 0; i < info->num_revs; i++)
873 if (rev_id == info->revs[i].rev)
874 rev_str = info->revs[i].str;
875
876 if (rev_str != NULL) {
877 snprintf(buf, buf_size, "%s - Rev: %s",
878 stm32x_info->part_info->device_str, rev_str);
879 } else {
880 snprintf(buf, buf_size,
881 "%s - Rev: unknown (0x%04x)",
882 stm32x_info->part_info->device_str, rev_id);
883 }
884 } else {
885 snprintf(buf, buf_size, "Cannot identify target as a STM32H7x");
886 return ERROR_FAIL;
887 }
888 return ERROR_OK;
889 }
890
891 COMMAND_HANDLER(stm32x_handle_lock_command)
892 {
893 struct target *target = NULL;
894 struct stm32h7x_flash_bank *stm32x_info = NULL;
895
896 if (CMD_ARGC < 1)
897 return ERROR_COMMAND_SYNTAX_ERROR;
898
899 struct flash_bank *bank;
900 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
901 if (ERROR_OK != retval)
902 return retval;
903
904 stm32x_info = bank->driver_priv;
905 target = bank->target;
906
907 /* if we have a dual flash bank device then
908 * we need to perform option byte lock on bank0 only */
909 if (stm32x_info->flash_base != FLASH_REG_BASE_B0) {
910 LOG_ERROR("Option Byte Lock Operation must use bank0");
911 return ERROR_FLASH_OPERATION_FAILED;
912 }
913
914 if (target->state != TARGET_HALTED) {
915 LOG_ERROR("Target not halted");
916 return ERROR_TARGET_NOT_HALTED;
917 }
918
919 if (stm32x_read_options(bank) != ERROR_OK) {
920 command_print(CMD, "%s failed to read options",
921 bank->driver->name);
922 return ERROR_OK;
923 }
924 /* set readout protection */
925 stm32x_info->option_bytes.RDP = 0;
926
927 if (stm32x_write_options(bank) != ERROR_OK) {
928 command_print(CMD, "%s failed to lock device",
929 bank->driver->name);
930 return ERROR_OK;
931 }
932 command_print(CMD, "%s locked", bank->driver->name);
933
934 return ERROR_OK;
935 }
936
937 COMMAND_HANDLER(stm32x_handle_unlock_command)
938 {
939 struct target *target = NULL;
940 struct stm32h7x_flash_bank *stm32x_info = NULL;
941
942 if (CMD_ARGC < 1)
943 return ERROR_COMMAND_SYNTAX_ERROR;
944
945 struct flash_bank *bank;
946 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
947 if (ERROR_OK != retval)
948 return retval;
949
950 stm32x_info = bank->driver_priv;
951 target = bank->target;
952
953 /* if we have a dual flash bank device then
954 * we need to perform option byte unlock on bank0 only */
955 if (stm32x_info->flash_base != FLASH_REG_BASE_B0) {
956 LOG_ERROR("Option Byte Unlock Operation must use bank0");
957 return ERROR_FLASH_OPERATION_FAILED;
958 }
959
960 if (target->state != TARGET_HALTED) {
961 LOG_ERROR("Target not halted");
962 return ERROR_TARGET_NOT_HALTED;
963 }
964
965 if (stm32x_read_options(bank) != ERROR_OK) {
966 command_print(CMD, "%s failed to read options", bank->driver->name);
967 return ERROR_OK;
968 }
969
970 /* clear readout protection option byte
971 * this will also force a device unlock if set */
972 stm32x_info->option_bytes.RDP = 0xAA;
973
974 if (stm32x_write_options(bank) != ERROR_OK) {
975 command_print(CMD, "%s failed to unlock device", bank->driver->name);
976 return ERROR_OK;
977 }
978 command_print(CMD, "%s unlocked.\n", bank->driver->name);
979
980 return ERROR_OK;
981 }
982
983 static int stm32x_mass_erase(struct flash_bank *bank)
984 {
985 int retval;
986 struct target *target = bank->target;
987
988 if (target->state != TARGET_HALTED) {
989 LOG_ERROR("Target not halted");
990 return ERROR_TARGET_NOT_HALTED;
991 }
992
993 retval = stm32x_unlock_reg(bank);
994 if (retval != ERROR_OK)
995 return retval;
996
997 /* mass erase flash memory bank */
998 retval = target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_CR), FLASH_BER | FLASH_PSIZE_64);
999 if (retval != ERROR_OK)
1000 return retval;
1001
1002 retval = target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_CR),
1003 FLASH_BER | FLASH_PSIZE_64 | FLASH_START);
1004 if (retval != ERROR_OK)
1005 return retval;
1006
1007 retval = stm32x_wait_flash_op_queue(bank, 30000);
1008 if (retval != ERROR_OK)
1009 return retval;
1010
1011 retval = stm32x_lock_reg(bank);
1012 if (retval != ERROR_OK) {
1013 LOG_ERROR("error during the lock of flash");
1014 return retval;
1015 }
1016 return ERROR_OK;
1017 }
1018
1019 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1020 {
1021 int i;
1022
1023 if (CMD_ARGC < 1) {
1024 command_print(CMD, "stm32h7x mass_erase <bank>");
1025 return ERROR_COMMAND_SYNTAX_ERROR;
1026 }
1027
1028 struct flash_bank *bank;
1029 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1030 if (ERROR_OK != retval)
1031 return retval;
1032
1033 retval = stm32x_mass_erase(bank);
1034 if (retval == ERROR_OK) {
1035 /* set all sectors as erased */
1036 for (i = 0; i < bank->num_sectors; i++)
1037 bank->sectors[i].is_erased = 1;
1038
1039 command_print(CMD, "stm32h7x mass erase complete");
1040 } else {
1041 command_print(CMD, "stm32h7x mass erase failed");
1042 }
1043
1044 return retval;
1045 }
1046
1047 static const struct command_registration stm32x_exec_command_handlers[] = {
1048 {
1049 .name = "lock",
1050 .handler = stm32x_handle_lock_command,
1051 .mode = COMMAND_EXEC,
1052 .usage = "bank_id",
1053 .help = "Lock entire flash device.",
1054 },
1055 {
1056 .name = "unlock",
1057 .handler = stm32x_handle_unlock_command,
1058 .mode = COMMAND_EXEC,
1059 .usage = "bank_id",
1060 .help = "Unlock entire protected flash device.",
1061 },
1062 {
1063 .name = "mass_erase",
1064 .handler = stm32x_handle_mass_erase_command,
1065 .mode = COMMAND_EXEC,
1066 .usage = "bank_id",
1067 .help = "Erase entire flash device.",
1068 },
1069 COMMAND_REGISTRATION_DONE
1070 };
1071
1072 static const struct command_registration stm32x_command_handlers[] = {
1073 {
1074 .name = "stm32h7x",
1075 .mode = COMMAND_ANY,
1076 .help = "stm32h7x flash command group",
1077 .usage = "",
1078 .chain = stm32x_exec_command_handlers,
1079 },
1080 COMMAND_REGISTRATION_DONE
1081 };
1082
1083 const struct flash_driver stm32h7x_flash = {
1084 .name = "stm32h7x",
1085 .commands = stm32x_command_handlers,
1086 .flash_bank_command = stm32x_flash_bank_command,
1087 .erase = stm32x_erase,
1088 .protect = stm32x_protect,
1089 .write = stm32x_write,
1090 .read = default_flash_read,
1091 .probe = stm32x_probe,
1092 .auto_probe = stm32x_auto_probe,
1093 .erase_check = default_flash_blank_check,
1094 .protect_check = stm32x_protect_check,
1095 .info = stm32x_get_info,
1096 .free_driver_priv = default_flash_free_driver_priv,
1097 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)