1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
34 /* stm32x register locations */
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
60 /* option byte location */
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
71 /* FLASH_CR register bits */
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
82 /* FLASH_SR register bits */
84 #define FLASH_BSY (1 << 0)
85 #define FLASH_PGERR (1 << 2)
86 #define FLASH_WRPRTERR (1 << 4)
87 #define FLASH_EOP (1 << 5)
89 /* STM32_FLASH_OBR bit definitions (reading) */
94 #define OPT_RDRSTSTOP 3
95 #define OPT_RDRSTSTDBY 4
96 #define OPT_BFB2 5 /* dual flash bank only */
98 /* register unlock keys */
100 #define KEY1 0x45670123
101 #define KEY2 0xCDEF89AB
105 #define FLASH_WRITE_TIMEOUT 10
106 #define FLASH_ERASE_TIMEOUT 100
108 struct stm32x_options
{
110 uint16_t user_options
;
112 uint16_t protection
[4];
115 struct stm32x_flash_bank
{
116 struct stm32x_options option_bytes
;
121 /* used to access dual flash bank stm32xl */
122 uint32_t register_base
;
123 uint16_t default_rdp
;
124 int user_data_offset
;
126 uint32_t user_bank_size
;
129 static int stm32x_mass_erase(struct flash_bank
*bank
);
130 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
);
131 static int stm32x_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
132 uint32_t offset
, uint32_t count
);
134 /* flash bank stm32x <base> <size> 0 0 <target#>
136 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
138 struct stm32x_flash_bank
*stm32x_info
;
141 return ERROR_COMMAND_SYNTAX_ERROR
;
143 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
145 bank
->driver_priv
= stm32x_info
;
146 stm32x_info
->probed
= 0;
147 stm32x_info
->has_dual_banks
= false;
148 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
149 stm32x_info
->user_bank_size
= bank
->size
;
154 static inline int stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
156 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
157 return reg
+ stm32x_info
->register_base
;
160 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
162 struct target
*target
= bank
->target
;
163 return target_read_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
166 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
168 struct target
*target
= bank
->target
;
170 int retval
= ERROR_OK
;
172 /* wait for busy to clear */
174 retval
= stm32x_get_flash_status(bank
, &status
);
175 if (retval
!= ERROR_OK
)
177 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
178 if ((status
& FLASH_BSY
) == 0)
180 if (timeout
-- <= 0) {
181 LOG_ERROR("timed out waiting for flash");
187 if (status
& FLASH_WRPRTERR
) {
188 LOG_ERROR("stm32x device protected");
192 if (status
& FLASH_PGERR
) {
193 LOG_ERROR("stm32x device programming failed");
197 /* Clear but report errors */
198 if (status
& (FLASH_WRPRTERR
| FLASH_PGERR
)) {
199 /* If this operation fails, we ignore it and report the original
202 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
),
203 FLASH_WRPRTERR
| FLASH_PGERR
);
208 static int stm32x_check_operation_supported(struct flash_bank
*bank
)
210 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
212 /* if we have a dual flash bank device then
213 * we need to perform option byte stuff on bank0 only */
214 if (stm32x_info
->register_base
!= FLASH_REG_BASE_B0
) {
215 LOG_ERROR("Option Byte Operation's must use bank0");
216 return ERROR_FLASH_OPERATION_FAILED
;
222 static int stm32x_read_options(struct flash_bank
*bank
)
225 struct stm32x_flash_bank
*stm32x_info
= NULL
;
226 struct target
*target
= bank
->target
;
228 stm32x_info
= bank
->driver_priv
;
230 /* read current option bytes */
231 int retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optiondata
);
232 if (retval
!= ERROR_OK
)
235 stm32x_info
->option_bytes
.user_options
= (optiondata
>> stm32x_info
->option_offset
>> 2) & 0xffff;
236 stm32x_info
->option_bytes
.user_data
= (optiondata
>> stm32x_info
->user_data_offset
) & 0xffff;
237 stm32x_info
->option_bytes
.RDP
= (optiondata
& (1 << OPT_READOUT
)) ? 0xFFFF : 0x5AA5;
239 if (optiondata
& (1 << OPT_READOUT
))
240 LOG_INFO("Device Security Bit Set");
242 /* each bit refers to a 4bank protection */
243 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &optiondata
);
244 if (retval
!= ERROR_OK
)
247 stm32x_info
->option_bytes
.protection
[0] = (uint16_t)optiondata
;
248 stm32x_info
->option_bytes
.protection
[1] = (uint16_t)(optiondata
>> 8);
249 stm32x_info
->option_bytes
.protection
[2] = (uint16_t)(optiondata
>> 16);
250 stm32x_info
->option_bytes
.protection
[3] = (uint16_t)(optiondata
>> 24);
255 static int stm32x_erase_options(struct flash_bank
*bank
)
257 struct stm32x_flash_bank
*stm32x_info
= NULL
;
258 struct target
*target
= bank
->target
;
260 stm32x_info
= bank
->driver_priv
;
262 /* read current options */
263 stm32x_read_options(bank
);
265 /* unlock flash registers */
266 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
267 if (retval
!= ERROR_OK
)
270 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
271 if (retval
!= ERROR_OK
)
274 /* unlock option flash registers */
275 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
276 if (retval
!= ERROR_OK
)
278 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
279 if (retval
!= ERROR_OK
)
282 /* erase option bytes */
283 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_OPTWRE
);
284 if (retval
!= ERROR_OK
)
286 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_STRT
| FLASH_OPTWRE
);
287 if (retval
!= ERROR_OK
)
290 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
291 if (retval
!= ERROR_OK
)
294 /* clear readout protection and complementary option bytes
295 * this will also force a device unlock if set */
296 stm32x_info
->option_bytes
.RDP
= stm32x_info
->default_rdp
;
301 static int stm32x_write_options(struct flash_bank
*bank
)
303 struct stm32x_flash_bank
*stm32x_info
= NULL
;
304 struct target
*target
= bank
->target
;
306 stm32x_info
= bank
->driver_priv
;
308 /* unlock flash registers */
309 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
310 if (retval
!= ERROR_OK
)
312 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
313 if (retval
!= ERROR_OK
)
316 /* unlock option flash registers */
317 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
318 if (retval
!= ERROR_OK
)
320 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
321 if (retval
!= ERROR_OK
)
324 /* program option bytes */
325 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTPG
| FLASH_OPTWRE
);
326 if (retval
!= ERROR_OK
)
329 uint8_t opt_bytes
[16];
331 target_buffer_set_u16(target
, opt_bytes
, stm32x_info
->option_bytes
.RDP
);
332 target_buffer_set_u16(target
, opt_bytes
+ 2, stm32x_info
->option_bytes
.user_options
);
333 target_buffer_set_u16(target
, opt_bytes
+ 4, stm32x_info
->option_bytes
.user_data
& 0xff);
334 target_buffer_set_u16(target
, opt_bytes
+ 6, (stm32x_info
->option_bytes
.user_data
>> 8) & 0xff);
335 target_buffer_set_u16(target
, opt_bytes
+ 8, stm32x_info
->option_bytes
.protection
[0]);
336 target_buffer_set_u16(target
, opt_bytes
+ 10, stm32x_info
->option_bytes
.protection
[1]);
337 target_buffer_set_u16(target
, opt_bytes
+ 12, stm32x_info
->option_bytes
.protection
[2]);
338 target_buffer_set_u16(target
, opt_bytes
+ 14, stm32x_info
->option_bytes
.protection
[3]);
340 uint32_t offset
= STM32_OB_RDP
- bank
->base
;
341 retval
= stm32x_write_block(bank
, opt_bytes
, offset
, sizeof(opt_bytes
) / 2);
342 if (retval
!= ERROR_OK
) {
343 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
344 LOG_ERROR("working area required to erase options bytes");
348 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_LOCK
);
349 if (retval
!= ERROR_OK
)
355 static int stm32x_protect_check(struct flash_bank
*bank
)
357 struct target
*target
= bank
->target
;
358 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
365 int retval
= stm32x_check_operation_supported(bank
);
366 if (ERROR_OK
!= retval
)
369 /* medium density - each bit refers to a 4bank protection
370 * high density - each bit refers to a 2bank protection */
371 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
372 if (retval
!= ERROR_OK
)
375 /* medium density - each protection bit is for 4 * 1K pages
376 * high density - each protection bit is for 2 * 2K pages */
377 num_bits
= (bank
->num_sectors
/ stm32x_info
->ppage_size
);
379 if (stm32x_info
->ppage_size
== 2) {
380 /* high density flash/connectivity line protection */
384 if (protection
& (1 << 31))
387 /* bit 31 controls sector 62 - 255 protection for high density
388 * bit 31 controls sector 62 - 127 protection for connectivity line */
389 for (s
= 62; s
< bank
->num_sectors
; s
++)
390 bank
->sectors
[s
].is_protected
= set
;
392 if (bank
->num_sectors
> 61)
395 for (i
= 0; i
< num_bits
; i
++) {
398 if (protection
& (1 << i
))
401 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
402 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
405 /* low/medium density flash protection */
406 for (i
= 0; i
< num_bits
; i
++) {
409 if (protection
& (1 << i
))
412 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
413 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
420 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
422 struct target
*target
= bank
->target
;
425 if (bank
->target
->state
!= TARGET_HALTED
) {
426 LOG_ERROR("Target not halted");
427 return ERROR_TARGET_NOT_HALTED
;
430 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
431 return stm32x_mass_erase(bank
);
433 /* unlock flash registers */
434 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
435 if (retval
!= ERROR_OK
)
437 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
438 if (retval
!= ERROR_OK
)
441 for (i
= first
; i
<= last
; i
++) {
442 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
);
443 if (retval
!= ERROR_OK
)
445 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_AR
),
446 bank
->base
+ bank
->sectors
[i
].offset
);
447 if (retval
!= ERROR_OK
)
449 retval
= target_write_u32(target
,
450 stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
| FLASH_STRT
);
451 if (retval
!= ERROR_OK
)
454 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
455 if (retval
!= ERROR_OK
)
458 bank
->sectors
[i
].is_erased
= 1;
461 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
462 if (retval
!= ERROR_OK
)
468 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
470 struct stm32x_flash_bank
*stm32x_info
= NULL
;
471 struct target
*target
= bank
->target
;
472 uint16_t prot_reg
[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
477 stm32x_info
= bank
->driver_priv
;
479 if (target
->state
!= TARGET_HALTED
) {
480 LOG_ERROR("Target not halted");
481 return ERROR_TARGET_NOT_HALTED
;
484 int retval
= stm32x_check_operation_supported(bank
);
485 if (ERROR_OK
!= retval
)
488 if ((first
% stm32x_info
->ppage_size
) != 0) {
489 LOG_WARNING("aligned start protect sector to a %d sector boundary",
490 stm32x_info
->ppage_size
);
491 first
= first
- (first
% stm32x_info
->ppage_size
);
493 if (((last
+ 1) % stm32x_info
->ppage_size
) != 0) {
494 LOG_WARNING("aligned end protect sector to a %d sector boundary",
495 stm32x_info
->ppage_size
);
497 last
= last
- (last
% stm32x_info
->ppage_size
);
501 /* medium density - each bit refers to a 4bank protection
502 * high density - each bit refers to a 2bank protection */
503 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
504 if (retval
!= ERROR_OK
)
507 prot_reg
[0] = (uint16_t)protection
;
508 prot_reg
[1] = (uint16_t)(protection
>> 8);
509 prot_reg
[2] = (uint16_t)(protection
>> 16);
510 prot_reg
[3] = (uint16_t)(protection
>> 24);
512 if (stm32x_info
->ppage_size
== 2) {
513 /* high density flash */
515 /* bit 7 controls sector 62 - 255 protection */
518 prot_reg
[3] &= ~(1 << 7);
520 prot_reg
[3] |= (1 << 7);
528 for (i
= first
; i
<= last
; i
++) {
529 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
530 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
533 prot_reg
[reg
] &= ~(1 << bit
);
535 prot_reg
[reg
] |= (1 << bit
);
538 /* medium density flash */
539 for (i
= first
; i
<= last
; i
++) {
540 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
541 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
544 prot_reg
[reg
] &= ~(1 << bit
);
546 prot_reg
[reg
] |= (1 << bit
);
550 status
= stm32x_erase_options(bank
);
551 if (status
!= ERROR_OK
)
554 stm32x_info
->option_bytes
.protection
[0] = prot_reg
[0];
555 stm32x_info
->option_bytes
.protection
[1] = prot_reg
[1];
556 stm32x_info
->option_bytes
.protection
[2] = prot_reg
[2];
557 stm32x_info
->option_bytes
.protection
[3] = prot_reg
[3];
559 return stm32x_write_options(bank
);
562 static int stm32x_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
563 uint32_t offset
, uint32_t count
)
565 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
566 struct target
*target
= bank
->target
;
567 uint32_t buffer_size
= 16384;
568 struct working_area
*write_algorithm
;
569 struct working_area
*source
;
570 uint32_t address
= bank
->base
+ offset
;
571 struct reg_param reg_params
[5];
572 struct armv7m_algorithm armv7m_info
;
573 int retval
= ERROR_OK
;
575 static const uint8_t stm32x_flash_write_code
[] = {
576 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
579 /* flash write code */
580 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
581 &write_algorithm
) != ERROR_OK
) {
582 LOG_WARNING("no working area available, can't do block memory writes");
583 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
586 retval
= target_write_buffer(target
, write_algorithm
->address
,
587 sizeof(stm32x_flash_write_code
), stm32x_flash_write_code
);
588 if (retval
!= ERROR_OK
) {
589 target_free_working_area(target
, write_algorithm
);
594 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
596 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
597 if (buffer_size
<= 256) {
598 /* we already allocated the writing code, but failed to get a
599 * buffer, free the algorithm */
600 target_free_working_area(target
, write_algorithm
);
602 LOG_WARNING("no large enough working area available, can't do block memory writes");
603 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
607 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* flash base (in), status (out) */
608 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* count (halfword-16bit) */
609 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer start */
610 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* buffer end */
611 init_reg_param(®_params
[4], "r4", 32, PARAM_IN_OUT
); /* target address */
613 buf_set_u32(reg_params
[0].value
, 0, 32, stm32x_info
->register_base
);
614 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
615 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
);
616 buf_set_u32(reg_params
[3].value
, 0, 32, source
->address
+ source
->size
);
617 buf_set_u32(reg_params
[4].value
, 0, 32, address
);
619 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
620 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
622 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
625 source
->address
, source
->size
,
626 write_algorithm
->address
, 0,
629 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
630 LOG_ERROR("flash write failed at address 0x%"PRIx32
,
631 buf_get_u32(reg_params
[4].value
, 0, 32));
633 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_PGERR
) {
634 LOG_ERROR("flash memory not erased before writing");
635 /* Clear but report errors */
636 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_PGERR
);
639 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_WRPRTERR
) {
640 LOG_ERROR("flash memory write protected");
641 /* Clear but report errors */
642 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_WRPRTERR
);
646 target_free_working_area(target
, source
);
647 target_free_working_area(target
, write_algorithm
);
649 destroy_reg_param(®_params
[0]);
650 destroy_reg_param(®_params
[1]);
651 destroy_reg_param(®_params
[2]);
652 destroy_reg_param(®_params
[3]);
653 destroy_reg_param(®_params
[4]);
658 static int stm32x_write(struct flash_bank
*bank
, const uint8_t *buffer
,
659 uint32_t offset
, uint32_t count
)
661 struct target
*target
= bank
->target
;
662 uint8_t *new_buffer
= NULL
;
664 if (bank
->target
->state
!= TARGET_HALTED
) {
665 LOG_ERROR("Target not halted");
666 return ERROR_TARGET_NOT_HALTED
;
670 LOG_ERROR("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
671 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
674 /* If there's an odd number of bytes, the data has to be padded. Duplicate
675 * the buffer and use the normal code path with a single block write since
676 * it's probably cheaper than to special case the last odd write using
677 * discrete accesses. */
679 new_buffer
= malloc(count
+ 1);
680 if (new_buffer
== NULL
) {
681 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
684 LOG_INFO("odd number of bytes to write, padding with 0xff");
685 buffer
= memcpy(new_buffer
, buffer
, count
);
686 new_buffer
[count
++] = 0xff;
689 uint32_t words_remaining
= count
/ 2;
692 /* unlock flash registers */
693 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
694 if (retval
!= ERROR_OK
)
696 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
697 if (retval
!= ERROR_OK
)
700 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PG
);
701 if (retval
!= ERROR_OK
)
704 /* try using a block write */
705 retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
);
707 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
708 /* if block write failed (no sufficient working area),
709 * we use normal (slow) single halfword accesses */
710 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
712 while (words_remaining
> 0) {
714 memcpy(&value
, buffer
, sizeof(uint16_t));
716 retval
= target_write_u16(target
, bank
->base
+ offset
, value
);
717 if (retval
!= ERROR_OK
)
718 goto reset_pg_and_lock
;
720 retval
= stm32x_wait_status_busy(bank
, 5);
721 if (retval
!= ERROR_OK
)
722 goto reset_pg_and_lock
;
731 retval2
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
732 if (retval
== ERROR_OK
)
742 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
)
744 /* This check the device CPUID core register to detect
745 * the M0 from the M3 devices. */
747 struct target
*target
= bank
->target
;
748 uint32_t cpuid
, device_id_register
= 0;
750 /* Get the CPUID from the ARM Core
751 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
752 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
753 if (retval
!= ERROR_OK
)
756 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
757 /* 0xC20 is M0 devices */
758 device_id_register
= 0x40015800;
759 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
760 /* 0xC23 is M3 devices */
761 device_id_register
= 0xE0042000;
762 } else if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
763 /* 0xC24 is M4 devices */
764 device_id_register
= 0xE0042000;
766 LOG_ERROR("Cannot identify target as a stm32x");
770 /* read stm32 device id register */
771 retval
= target_read_u32(target
, device_id_register
, device_id
);
772 if (retval
!= ERROR_OK
)
778 static int stm32x_get_flash_size(struct flash_bank
*bank
, uint16_t *flash_size_in_kb
)
780 struct target
*target
= bank
->target
;
781 uint32_t cpuid
, flash_size_reg
;
783 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
784 if (retval
!= ERROR_OK
)
787 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
788 /* 0xC20 is M0 devices */
789 flash_size_reg
= 0x1FFFF7CC;
790 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
791 /* 0xC23 is M3 devices */
792 flash_size_reg
= 0x1FFFF7E0;
793 } else if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
794 /* 0xC24 is M4 devices */
795 flash_size_reg
= 0x1FFFF7CC;
797 LOG_ERROR("Cannot identify target as a stm32x");
801 retval
= target_read_u16(target
, flash_size_reg
, flash_size_in_kb
);
802 if (retval
!= ERROR_OK
)
808 static int stm32x_probe(struct flash_bank
*bank
)
810 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
812 uint16_t flash_size_in_kb
;
813 uint16_t max_flash_size_in_kb
;
816 uint32_t base_address
= 0x08000000;
818 stm32x_info
->probed
= 0;
819 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
820 stm32x_info
->user_data_offset
= 10;
821 stm32x_info
->option_offset
= 0;
823 /* default factory protection level */
824 stm32x_info
->default_rdp
= 0x5AA5;
826 /* read stm32 device id register */
827 int retval
= stm32x_get_device_id(bank
, &device_id
);
828 if (retval
!= ERROR_OK
)
831 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
833 /* set page size, protection granularity and max flash size depending on family */
834 switch (device_id
& 0xfff) {
835 case 0x410: /* medium density */
837 stm32x_info
->ppage_size
= 4;
838 max_flash_size_in_kb
= 128;
840 case 0x412: /* low density */
842 stm32x_info
->ppage_size
= 4;
843 max_flash_size_in_kb
= 32;
845 case 0x414: /* high density */
847 stm32x_info
->ppage_size
= 2;
848 max_flash_size_in_kb
= 512;
850 case 0x418: /* connectivity line density */
852 stm32x_info
->ppage_size
= 2;
853 max_flash_size_in_kb
= 256;
855 case 0x420: /* value line density */
857 stm32x_info
->ppage_size
= 4;
858 max_flash_size_in_kb
= 128;
860 case 0x422: /* stm32f302/3xb/c */
862 stm32x_info
->ppage_size
= 2;
863 max_flash_size_in_kb
= 256;
864 stm32x_info
->user_data_offset
= 16;
865 stm32x_info
->option_offset
= 6;
866 stm32x_info
->default_rdp
= 0x55AA;
868 case 0x446: /* stm32f303xD/E */
870 stm32x_info
->ppage_size
= 2;
871 max_flash_size_in_kb
= 512;
872 stm32x_info
->user_data_offset
= 16;
873 stm32x_info
->option_offset
= 6;
874 stm32x_info
->default_rdp
= 0x55AA;
876 case 0x428: /* value line High density */
878 stm32x_info
->ppage_size
= 4;
879 max_flash_size_in_kb
= 128;
881 case 0x430: /* xl line density (dual flash banks) */
883 stm32x_info
->ppage_size
= 2;
884 max_flash_size_in_kb
= 1024;
885 stm32x_info
->has_dual_banks
= true;
887 case 0x432: /* stm32f37x */
889 stm32x_info
->ppage_size
= 2;
890 max_flash_size_in_kb
= 256;
891 stm32x_info
->user_data_offset
= 16;
892 stm32x_info
->option_offset
= 6;
893 stm32x_info
->default_rdp
= 0x55AA;
895 case 0x438: /* stm32f33x */
896 case 0x439: /* stm32f302x6/8 */
898 stm32x_info
->ppage_size
= 2;
899 max_flash_size_in_kb
= 64;
900 stm32x_info
->user_data_offset
= 16;
901 stm32x_info
->option_offset
= 6;
902 stm32x_info
->default_rdp
= 0x55AA;
904 case 0x440: /* stm32f05x */
905 case 0x444: /* stm32f03x */
906 case 0x445: /* stm32f04x */
908 stm32x_info
->ppage_size
= 4;
909 max_flash_size_in_kb
= 64;
910 stm32x_info
->user_data_offset
= 16;
911 stm32x_info
->option_offset
= 6;
912 stm32x_info
->default_rdp
= 0x55AA;
914 case 0x448: /* stm32f07x */
915 case 0x442: /* stm32f09x */
917 stm32x_info
->ppage_size
= 4;
918 max_flash_size_in_kb
= 256;
919 stm32x_info
->user_data_offset
= 16;
920 stm32x_info
->option_offset
= 6;
921 stm32x_info
->default_rdp
= 0x55AA;
924 LOG_WARNING("Cannot identify target as a STM32 family.");
928 /* get flash size from target. */
929 retval
= stm32x_get_flash_size(bank
, &flash_size_in_kb
);
931 /* failed reading flash size or flash size invalid (early silicon),
932 * default to max target family */
933 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
934 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
935 max_flash_size_in_kb
);
936 flash_size_in_kb
= max_flash_size_in_kb
;
939 if (stm32x_info
->has_dual_banks
) {
940 /* split reported size into matching bank */
941 if (bank
->base
!= 0x08080000) {
942 /* bank 0 will be fixed 512k */
943 flash_size_in_kb
= 512;
945 flash_size_in_kb
-= 512;
946 /* bank1 also uses a register offset */
947 stm32x_info
->register_base
= FLASH_REG_BASE_B1
;
948 base_address
= 0x08080000;
952 /* if the user sets the size manually then ignore the probed value
953 * this allows us to work around devices that have a invalid flash size register value */
954 if (stm32x_info
->user_bank_size
) {
955 LOG_INFO("ignoring flash probed value, using configured bank size");
956 flash_size_in_kb
= stm32x_info
->user_bank_size
/ 1024;
959 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
961 /* did we assign flash size? */
962 assert(flash_size_in_kb
!= 0xffff);
964 /* calculate numbers of pages */
965 int num_pages
= flash_size_in_kb
* 1024 / page_size
;
967 /* check that calculation result makes sense */
968 assert(num_pages
> 0);
972 bank
->sectors
= NULL
;
975 bank
->base
= base_address
;
976 bank
->size
= (num_pages
* page_size
);
977 bank
->num_sectors
= num_pages
;
978 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
980 for (i
= 0; i
< num_pages
; i
++) {
981 bank
->sectors
[i
].offset
= i
* page_size
;
982 bank
->sectors
[i
].size
= page_size
;
983 bank
->sectors
[i
].is_erased
= -1;
984 bank
->sectors
[i
].is_protected
= 1;
987 stm32x_info
->probed
= 1;
992 static int stm32x_auto_probe(struct flash_bank
*bank
)
994 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
995 if (stm32x_info
->probed
)
997 return stm32x_probe(bank
);
1001 COMMAND_HANDLER(stm32x_handle_part_id_command
)
1007 static const char *get_stm32f0_revision(uint16_t rev_id
)
1009 const char *rev_str
= NULL
;
1022 static int get_stm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1024 uint32_t dbgmcu_idcode
;
1026 /* read stm32 device id register */
1027 int retval
= stm32x_get_device_id(bank
, &dbgmcu_idcode
);
1028 if (retval
!= ERROR_OK
)
1031 uint16_t device_id
= dbgmcu_idcode
& 0xfff;
1032 uint16_t rev_id
= dbgmcu_idcode
>> 16;
1033 const char *device_str
;
1034 const char *rev_str
= NULL
;
1036 switch (device_id
) {
1038 device_str
= "STM32F10x (Medium Density)";
1060 device_str
= "STM32F10x (Low Density)";
1070 device_str
= "STM32F10x (High Density)";
1088 device_str
= "STM32F10x (Connectivity)";
1102 device_str
= "STM32F100 (Low/Medium Density)";
1116 device_str
= "STM32F302xB/C";
1138 device_str
= "STM32F100 (High Density)";
1152 device_str
= "STM32F10x (XL Density)";
1162 device_str
= "STM32F37x";
1176 device_str
= "STM32F33x";
1186 device_str
= "STM32F302x6/8";
1200 device_str
= "STM32F03x";
1201 rev_str
= get_stm32f0_revision(rev_id
);
1205 device_str
= "STM32F05x";
1206 rev_str
= get_stm32f0_revision(rev_id
);
1210 device_str
= "STM32F04x";
1211 rev_str
= get_stm32f0_revision(rev_id
);
1215 device_str
= "STM32F303xD/E";
1224 device_str
= "STM32F07x";
1225 rev_str
= get_stm32f0_revision(rev_id
);
1229 device_str
= "STM32F09x";
1230 rev_str
= get_stm32f0_revision(rev_id
);
1234 snprintf(buf
, buf_size
, "Cannot identify target as a STM32F0/1/3\n");
1238 if (rev_str
!= NULL
)
1239 snprintf(buf
, buf_size
, "%s - Rev: %s", device_str
, rev_str
);
1241 snprintf(buf
, buf_size
, "%s - Rev: unknown (0x%04x)", device_str
, rev_id
);
1246 COMMAND_HANDLER(stm32x_handle_lock_command
)
1248 struct target
*target
= NULL
;
1249 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1252 return ERROR_COMMAND_SYNTAX_ERROR
;
1254 struct flash_bank
*bank
;
1255 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1256 if (ERROR_OK
!= retval
)
1259 stm32x_info
= bank
->driver_priv
;
1261 target
= bank
->target
;
1263 if (target
->state
!= TARGET_HALTED
) {
1264 LOG_ERROR("Target not halted");
1265 return ERROR_TARGET_NOT_HALTED
;
1268 retval
= stm32x_check_operation_supported(bank
);
1269 if (ERROR_OK
!= retval
)
1272 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1273 command_print(CMD_CTX
, "stm32x failed to erase options");
1277 /* set readout protection */
1278 stm32x_info
->option_bytes
.RDP
= 0;
1280 if (stm32x_write_options(bank
) != ERROR_OK
) {
1281 command_print(CMD_CTX
, "stm32x failed to lock device");
1285 command_print(CMD_CTX
, "stm32x locked");
1290 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1292 struct target
*target
= NULL
;
1295 return ERROR_COMMAND_SYNTAX_ERROR
;
1297 struct flash_bank
*bank
;
1298 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1299 if (ERROR_OK
!= retval
)
1302 target
= bank
->target
;
1304 if (target
->state
!= TARGET_HALTED
) {
1305 LOG_ERROR("Target not halted");
1306 return ERROR_TARGET_NOT_HALTED
;
1309 retval
= stm32x_check_operation_supported(bank
);
1310 if (ERROR_OK
!= retval
)
1313 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1314 command_print(CMD_CTX
, "stm32x failed to unlock device");
1318 if (stm32x_write_options(bank
) != ERROR_OK
) {
1319 command_print(CMD_CTX
, "stm32x failed to lock device");
1323 command_print(CMD_CTX
, "stm32x unlocked.\n"
1324 "INFO: a reset or power cycle is required "
1325 "for the new settings to take effect.");
1330 COMMAND_HANDLER(stm32x_handle_options_read_command
)
1332 uint32_t optionbyte
;
1333 struct target
*target
= NULL
;
1334 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1337 return ERROR_COMMAND_SYNTAX_ERROR
;
1339 struct flash_bank
*bank
;
1340 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1341 if (ERROR_OK
!= retval
)
1344 stm32x_info
= bank
->driver_priv
;
1346 target
= bank
->target
;
1348 if (target
->state
!= TARGET_HALTED
) {
1349 LOG_ERROR("Target not halted");
1350 return ERROR_TARGET_NOT_HALTED
;
1353 retval
= stm32x_check_operation_supported(bank
);
1354 if (ERROR_OK
!= retval
)
1357 retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optionbyte
);
1358 if (retval
!= ERROR_OK
)
1360 command_print(CMD_CTX
, "Option Byte: 0x%" PRIx32
"", optionbyte
);
1362 int user_data
= optionbyte
;
1364 if (optionbyte
>> OPT_ERROR
& 1)
1365 command_print(CMD_CTX
, "Option Byte Complement Error");
1367 if (optionbyte
>> OPT_READOUT
& 1)
1368 command_print(CMD_CTX
, "Readout Protection On");
1370 command_print(CMD_CTX
, "Readout Protection Off");
1372 /* user option bytes are offset depending on variant */
1373 optionbyte
>>= stm32x_info
->option_offset
;
1375 if (optionbyte
>> OPT_RDWDGSW
& 1)
1376 command_print(CMD_CTX
, "Software Watchdog");
1378 command_print(CMD_CTX
, "Hardware Watchdog");
1380 if (optionbyte
>> OPT_RDRSTSTOP
& 1)
1381 command_print(CMD_CTX
, "Stop: No reset generated");
1383 command_print(CMD_CTX
, "Stop: Reset generated");
1385 if (optionbyte
>> OPT_RDRSTSTDBY
& 1)
1386 command_print(CMD_CTX
, "Standby: No reset generated");
1388 command_print(CMD_CTX
, "Standby: Reset generated");
1390 if (stm32x_info
->has_dual_banks
) {
1391 if (optionbyte
>> OPT_BFB2
& 1)
1392 command_print(CMD_CTX
, "Boot: Bank 0");
1394 command_print(CMD_CTX
, "Boot: Bank 1");
1397 command_print(CMD_CTX
, "User Option0: 0x%02" PRIx8
,
1398 (uint8_t)((user_data
>> stm32x_info
->user_data_offset
) & 0xff));
1399 command_print(CMD_CTX
, "User Option1: 0x%02" PRIx8
,
1400 (uint8_t)((user_data
>> (stm32x_info
->user_data_offset
+ 8)) & 0xff));
1405 COMMAND_HANDLER(stm32x_handle_options_write_command
)
1407 struct target
*target
= NULL
;
1408 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1409 uint16_t optionbyte
;
1412 return ERROR_COMMAND_SYNTAX_ERROR
;
1414 struct flash_bank
*bank
;
1415 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1416 if (ERROR_OK
!= retval
)
1419 stm32x_info
= bank
->driver_priv
;
1421 target
= bank
->target
;
1423 if (target
->state
!= TARGET_HALTED
) {
1424 LOG_ERROR("Target not halted");
1425 return ERROR_TARGET_NOT_HALTED
;
1428 retval
= stm32x_check_operation_supported(bank
);
1429 if (ERROR_OK
!= retval
)
1432 retval
= stm32x_read_options(bank
);
1433 if (ERROR_OK
!= retval
)
1436 /* start with current options */
1437 optionbyte
= stm32x_info
->option_bytes
.user_options
;
1439 /* skip over flash bank */
1444 if (strcmp("SWWDG", CMD_ARGV
[0]) == 0)
1445 optionbyte
|= (1 << 0);
1446 else if (strcmp("HWWDG", CMD_ARGV
[0]) == 0)
1447 optionbyte
&= ~(1 << 0);
1448 else if (strcmp("NORSTSTOP", CMD_ARGV
[0]) == 0)
1449 optionbyte
|= (1 << 1);
1450 else if (strcmp("RSTSTOP", CMD_ARGV
[0]) == 0)
1451 optionbyte
&= ~(1 << 1);
1452 else if (strcmp("NORSTSTNDBY", CMD_ARGV
[0]) == 0)
1453 optionbyte
|= (1 << 2);
1454 else if (strcmp("RSTSTNDBY", CMD_ARGV
[0]) == 0)
1455 optionbyte
&= ~(1 << 2);
1456 else if (stm32x_info
->has_dual_banks
) {
1457 if (strcmp("BOOT0", CMD_ARGV
[0]) == 0)
1458 optionbyte
|= (1 << 3);
1459 else if (strcmp("BOOT1", CMD_ARGV
[0]) == 0)
1460 optionbyte
&= ~(1 << 3);
1462 return ERROR_COMMAND_SYNTAX_ERROR
;
1464 return ERROR_COMMAND_SYNTAX_ERROR
;
1469 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1470 command_print(CMD_CTX
, "stm32x failed to erase options");
1474 stm32x_info
->option_bytes
.user_options
= optionbyte
;
1476 if (stm32x_write_options(bank
) != ERROR_OK
) {
1477 command_print(CMD_CTX
, "stm32x failed to write options");
1481 command_print(CMD_CTX
, "stm32x write options complete.\n"
1482 "INFO: a reset or power cycle is required "
1483 "for the new settings to take effect.");
1488 static int stm32x_mass_erase(struct flash_bank
*bank
)
1490 struct target
*target
= bank
->target
;
1492 if (target
->state
!= TARGET_HALTED
) {
1493 LOG_ERROR("Target not halted");
1494 return ERROR_TARGET_NOT_HALTED
;
1497 /* unlock option flash registers */
1498 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
1499 if (retval
!= ERROR_OK
)
1501 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
1502 if (retval
!= ERROR_OK
)
1505 /* mass erase flash memory */
1506 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_MER
);
1507 if (retval
!= ERROR_OK
)
1509 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
1510 FLASH_MER
| FLASH_STRT
);
1511 if (retval
!= ERROR_OK
)
1514 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1515 if (retval
!= ERROR_OK
)
1518 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
1519 if (retval
!= ERROR_OK
)
1525 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1530 return ERROR_COMMAND_SYNTAX_ERROR
;
1532 struct flash_bank
*bank
;
1533 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1534 if (ERROR_OK
!= retval
)
1537 retval
= stm32x_mass_erase(bank
);
1538 if (retval
== ERROR_OK
) {
1539 /* set all sectors as erased */
1540 for (i
= 0; i
< bank
->num_sectors
; i
++)
1541 bank
->sectors
[i
].is_erased
= 1;
1543 command_print(CMD_CTX
, "stm32x mass erase complete");
1545 command_print(CMD_CTX
, "stm32x mass erase failed");
1550 static const struct command_registration stm32x_exec_command_handlers
[] = {
1553 .handler
= stm32x_handle_lock_command
,
1554 .mode
= COMMAND_EXEC
,
1556 .help
= "Lock entire flash device.",
1560 .handler
= stm32x_handle_unlock_command
,
1561 .mode
= COMMAND_EXEC
,
1563 .help
= "Unlock entire protected flash device.",
1566 .name
= "mass_erase",
1567 .handler
= stm32x_handle_mass_erase_command
,
1568 .mode
= COMMAND_EXEC
,
1570 .help
= "Erase entire flash device.",
1573 .name
= "options_read",
1574 .handler
= stm32x_handle_options_read_command
,
1575 .mode
= COMMAND_EXEC
,
1577 .help
= "Read and display device option byte.",
1580 .name
= "options_write",
1581 .handler
= stm32x_handle_options_write_command
,
1582 .mode
= COMMAND_EXEC
,
1583 .usage
= "bank_id ('SWWDG'|'HWWDG') "
1584 "('RSTSTNDBY'|'NORSTSTNDBY') "
1585 "('RSTSTOP'|'NORSTSTOP')",
1586 .help
= "Replace bits in device option byte.",
1588 COMMAND_REGISTRATION_DONE
1591 static const struct command_registration stm32x_command_handlers
[] = {
1594 .mode
= COMMAND_ANY
,
1595 .help
= "stm32f1x flash command group",
1597 .chain
= stm32x_exec_command_handlers
,
1599 COMMAND_REGISTRATION_DONE
1602 struct flash_driver stm32f1x_flash
= {
1604 .commands
= stm32x_command_handlers
,
1605 .flash_bank_command
= stm32x_flash_bank_command
,
1606 .erase
= stm32x_erase
,
1607 .protect
= stm32x_protect
,
1608 .write
= stm32x_write
,
1609 .read
= default_flash_read
,
1610 .probe
= stm32x_probe
,
1611 .auto_probe
= stm32x_auto_probe
,
1612 .erase_check
= default_flash_blank_check
,
1613 .protect_check
= stm32x_protect_check
,
1614 .info
= get_stm32x_info
,
1615 .free_driver_priv
= default_flash_free_driver_priv
,
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