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flash/nor/stm32: Eliminate working area leak
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81
82 /* FLASH_SR register bits */
83
84 #define FLASH_BSY (1 << 0)
85 #define FLASH_PGERR (1 << 2)
86 #define FLASH_WRPRTERR (1 << 4)
87 #define FLASH_EOP (1 << 5)
88
89 /* STM32_FLASH_OBR bit definitions (reading) */
90
91 #define OPT_ERROR 0
92 #define OPT_READOUT 1
93 #define OPT_RDWDGSW 2
94 #define OPT_RDRSTSTOP 3
95 #define OPT_RDRSTSTDBY 4
96 #define OPT_BFB2 5 /* dual flash bank only */
97
98 /* register unlock keys */
99
100 #define KEY1 0x45670123
101 #define KEY2 0xCDEF89AB
102
103 /* timeout values */
104
105 #define FLASH_WRITE_TIMEOUT 10
106 #define FLASH_ERASE_TIMEOUT 100
107
108 struct stm32x_options {
109 uint16_t RDP;
110 uint16_t user_options;
111 uint16_t user_data;
112 uint16_t protection[4];
113 };
114
115 struct stm32x_flash_bank {
116 struct stm32x_options option_bytes;
117 int ppage_size;
118 int probed;
119
120 bool has_dual_banks;
121 /* used to access dual flash bank stm32xl */
122 uint32_t register_base;
123 uint16_t default_rdp;
124 int user_data_offset;
125 int option_offset;
126 uint32_t user_bank_size;
127 };
128
129 static int stm32x_mass_erase(struct flash_bank *bank);
130 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
131 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
132 uint32_t offset, uint32_t count);
133
134 /* flash bank stm32x <base> <size> 0 0 <target#>
135 */
136 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
137 {
138 struct stm32x_flash_bank *stm32x_info;
139
140 if (CMD_ARGC < 6)
141 return ERROR_COMMAND_SYNTAX_ERROR;
142
143 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
144
145 bank->driver_priv = stm32x_info;
146 stm32x_info->probed = 0;
147 stm32x_info->has_dual_banks = false;
148 stm32x_info->register_base = FLASH_REG_BASE_B0;
149 stm32x_info->user_bank_size = bank->size;
150
151 return ERROR_OK;
152 }
153
154 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
155 {
156 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
157 return reg + stm32x_info->register_base;
158 }
159
160 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
161 {
162 struct target *target = bank->target;
163 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
164 }
165
166 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
167 {
168 struct target *target = bank->target;
169 uint32_t status;
170 int retval = ERROR_OK;
171
172 /* wait for busy to clear */
173 for (;;) {
174 retval = stm32x_get_flash_status(bank, &status);
175 if (retval != ERROR_OK)
176 return retval;
177 LOG_DEBUG("status: 0x%" PRIx32 "", status);
178 if ((status & FLASH_BSY) == 0)
179 break;
180 if (timeout-- <= 0) {
181 LOG_ERROR("timed out waiting for flash");
182 return ERROR_FAIL;
183 }
184 alive_sleep(1);
185 }
186
187 if (status & FLASH_WRPRTERR) {
188 LOG_ERROR("stm32x device protected");
189 retval = ERROR_FAIL;
190 }
191
192 if (status & FLASH_PGERR) {
193 LOG_ERROR("stm32x device programming failed");
194 retval = ERROR_FAIL;
195 }
196
197 /* Clear but report errors */
198 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
199 /* If this operation fails, we ignore it and report the original
200 * retval
201 */
202 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
203 FLASH_WRPRTERR | FLASH_PGERR);
204 }
205 return retval;
206 }
207
208 static int stm32x_check_operation_supported(struct flash_bank *bank)
209 {
210 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
211
212 /* if we have a dual flash bank device then
213 * we need to perform option byte stuff on bank0 only */
214 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
215 LOG_ERROR("Option Byte Operation's must use bank0");
216 return ERROR_FLASH_OPERATION_FAILED;
217 }
218
219 return ERROR_OK;
220 }
221
222 static int stm32x_read_options(struct flash_bank *bank)
223 {
224 uint32_t optiondata;
225 struct stm32x_flash_bank *stm32x_info = NULL;
226 struct target *target = bank->target;
227
228 stm32x_info = bank->driver_priv;
229
230 /* read current option bytes */
231 int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
232 if (retval != ERROR_OK)
233 return retval;
234
235 stm32x_info->option_bytes.user_options = (optiondata >> stm32x_info->option_offset >> 2) & 0xffff;
236 stm32x_info->option_bytes.user_data = (optiondata >> stm32x_info->user_data_offset) & 0xffff;
237 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
238
239 if (optiondata & (1 << OPT_READOUT))
240 LOG_INFO("Device Security Bit Set");
241
242 /* each bit refers to a 4bank protection */
243 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
244 if (retval != ERROR_OK)
245 return retval;
246
247 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
248 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
249 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
250 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
251
252 return ERROR_OK;
253 }
254
255 static int stm32x_erase_options(struct flash_bank *bank)
256 {
257 struct stm32x_flash_bank *stm32x_info = NULL;
258 struct target *target = bank->target;
259
260 stm32x_info = bank->driver_priv;
261
262 /* read current options */
263 stm32x_read_options(bank);
264
265 /* unlock flash registers */
266 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
267 if (retval != ERROR_OK)
268 return retval;
269
270 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* unlock option flash registers */
275 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
276 if (retval != ERROR_OK)
277 return retval;
278 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
279 if (retval != ERROR_OK)
280 return retval;
281
282 /* erase option bytes */
283 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
284 if (retval != ERROR_OK)
285 return retval;
286 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
287 if (retval != ERROR_OK)
288 return retval;
289
290 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
291 if (retval != ERROR_OK)
292 return retval;
293
294 /* clear readout protection and complementary option bytes
295 * this will also force a device unlock if set */
296 stm32x_info->option_bytes.RDP = stm32x_info->default_rdp;
297
298 return ERROR_OK;
299 }
300
301 static int stm32x_write_options(struct flash_bank *bank)
302 {
303 struct stm32x_flash_bank *stm32x_info = NULL;
304 struct target *target = bank->target;
305
306 stm32x_info = bank->driver_priv;
307
308 /* unlock flash registers */
309 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
310 if (retval != ERROR_OK)
311 return retval;
312 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
313 if (retval != ERROR_OK)
314 return retval;
315
316 /* unlock option flash registers */
317 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
318 if (retval != ERROR_OK)
319 return retval;
320 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
321 if (retval != ERROR_OK)
322 return retval;
323
324 /* program option bytes */
325 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
326 if (retval != ERROR_OK)
327 return retval;
328
329 uint8_t opt_bytes[16];
330
331 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.RDP);
332 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user_options);
333 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.user_data & 0xff);
334 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.user_data >> 8) & 0xff);
335 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection[0]);
336 target_buffer_set_u16(target, opt_bytes + 10, stm32x_info->option_bytes.protection[1]);
337 target_buffer_set_u16(target, opt_bytes + 12, stm32x_info->option_bytes.protection[2]);
338 target_buffer_set_u16(target, opt_bytes + 14, stm32x_info->option_bytes.protection[3]);
339
340 uint32_t offset = STM32_OB_RDP - bank->base;
341 retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
342 if (retval != ERROR_OK) {
343 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
344 LOG_ERROR("working area required to erase options bytes");
345 return retval;
346 }
347
348 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
349 if (retval != ERROR_OK)
350 return retval;
351
352 return ERROR_OK;
353 }
354
355 static int stm32x_protect_check(struct flash_bank *bank)
356 {
357 struct target *target = bank->target;
358 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
359
360 uint32_t protection;
361 int i, s;
362 int num_bits;
363 int set;
364
365 int retval = stm32x_check_operation_supported(bank);
366 if (ERROR_OK != retval)
367 return retval;
368
369 /* medium density - each bit refers to a 4bank protection
370 * high density - each bit refers to a 2bank protection */
371 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
372 if (retval != ERROR_OK)
373 return retval;
374
375 /* medium density - each protection bit is for 4 * 1K pages
376 * high density - each protection bit is for 2 * 2K pages */
377 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
378
379 if (stm32x_info->ppage_size == 2) {
380 /* high density flash/connectivity line protection */
381
382 set = 1;
383
384 if (protection & (1 << 31))
385 set = 0;
386
387 /* bit 31 controls sector 62 - 255 protection for high density
388 * bit 31 controls sector 62 - 127 protection for connectivity line */
389 for (s = 62; s < bank->num_sectors; s++)
390 bank->sectors[s].is_protected = set;
391
392 if (bank->num_sectors > 61)
393 num_bits = 31;
394
395 for (i = 0; i < num_bits; i++) {
396 set = 1;
397
398 if (protection & (1 << i))
399 set = 0;
400
401 for (s = 0; s < stm32x_info->ppage_size; s++)
402 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
403 }
404 } else {
405 /* low/medium density flash protection */
406 for (i = 0; i < num_bits; i++) {
407 set = 1;
408
409 if (protection & (1 << i))
410 set = 0;
411
412 for (s = 0; s < stm32x_info->ppage_size; s++)
413 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
414 }
415 }
416
417 return ERROR_OK;
418 }
419
420 static int stm32x_erase(struct flash_bank *bank, int first, int last)
421 {
422 struct target *target = bank->target;
423 int i;
424
425 if (bank->target->state != TARGET_HALTED) {
426 LOG_ERROR("Target not halted");
427 return ERROR_TARGET_NOT_HALTED;
428 }
429
430 if ((first == 0) && (last == (bank->num_sectors - 1)))
431 return stm32x_mass_erase(bank);
432
433 /* unlock flash registers */
434 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
435 if (retval != ERROR_OK)
436 return retval;
437 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
438 if (retval != ERROR_OK)
439 return retval;
440
441 for (i = first; i <= last; i++) {
442 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
443 if (retval != ERROR_OK)
444 return retval;
445 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
446 bank->base + bank->sectors[i].offset);
447 if (retval != ERROR_OK)
448 return retval;
449 retval = target_write_u32(target,
450 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
451 if (retval != ERROR_OK)
452 return retval;
453
454 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
455 if (retval != ERROR_OK)
456 return retval;
457
458 bank->sectors[i].is_erased = 1;
459 }
460
461 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
462 if (retval != ERROR_OK)
463 return retval;
464
465 return ERROR_OK;
466 }
467
468 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
469 {
470 struct stm32x_flash_bank *stm32x_info = NULL;
471 struct target *target = bank->target;
472 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
473 int i, reg, bit;
474 int status;
475 uint32_t protection;
476
477 stm32x_info = bank->driver_priv;
478
479 if (target->state != TARGET_HALTED) {
480 LOG_ERROR("Target not halted");
481 return ERROR_TARGET_NOT_HALTED;
482 }
483
484 int retval = stm32x_check_operation_supported(bank);
485 if (ERROR_OK != retval)
486 return retval;
487
488 if ((first % stm32x_info->ppage_size) != 0) {
489 LOG_WARNING("aligned start protect sector to a %d sector boundary",
490 stm32x_info->ppage_size);
491 first = first - (first % stm32x_info->ppage_size);
492 }
493 if (((last + 1) % stm32x_info->ppage_size) != 0) {
494 LOG_WARNING("aligned end protect sector to a %d sector boundary",
495 stm32x_info->ppage_size);
496 last++;
497 last = last - (last % stm32x_info->ppage_size);
498 last--;
499 }
500
501 /* medium density - each bit refers to a 4bank protection
502 * high density - each bit refers to a 2bank protection */
503 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
504 if (retval != ERROR_OK)
505 return retval;
506
507 prot_reg[0] = (uint16_t)protection;
508 prot_reg[1] = (uint16_t)(protection >> 8);
509 prot_reg[2] = (uint16_t)(protection >> 16);
510 prot_reg[3] = (uint16_t)(protection >> 24);
511
512 if (stm32x_info->ppage_size == 2) {
513 /* high density flash */
514
515 /* bit 7 controls sector 62 - 255 protection */
516 if (last > 61) {
517 if (set)
518 prot_reg[3] &= ~(1 << 7);
519 else
520 prot_reg[3] |= (1 << 7);
521 }
522
523 if (first > 61)
524 first = 62;
525 if (last > 61)
526 last = 61;
527
528 for (i = first; i <= last; i++) {
529 reg = (i / stm32x_info->ppage_size) / 8;
530 bit = (i / stm32x_info->ppage_size) - (reg * 8);
531
532 if (set)
533 prot_reg[reg] &= ~(1 << bit);
534 else
535 prot_reg[reg] |= (1 << bit);
536 }
537 } else {
538 /* medium density flash */
539 for (i = first; i <= last; i++) {
540 reg = (i / stm32x_info->ppage_size) / 8;
541 bit = (i / stm32x_info->ppage_size) - (reg * 8);
542
543 if (set)
544 prot_reg[reg] &= ~(1 << bit);
545 else
546 prot_reg[reg] |= (1 << bit);
547 }
548 }
549
550 status = stm32x_erase_options(bank);
551 if (status != ERROR_OK)
552 return status;
553
554 stm32x_info->option_bytes.protection[0] = prot_reg[0];
555 stm32x_info->option_bytes.protection[1] = prot_reg[1];
556 stm32x_info->option_bytes.protection[2] = prot_reg[2];
557 stm32x_info->option_bytes.protection[3] = prot_reg[3];
558
559 return stm32x_write_options(bank);
560 }
561
562 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
563 uint32_t offset, uint32_t count)
564 {
565 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
566 struct target *target = bank->target;
567 uint32_t buffer_size = 16384;
568 struct working_area *write_algorithm;
569 struct working_area *source;
570 uint32_t address = bank->base + offset;
571 struct reg_param reg_params[5];
572 struct armv7m_algorithm armv7m_info;
573 int retval = ERROR_OK;
574
575 static const uint8_t stm32x_flash_write_code[] = {
576 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
577 };
578
579 /* flash write code */
580 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
581 &write_algorithm) != ERROR_OK) {
582 LOG_WARNING("no working area available, can't do block memory writes");
583 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
584 }
585
586 retval = target_write_buffer(target, write_algorithm->address,
587 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
588 if (retval != ERROR_OK) {
589 target_free_working_area(target, write_algorithm);
590 return retval;
591 }
592
593 /* memory buffer */
594 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
595 buffer_size /= 2;
596 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
597 if (buffer_size <= 256) {
598 /* we already allocated the writing code, but failed to get a
599 * buffer, free the algorithm */
600 target_free_working_area(target, write_algorithm);
601
602 LOG_WARNING("no large enough working area available, can't do block memory writes");
603 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
604 }
605 }
606
607 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
608 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
609 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
610 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
611 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
612
613 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
614 buf_set_u32(reg_params[1].value, 0, 32, count);
615 buf_set_u32(reg_params[2].value, 0, 32, source->address);
616 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
617 buf_set_u32(reg_params[4].value, 0, 32, address);
618
619 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
620 armv7m_info.core_mode = ARM_MODE_THREAD;
621
622 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
623 0, NULL,
624 5, reg_params,
625 source->address, source->size,
626 write_algorithm->address, 0,
627 &armv7m_info);
628
629 if (retval == ERROR_FLASH_OPERATION_FAILED) {
630 LOG_ERROR("flash write failed at address 0x%"PRIx32,
631 buf_get_u32(reg_params[4].value, 0, 32));
632
633 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
634 LOG_ERROR("flash memory not erased before writing");
635 /* Clear but report errors */
636 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
637 }
638
639 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
640 LOG_ERROR("flash memory write protected");
641 /* Clear but report errors */
642 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
643 }
644 }
645
646 target_free_working_area(target, source);
647 target_free_working_area(target, write_algorithm);
648
649 destroy_reg_param(&reg_params[0]);
650 destroy_reg_param(&reg_params[1]);
651 destroy_reg_param(&reg_params[2]);
652 destroy_reg_param(&reg_params[3]);
653 destroy_reg_param(&reg_params[4]);
654
655 return retval;
656 }
657
658 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
659 uint32_t offset, uint32_t count)
660 {
661 struct target *target = bank->target;
662 uint8_t *new_buffer = NULL;
663
664 if (bank->target->state != TARGET_HALTED) {
665 LOG_ERROR("Target not halted");
666 return ERROR_TARGET_NOT_HALTED;
667 }
668
669 if (offset & 0x1) {
670 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
671 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
672 }
673
674 /* If there's an odd number of bytes, the data has to be padded. Duplicate
675 * the buffer and use the normal code path with a single block write since
676 * it's probably cheaper than to special case the last odd write using
677 * discrete accesses. */
678 if (count & 1) {
679 new_buffer = malloc(count + 1);
680 if (new_buffer == NULL) {
681 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
682 return ERROR_FAIL;
683 }
684 LOG_INFO("odd number of bytes to write, padding with 0xff");
685 buffer = memcpy(new_buffer, buffer, count);
686 new_buffer[count++] = 0xff;
687 }
688
689 uint32_t words_remaining = count / 2;
690 int retval, retval2;
691
692 /* unlock flash registers */
693 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
694 if (retval != ERROR_OK)
695 goto cleanup;
696 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
697 if (retval != ERROR_OK)
698 goto cleanup;
699
700 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
701 if (retval != ERROR_OK)
702 goto cleanup;
703
704 /* try using a block write */
705 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
706
707 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
708 /* if block write failed (no sufficient working area),
709 * we use normal (slow) single halfword accesses */
710 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
711
712 while (words_remaining > 0) {
713 uint16_t value;
714 memcpy(&value, buffer, sizeof(uint16_t));
715
716 retval = target_write_u16(target, bank->base + offset, value);
717 if (retval != ERROR_OK)
718 goto reset_pg_and_lock;
719
720 retval = stm32x_wait_status_busy(bank, 5);
721 if (retval != ERROR_OK)
722 goto reset_pg_and_lock;
723
724 words_remaining--;
725 buffer += 2;
726 offset += 2;
727 }
728 }
729
730 reset_pg_and_lock:
731 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
732 if (retval == ERROR_OK)
733 retval = retval2;
734
735 cleanup:
736 if (new_buffer)
737 free(new_buffer);
738
739 return retval;
740 }
741
742 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
743 {
744 /* This check the device CPUID core register to detect
745 * the M0 from the M3 devices. */
746
747 struct target *target = bank->target;
748 uint32_t cpuid, device_id_register = 0;
749
750 /* Get the CPUID from the ARM Core
751 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
752 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
753 if (retval != ERROR_OK)
754 return retval;
755
756 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
757 /* 0xC20 is M0 devices */
758 device_id_register = 0x40015800;
759 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
760 /* 0xC23 is M3 devices */
761 device_id_register = 0xE0042000;
762 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
763 /* 0xC24 is M4 devices */
764 device_id_register = 0xE0042000;
765 } else {
766 LOG_ERROR("Cannot identify target as a stm32x");
767 return ERROR_FAIL;
768 }
769
770 /* read stm32 device id register */
771 retval = target_read_u32(target, device_id_register, device_id);
772 if (retval != ERROR_OK)
773 return retval;
774
775 return retval;
776 }
777
778 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
779 {
780 struct target *target = bank->target;
781 uint32_t cpuid, flash_size_reg;
782
783 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
784 if (retval != ERROR_OK)
785 return retval;
786
787 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
788 /* 0xC20 is M0 devices */
789 flash_size_reg = 0x1FFFF7CC;
790 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
791 /* 0xC23 is M3 devices */
792 flash_size_reg = 0x1FFFF7E0;
793 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
794 /* 0xC24 is M4 devices */
795 flash_size_reg = 0x1FFFF7CC;
796 } else {
797 LOG_ERROR("Cannot identify target as a stm32x");
798 return ERROR_FAIL;
799 }
800
801 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
802 if (retval != ERROR_OK)
803 return retval;
804
805 return retval;
806 }
807
808 static int stm32x_probe(struct flash_bank *bank)
809 {
810 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
811 int i;
812 uint16_t flash_size_in_kb;
813 uint16_t max_flash_size_in_kb;
814 uint32_t device_id;
815 int page_size;
816 uint32_t base_address = 0x08000000;
817
818 stm32x_info->probed = 0;
819 stm32x_info->register_base = FLASH_REG_BASE_B0;
820 stm32x_info->user_data_offset = 10;
821 stm32x_info->option_offset = 0;
822
823 /* default factory protection level */
824 stm32x_info->default_rdp = 0x5AA5;
825
826 /* read stm32 device id register */
827 int retval = stm32x_get_device_id(bank, &device_id);
828 if (retval != ERROR_OK)
829 return retval;
830
831 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
832
833 /* set page size, protection granularity and max flash size depending on family */
834 switch (device_id & 0xfff) {
835 case 0x410: /* medium density */
836 page_size = 1024;
837 stm32x_info->ppage_size = 4;
838 max_flash_size_in_kb = 128;
839 break;
840 case 0x412: /* low density */
841 page_size = 1024;
842 stm32x_info->ppage_size = 4;
843 max_flash_size_in_kb = 32;
844 break;
845 case 0x414: /* high density */
846 page_size = 2048;
847 stm32x_info->ppage_size = 2;
848 max_flash_size_in_kb = 512;
849 break;
850 case 0x418: /* connectivity line density */
851 page_size = 2048;
852 stm32x_info->ppage_size = 2;
853 max_flash_size_in_kb = 256;
854 break;
855 case 0x420: /* value line density */
856 page_size = 1024;
857 stm32x_info->ppage_size = 4;
858 max_flash_size_in_kb = 128;
859 break;
860 case 0x422: /* stm32f302/3xb/c */
861 page_size = 2048;
862 stm32x_info->ppage_size = 2;
863 max_flash_size_in_kb = 256;
864 stm32x_info->user_data_offset = 16;
865 stm32x_info->option_offset = 6;
866 stm32x_info->default_rdp = 0x55AA;
867 break;
868 case 0x446: /* stm32f303xD/E */
869 page_size = 2048;
870 stm32x_info->ppage_size = 2;
871 max_flash_size_in_kb = 512;
872 stm32x_info->user_data_offset = 16;
873 stm32x_info->option_offset = 6;
874 stm32x_info->default_rdp = 0x55AA;
875 break;
876 case 0x428: /* value line High density */
877 page_size = 2048;
878 stm32x_info->ppage_size = 4;
879 max_flash_size_in_kb = 128;
880 break;
881 case 0x430: /* xl line density (dual flash banks) */
882 page_size = 2048;
883 stm32x_info->ppage_size = 2;
884 max_flash_size_in_kb = 1024;
885 stm32x_info->has_dual_banks = true;
886 break;
887 case 0x432: /* stm32f37x */
888 page_size = 2048;
889 stm32x_info->ppage_size = 2;
890 max_flash_size_in_kb = 256;
891 stm32x_info->user_data_offset = 16;
892 stm32x_info->option_offset = 6;
893 stm32x_info->default_rdp = 0x55AA;
894 break;
895 case 0x438: /* stm32f33x */
896 case 0x439: /* stm32f302x6/8 */
897 page_size = 2048;
898 stm32x_info->ppage_size = 2;
899 max_flash_size_in_kb = 64;
900 stm32x_info->user_data_offset = 16;
901 stm32x_info->option_offset = 6;
902 stm32x_info->default_rdp = 0x55AA;
903 break;
904 case 0x440: /* stm32f05x */
905 case 0x444: /* stm32f03x */
906 case 0x445: /* stm32f04x */
907 page_size = 1024;
908 stm32x_info->ppage_size = 4;
909 max_flash_size_in_kb = 64;
910 stm32x_info->user_data_offset = 16;
911 stm32x_info->option_offset = 6;
912 stm32x_info->default_rdp = 0x55AA;
913 break;
914 case 0x448: /* stm32f07x */
915 case 0x442: /* stm32f09x */
916 page_size = 2048;
917 stm32x_info->ppage_size = 4;
918 max_flash_size_in_kb = 256;
919 stm32x_info->user_data_offset = 16;
920 stm32x_info->option_offset = 6;
921 stm32x_info->default_rdp = 0x55AA;
922 break;
923 default:
924 LOG_WARNING("Cannot identify target as a STM32 family.");
925 return ERROR_FAIL;
926 }
927
928 /* get flash size from target. */
929 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
930
931 /* failed reading flash size or flash size invalid (early silicon),
932 * default to max target family */
933 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
934 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
935 max_flash_size_in_kb);
936 flash_size_in_kb = max_flash_size_in_kb;
937 }
938
939 if (stm32x_info->has_dual_banks) {
940 /* split reported size into matching bank */
941 if (bank->base != 0x08080000) {
942 /* bank 0 will be fixed 512k */
943 flash_size_in_kb = 512;
944 } else {
945 flash_size_in_kb -= 512;
946 /* bank1 also uses a register offset */
947 stm32x_info->register_base = FLASH_REG_BASE_B1;
948 base_address = 0x08080000;
949 }
950 }
951
952 /* if the user sets the size manually then ignore the probed value
953 * this allows us to work around devices that have a invalid flash size register value */
954 if (stm32x_info->user_bank_size) {
955 LOG_INFO("ignoring flash probed value, using configured bank size");
956 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
957 }
958
959 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
960
961 /* did we assign flash size? */
962 assert(flash_size_in_kb != 0xffff);
963
964 /* calculate numbers of pages */
965 int num_pages = flash_size_in_kb * 1024 / page_size;
966
967 /* check that calculation result makes sense */
968 assert(num_pages > 0);
969
970 if (bank->sectors) {
971 free(bank->sectors);
972 bank->sectors = NULL;
973 }
974
975 bank->base = base_address;
976 bank->size = (num_pages * page_size);
977 bank->num_sectors = num_pages;
978 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
979
980 for (i = 0; i < num_pages; i++) {
981 bank->sectors[i].offset = i * page_size;
982 bank->sectors[i].size = page_size;
983 bank->sectors[i].is_erased = -1;
984 bank->sectors[i].is_protected = 1;
985 }
986
987 stm32x_info->probed = 1;
988
989 return ERROR_OK;
990 }
991
992 static int stm32x_auto_probe(struct flash_bank *bank)
993 {
994 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
995 if (stm32x_info->probed)
996 return ERROR_OK;
997 return stm32x_probe(bank);
998 }
999
1000 #if 0
1001 COMMAND_HANDLER(stm32x_handle_part_id_command)
1002 {
1003 return ERROR_OK;
1004 }
1005 #endif
1006
1007 static const char *get_stm32f0_revision(uint16_t rev_id)
1008 {
1009 const char *rev_str = NULL;
1010
1011 switch (rev_id) {
1012 case 0x1000:
1013 rev_str = "1.0";
1014 break;
1015 case 0x2000:
1016 rev_str = "2.0";
1017 break;
1018 }
1019 return rev_str;
1020 }
1021
1022 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1023 {
1024 uint32_t dbgmcu_idcode;
1025
1026 /* read stm32 device id register */
1027 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1028 if (retval != ERROR_OK)
1029 return retval;
1030
1031 uint16_t device_id = dbgmcu_idcode & 0xfff;
1032 uint16_t rev_id = dbgmcu_idcode >> 16;
1033 const char *device_str;
1034 const char *rev_str = NULL;
1035
1036 switch (device_id) {
1037 case 0x410:
1038 device_str = "STM32F10x (Medium Density)";
1039
1040 switch (rev_id) {
1041 case 0x0000:
1042 rev_str = "A";
1043 break;
1044
1045 case 0x2000:
1046 rev_str = "B";
1047 break;
1048
1049 case 0x2001:
1050 rev_str = "Z";
1051 break;
1052
1053 case 0x2003:
1054 rev_str = "Y";
1055 break;
1056 }
1057 break;
1058
1059 case 0x412:
1060 device_str = "STM32F10x (Low Density)";
1061
1062 switch (rev_id) {
1063 case 0x1000:
1064 rev_str = "A";
1065 break;
1066 }
1067 break;
1068
1069 case 0x414:
1070 device_str = "STM32F10x (High Density)";
1071
1072 switch (rev_id) {
1073 case 0x1000:
1074 rev_str = "A";
1075 break;
1076
1077 case 0x1001:
1078 rev_str = "Z";
1079 break;
1080
1081 case 0x1003:
1082 rev_str = "Y";
1083 break;
1084 }
1085 break;
1086
1087 case 0x418:
1088 device_str = "STM32F10x (Connectivity)";
1089
1090 switch (rev_id) {
1091 case 0x1000:
1092 rev_str = "A";
1093 break;
1094
1095 case 0x1001:
1096 rev_str = "Z";
1097 break;
1098 }
1099 break;
1100
1101 case 0x420:
1102 device_str = "STM32F100 (Low/Medium Density)";
1103
1104 switch (rev_id) {
1105 case 0x1000:
1106 rev_str = "A";
1107 break;
1108
1109 case 0x1001:
1110 rev_str = "Z";
1111 break;
1112 }
1113 break;
1114
1115 case 0x422:
1116 device_str = "STM32F302xB/C";
1117
1118 switch (rev_id) {
1119 case 0x1000:
1120 rev_str = "A";
1121 break;
1122
1123 case 0x1001:
1124 rev_str = "Z";
1125 break;
1126
1127 case 0x1003:
1128 rev_str = "Y";
1129 break;
1130
1131 case 0x2000:
1132 rev_str = "B";
1133 break;
1134 }
1135 break;
1136
1137 case 0x428:
1138 device_str = "STM32F100 (High Density)";
1139
1140 switch (rev_id) {
1141 case 0x1000:
1142 rev_str = "A";
1143 break;
1144
1145 case 0x1001:
1146 rev_str = "Z";
1147 break;
1148 }
1149 break;
1150
1151 case 0x430:
1152 device_str = "STM32F10x (XL Density)";
1153
1154 switch (rev_id) {
1155 case 0x1000:
1156 rev_str = "A";
1157 break;
1158 }
1159 break;
1160
1161 case 0x432:
1162 device_str = "STM32F37x";
1163
1164 switch (rev_id) {
1165 case 0x1000:
1166 rev_str = "A";
1167 break;
1168
1169 case 0x2000:
1170 rev_str = "B";
1171 break;
1172 }
1173 break;
1174
1175 case 0x438:
1176 device_str = "STM32F33x";
1177
1178 switch (rev_id) {
1179 case 0x1000:
1180 rev_str = "A";
1181 break;
1182 }
1183 break;
1184
1185 case 0x439:
1186 device_str = "STM32F302x6/8";
1187
1188 switch (rev_id) {
1189 case 0x1000:
1190 rev_str = "A";
1191 break;
1192
1193 case 0x1001:
1194 rev_str = "Z";
1195 break;
1196 }
1197 break;
1198
1199 case 0x444:
1200 device_str = "STM32F03x";
1201 rev_str = get_stm32f0_revision(rev_id);
1202 break;
1203
1204 case 0x440:
1205 device_str = "STM32F05x";
1206 rev_str = get_stm32f0_revision(rev_id);
1207 break;
1208
1209 case 0x445:
1210 device_str = "STM32F04x";
1211 rev_str = get_stm32f0_revision(rev_id);
1212 break;
1213
1214 case 0x446:
1215 device_str = "STM32F303xD/E";
1216 switch (rev_id) {
1217 case 0x1000:
1218 rev_str = "A";
1219 break;
1220 }
1221 break;
1222
1223 case 0x448:
1224 device_str = "STM32F07x";
1225 rev_str = get_stm32f0_revision(rev_id);
1226 break;
1227
1228 case 0x442:
1229 device_str = "STM32F09x";
1230 rev_str = get_stm32f0_revision(rev_id);
1231 break;
1232
1233 default:
1234 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1235 return ERROR_FAIL;
1236 }
1237
1238 if (rev_str != NULL)
1239 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1240 else
1241 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1242
1243 return ERROR_OK;
1244 }
1245
1246 COMMAND_HANDLER(stm32x_handle_lock_command)
1247 {
1248 struct target *target = NULL;
1249 struct stm32x_flash_bank *stm32x_info = NULL;
1250
1251 if (CMD_ARGC < 1)
1252 return ERROR_COMMAND_SYNTAX_ERROR;
1253
1254 struct flash_bank *bank;
1255 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1256 if (ERROR_OK != retval)
1257 return retval;
1258
1259 stm32x_info = bank->driver_priv;
1260
1261 target = bank->target;
1262
1263 if (target->state != TARGET_HALTED) {
1264 LOG_ERROR("Target not halted");
1265 return ERROR_TARGET_NOT_HALTED;
1266 }
1267
1268 retval = stm32x_check_operation_supported(bank);
1269 if (ERROR_OK != retval)
1270 return retval;
1271
1272 if (stm32x_erase_options(bank) != ERROR_OK) {
1273 command_print(CMD_CTX, "stm32x failed to erase options");
1274 return ERROR_OK;
1275 }
1276
1277 /* set readout protection */
1278 stm32x_info->option_bytes.RDP = 0;
1279
1280 if (stm32x_write_options(bank) != ERROR_OK) {
1281 command_print(CMD_CTX, "stm32x failed to lock device");
1282 return ERROR_OK;
1283 }
1284
1285 command_print(CMD_CTX, "stm32x locked");
1286
1287 return ERROR_OK;
1288 }
1289
1290 COMMAND_HANDLER(stm32x_handle_unlock_command)
1291 {
1292 struct target *target = NULL;
1293
1294 if (CMD_ARGC < 1)
1295 return ERROR_COMMAND_SYNTAX_ERROR;
1296
1297 struct flash_bank *bank;
1298 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1299 if (ERROR_OK != retval)
1300 return retval;
1301
1302 target = bank->target;
1303
1304 if (target->state != TARGET_HALTED) {
1305 LOG_ERROR("Target not halted");
1306 return ERROR_TARGET_NOT_HALTED;
1307 }
1308
1309 retval = stm32x_check_operation_supported(bank);
1310 if (ERROR_OK != retval)
1311 return retval;
1312
1313 if (stm32x_erase_options(bank) != ERROR_OK) {
1314 command_print(CMD_CTX, "stm32x failed to unlock device");
1315 return ERROR_OK;
1316 }
1317
1318 if (stm32x_write_options(bank) != ERROR_OK) {
1319 command_print(CMD_CTX, "stm32x failed to lock device");
1320 return ERROR_OK;
1321 }
1322
1323 command_print(CMD_CTX, "stm32x unlocked.\n"
1324 "INFO: a reset or power cycle is required "
1325 "for the new settings to take effect.");
1326
1327 return ERROR_OK;
1328 }
1329
1330 COMMAND_HANDLER(stm32x_handle_options_read_command)
1331 {
1332 uint32_t optionbyte;
1333 struct target *target = NULL;
1334 struct stm32x_flash_bank *stm32x_info = NULL;
1335
1336 if (CMD_ARGC < 1)
1337 return ERROR_COMMAND_SYNTAX_ERROR;
1338
1339 struct flash_bank *bank;
1340 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1341 if (ERROR_OK != retval)
1342 return retval;
1343
1344 stm32x_info = bank->driver_priv;
1345
1346 target = bank->target;
1347
1348 if (target->state != TARGET_HALTED) {
1349 LOG_ERROR("Target not halted");
1350 return ERROR_TARGET_NOT_HALTED;
1351 }
1352
1353 retval = stm32x_check_operation_supported(bank);
1354 if (ERROR_OK != retval)
1355 return retval;
1356
1357 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1358 if (retval != ERROR_OK)
1359 return retval;
1360 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1361
1362 int user_data = optionbyte;
1363
1364 if (optionbyte >> OPT_ERROR & 1)
1365 command_print(CMD_CTX, "Option Byte Complement Error");
1366
1367 if (optionbyte >> OPT_READOUT & 1)
1368 command_print(CMD_CTX, "Readout Protection On");
1369 else
1370 command_print(CMD_CTX, "Readout Protection Off");
1371
1372 /* user option bytes are offset depending on variant */
1373 optionbyte >>= stm32x_info->option_offset;
1374
1375 if (optionbyte >> OPT_RDWDGSW & 1)
1376 command_print(CMD_CTX, "Software Watchdog");
1377 else
1378 command_print(CMD_CTX, "Hardware Watchdog");
1379
1380 if (optionbyte >> OPT_RDRSTSTOP & 1)
1381 command_print(CMD_CTX, "Stop: No reset generated");
1382 else
1383 command_print(CMD_CTX, "Stop: Reset generated");
1384
1385 if (optionbyte >> OPT_RDRSTSTDBY & 1)
1386 command_print(CMD_CTX, "Standby: No reset generated");
1387 else
1388 command_print(CMD_CTX, "Standby: Reset generated");
1389
1390 if (stm32x_info->has_dual_banks) {
1391 if (optionbyte >> OPT_BFB2 & 1)
1392 command_print(CMD_CTX, "Boot: Bank 0");
1393 else
1394 command_print(CMD_CTX, "Boot: Bank 1");
1395 }
1396
1397 command_print(CMD_CTX, "User Option0: 0x%02" PRIx8,
1398 (uint8_t)((user_data >> stm32x_info->user_data_offset) & 0xff));
1399 command_print(CMD_CTX, "User Option1: 0x%02" PRIx8,
1400 (uint8_t)((user_data >> (stm32x_info->user_data_offset + 8)) & 0xff));
1401
1402 return ERROR_OK;
1403 }
1404
1405 COMMAND_HANDLER(stm32x_handle_options_write_command)
1406 {
1407 struct target *target = NULL;
1408 struct stm32x_flash_bank *stm32x_info = NULL;
1409 uint16_t optionbyte;
1410
1411 if (CMD_ARGC < 2)
1412 return ERROR_COMMAND_SYNTAX_ERROR;
1413
1414 struct flash_bank *bank;
1415 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1416 if (ERROR_OK != retval)
1417 return retval;
1418
1419 stm32x_info = bank->driver_priv;
1420
1421 target = bank->target;
1422
1423 if (target->state != TARGET_HALTED) {
1424 LOG_ERROR("Target not halted");
1425 return ERROR_TARGET_NOT_HALTED;
1426 }
1427
1428 retval = stm32x_check_operation_supported(bank);
1429 if (ERROR_OK != retval)
1430 return retval;
1431
1432 retval = stm32x_read_options(bank);
1433 if (ERROR_OK != retval)
1434 return retval;
1435
1436 /* start with current options */
1437 optionbyte = stm32x_info->option_bytes.user_options;
1438
1439 /* skip over flash bank */
1440 CMD_ARGC--;
1441 CMD_ARGV++;
1442
1443 while (CMD_ARGC) {
1444 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1445 optionbyte |= (1 << 0);
1446 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1447 optionbyte &= ~(1 << 0);
1448 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1449 optionbyte |= (1 << 1);
1450 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1451 optionbyte &= ~(1 << 1);
1452 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1453 optionbyte |= (1 << 2);
1454 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1455 optionbyte &= ~(1 << 2);
1456 else if (stm32x_info->has_dual_banks) {
1457 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1458 optionbyte |= (1 << 3);
1459 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1460 optionbyte &= ~(1 << 3);
1461 else
1462 return ERROR_COMMAND_SYNTAX_ERROR;
1463 } else
1464 return ERROR_COMMAND_SYNTAX_ERROR;
1465 CMD_ARGC--;
1466 CMD_ARGV++;
1467 }
1468
1469 if (stm32x_erase_options(bank) != ERROR_OK) {
1470 command_print(CMD_CTX, "stm32x failed to erase options");
1471 return ERROR_OK;
1472 }
1473
1474 stm32x_info->option_bytes.user_options = optionbyte;
1475
1476 if (stm32x_write_options(bank) != ERROR_OK) {
1477 command_print(CMD_CTX, "stm32x failed to write options");
1478 return ERROR_OK;
1479 }
1480
1481 command_print(CMD_CTX, "stm32x write options complete.\n"
1482 "INFO: a reset or power cycle is required "
1483 "for the new settings to take effect.");
1484
1485 return ERROR_OK;
1486 }
1487
1488 static int stm32x_mass_erase(struct flash_bank *bank)
1489 {
1490 struct target *target = bank->target;
1491
1492 if (target->state != TARGET_HALTED) {
1493 LOG_ERROR("Target not halted");
1494 return ERROR_TARGET_NOT_HALTED;
1495 }
1496
1497 /* unlock option flash registers */
1498 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1499 if (retval != ERROR_OK)
1500 return retval;
1501 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1502 if (retval != ERROR_OK)
1503 return retval;
1504
1505 /* mass erase flash memory */
1506 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1507 if (retval != ERROR_OK)
1508 return retval;
1509 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1510 FLASH_MER | FLASH_STRT);
1511 if (retval != ERROR_OK)
1512 return retval;
1513
1514 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1515 if (retval != ERROR_OK)
1516 return retval;
1517
1518 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1519 if (retval != ERROR_OK)
1520 return retval;
1521
1522 return ERROR_OK;
1523 }
1524
1525 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1526 {
1527 int i;
1528
1529 if (CMD_ARGC < 1)
1530 return ERROR_COMMAND_SYNTAX_ERROR;
1531
1532 struct flash_bank *bank;
1533 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1534 if (ERROR_OK != retval)
1535 return retval;
1536
1537 retval = stm32x_mass_erase(bank);
1538 if (retval == ERROR_OK) {
1539 /* set all sectors as erased */
1540 for (i = 0; i < bank->num_sectors; i++)
1541 bank->sectors[i].is_erased = 1;
1542
1543 command_print(CMD_CTX, "stm32x mass erase complete");
1544 } else
1545 command_print(CMD_CTX, "stm32x mass erase failed");
1546
1547 return retval;
1548 }
1549
1550 static const struct command_registration stm32x_exec_command_handlers[] = {
1551 {
1552 .name = "lock",
1553 .handler = stm32x_handle_lock_command,
1554 .mode = COMMAND_EXEC,
1555 .usage = "bank_id",
1556 .help = "Lock entire flash device.",
1557 },
1558 {
1559 .name = "unlock",
1560 .handler = stm32x_handle_unlock_command,
1561 .mode = COMMAND_EXEC,
1562 .usage = "bank_id",
1563 .help = "Unlock entire protected flash device.",
1564 },
1565 {
1566 .name = "mass_erase",
1567 .handler = stm32x_handle_mass_erase_command,
1568 .mode = COMMAND_EXEC,
1569 .usage = "bank_id",
1570 .help = "Erase entire flash device.",
1571 },
1572 {
1573 .name = "options_read",
1574 .handler = stm32x_handle_options_read_command,
1575 .mode = COMMAND_EXEC,
1576 .usage = "bank_id",
1577 .help = "Read and display device option byte.",
1578 },
1579 {
1580 .name = "options_write",
1581 .handler = stm32x_handle_options_write_command,
1582 .mode = COMMAND_EXEC,
1583 .usage = "bank_id ('SWWDG'|'HWWDG') "
1584 "('RSTSTNDBY'|'NORSTSTNDBY') "
1585 "('RSTSTOP'|'NORSTSTOP')",
1586 .help = "Replace bits in device option byte.",
1587 },
1588 COMMAND_REGISTRATION_DONE
1589 };
1590
1591 static const struct command_registration stm32x_command_handlers[] = {
1592 {
1593 .name = "stm32f1x",
1594 .mode = COMMAND_ANY,
1595 .help = "stm32f1x flash command group",
1596 .usage = "",
1597 .chain = stm32x_exec_command_handlers,
1598 },
1599 COMMAND_REGISTRATION_DONE
1600 };
1601
1602 struct flash_driver stm32f1x_flash = {
1603 .name = "stm32f1x",
1604 .commands = stm32x_command_handlers,
1605 .flash_bank_command = stm32x_flash_bank_command,
1606 .erase = stm32x_erase,
1607 .protect = stm32x_protect,
1608 .write = stm32x_write,
1609 .read = default_flash_read,
1610 .probe = stm32x_probe,
1611 .auto_probe = stm32x_auto_probe,
1612 .erase_check = default_flash_blank_check,
1613 .protect_check = stm32x_protect_check,
1614 .info = get_stm32x_info,
1615 .free_driver_priv = default_flash_free_driver_priv,
1616 };
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