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[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35
36 /* stm32x register locations */
37
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
40
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
49
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
61
62 /* option byte location */
63
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
72
73 /* FLASH_CR register bits */
74
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
83
84 /* FLASH_SR register bits */
85
86 #define FLASH_BSY (1 << 0)
87 #define FLASH_PGERR (1 << 2)
88 #define FLASH_WRPRTERR (1 << 4)
89 #define FLASH_EOP (1 << 5)
90
91 /* STM32_FLASH_OBR bit definitions (reading) */
92
93 #define OPT_ERROR 0
94 #define OPT_READOUT 1
95 #define OPT_RDWDGSW 2
96 #define OPT_RDRSTSTOP 3
97 #define OPT_RDRSTSTDBY 4
98 #define OPT_BFB2 5 /* dual flash bank only */
99
100 /* register unlock keys */
101
102 #define KEY1 0x45670123
103 #define KEY2 0xCDEF89AB
104
105 struct stm32x_options {
106 uint16_t RDP;
107 uint16_t user_options;
108 uint16_t protection[4];
109 };
110
111 struct stm32x_flash_bank {
112 struct stm32x_options option_bytes;
113 struct working_area *write_algorithm;
114 int ppage_size;
115 int probed;
116
117 bool has_dual_banks;
118 /* used to access dual flash bank stm32xl */
119 uint32_t register_base;
120 };
121
122 static int stm32x_mass_erase(struct flash_bank *bank);
123 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
124
125 /* flash bank stm32x <base> <size> 0 0 <target#>
126 */
127 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
128 {
129 struct stm32x_flash_bank *stm32x_info;
130
131 if (CMD_ARGC < 6)
132 return ERROR_COMMAND_SYNTAX_ERROR;
133
134 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
135
136 bank->driver_priv = stm32x_info;
137 stm32x_info->write_algorithm = NULL;
138 stm32x_info->probed = 0;
139 stm32x_info->has_dual_banks = false;
140 stm32x_info->register_base = FLASH_REG_BASE_B0;
141
142 return ERROR_OK;
143 }
144
145 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
146 {
147 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
148 return reg + stm32x_info->register_base;
149 }
150
151 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
152 {
153 struct target *target = bank->target;
154 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
155 }
156
157 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
158 {
159 struct target *target = bank->target;
160 uint32_t status;
161 int retval = ERROR_OK;
162
163 /* wait for busy to clear */
164 for (;;) {
165 retval = stm32x_get_flash_status(bank, &status);
166 if (retval != ERROR_OK)
167 return retval;
168 LOG_DEBUG("status: 0x%" PRIx32 "", status);
169 if ((status & FLASH_BSY) == 0)
170 break;
171 if (timeout-- <= 0) {
172 LOG_ERROR("timed out waiting for flash");
173 return ERROR_FAIL;
174 }
175 alive_sleep(1);
176 }
177
178 if (status & FLASH_WRPRTERR) {
179 LOG_ERROR("stm32x device protected");
180 retval = ERROR_FAIL;
181 }
182
183 if (status & FLASH_PGERR) {
184 LOG_ERROR("stm32x device programming failed");
185 retval = ERROR_FAIL;
186 }
187
188 /* Clear but report errors */
189 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
190 /* If this operation fails, we ignore it and report the original
191 * retval
192 */
193 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
194 FLASH_WRPRTERR | FLASH_PGERR);
195 }
196 return retval;
197 }
198
199 int stm32x_check_operation_supported(struct flash_bank *bank)
200 {
201 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
202
203 /* if we have a dual flash bank device then
204 * we need to perform option byte stuff on bank0 only */
205 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
206 LOG_ERROR("Option Byte Operation's must use bank0");
207 return ERROR_FLASH_OPERATION_FAILED;
208 }
209
210 return ERROR_OK;
211 }
212
213 static int stm32x_read_options(struct flash_bank *bank)
214 {
215 uint32_t optiondata;
216 struct stm32x_flash_bank *stm32x_info = NULL;
217 struct target *target = bank->target;
218
219 stm32x_info = bank->driver_priv;
220
221 /* read current option bytes */
222 int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
223 if (retval != ERROR_OK)
224 return retval;
225
226 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
227 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
228
229 if (optiondata & (1 << OPT_READOUT))
230 LOG_INFO("Device Security Bit Set");
231
232 /* each bit refers to a 4bank protection */
233 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
238 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
239 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
240 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
241
242 return ERROR_OK;
243 }
244
245 static int stm32x_erase_options(struct flash_bank *bank)
246 {
247 struct stm32x_flash_bank *stm32x_info = NULL;
248 struct target *target = bank->target;
249
250 stm32x_info = bank->driver_priv;
251
252 /* read current options */
253 stm32x_read_options(bank);
254
255 /* unlock flash registers */
256 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
257 if (retval != ERROR_OK)
258 return retval;
259
260 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
261 if (retval != ERROR_OK)
262 return retval;
263
264 /* unlock option flash registers */
265 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
266 if (retval != ERROR_OK)
267 return retval;
268 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
269 if (retval != ERROR_OK)
270 return retval;
271
272 /* erase option bytes */
273 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
274 if (retval != ERROR_OK)
275 return retval;
276 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
277 if (retval != ERROR_OK)
278 return retval;
279
280 retval = stm32x_wait_status_busy(bank, 10);
281 if (retval != ERROR_OK)
282 return retval;
283
284 /* clear readout protection and complementary option bytes
285 * this will also force a device unlock if set */
286 stm32x_info->option_bytes.RDP = 0x5AA5;
287
288 return ERROR_OK;
289 }
290
291 static int stm32x_write_options(struct flash_bank *bank)
292 {
293 struct stm32x_flash_bank *stm32x_info = NULL;
294 struct target *target = bank->target;
295
296 stm32x_info = bank->driver_priv;
297
298 /* unlock flash registers */
299 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
300 if (retval != ERROR_OK)
301 return retval;
302 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
303 if (retval != ERROR_OK)
304 return retval;
305
306 /* unlock option flash registers */
307 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
308 if (retval != ERROR_OK)
309 return retval;
310 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
311 if (retval != ERROR_OK)
312 return retval;
313
314 /* program option bytes */
315 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
316 if (retval != ERROR_OK)
317 return retval;
318
319 /* write user option byte */
320 retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
321 if (retval != ERROR_OK)
322 return retval;
323
324 retval = stm32x_wait_status_busy(bank, 10);
325 if (retval != ERROR_OK)
326 return retval;
327
328 /* write protection byte 1 */
329 retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
330 if (retval != ERROR_OK)
331 return retval;
332
333 retval = stm32x_wait_status_busy(bank, 10);
334 if (retval != ERROR_OK)
335 return retval;
336
337 /* write protection byte 2 */
338 retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
339 if (retval != ERROR_OK)
340 return retval;
341
342 retval = stm32x_wait_status_busy(bank, 10);
343 if (retval != ERROR_OK)
344 return retval;
345
346 /* write protection byte 3 */
347 retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
348 if (retval != ERROR_OK)
349 return retval;
350
351 retval = stm32x_wait_status_busy(bank, 10);
352 if (retval != ERROR_OK)
353 return retval;
354
355 /* write protection byte 4 */
356 retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
357 if (retval != ERROR_OK)
358 return retval;
359
360 retval = stm32x_wait_status_busy(bank, 10);
361 if (retval != ERROR_OK)
362 return retval;
363
364 /* write readout protection bit */
365 retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
366 if (retval != ERROR_OK)
367 return retval;
368
369 retval = stm32x_wait_status_busy(bank, 10);
370 if (retval != ERROR_OK)
371 return retval;
372
373 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
374 if (retval != ERROR_OK)
375 return retval;
376
377 return ERROR_OK;
378 }
379
380 static int stm32x_protect_check(struct flash_bank *bank)
381 {
382 struct target *target = bank->target;
383 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
384
385 uint32_t protection;
386 int i, s;
387 int num_bits;
388 int set;
389
390 if (target->state != TARGET_HALTED) {
391 LOG_ERROR("Target not halted");
392 return ERROR_TARGET_NOT_HALTED;
393 }
394
395 int retval = stm32x_check_operation_supported(bank);
396 if (ERROR_OK != retval)
397 return retval;
398
399 /* medium density - each bit refers to a 4bank protection
400 * high density - each bit refers to a 2bank protection */
401 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
402 if (retval != ERROR_OK)
403 return retval;
404
405 /* medium density - each protection bit is for 4 * 1K pages
406 * high density - each protection bit is for 2 * 2K pages */
407 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
408
409 if (stm32x_info->ppage_size == 2) {
410 /* high density flash/connectivity line protection */
411
412 set = 1;
413
414 if (protection & (1 << 31))
415 set = 0;
416
417 /* bit 31 controls sector 62 - 255 protection for high density
418 * bit 31 controls sector 62 - 127 protection for connectivity line */
419 for (s = 62; s < bank->num_sectors; s++)
420 bank->sectors[s].is_protected = set;
421
422 if (bank->num_sectors > 61)
423 num_bits = 31;
424
425 for (i = 0; i < num_bits; i++) {
426 set = 1;
427
428 if (protection & (1 << i))
429 set = 0;
430
431 for (s = 0; s < stm32x_info->ppage_size; s++)
432 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
433 }
434 } else {
435 /* low/medium density flash protection */
436 for (i = 0; i < num_bits; i++) {
437 set = 1;
438
439 if (protection & (1 << i))
440 set = 0;
441
442 for (s = 0; s < stm32x_info->ppage_size; s++)
443 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
444 }
445 }
446
447 return ERROR_OK;
448 }
449
450 static int stm32x_erase(struct flash_bank *bank, int first, int last)
451 {
452 struct target *target = bank->target;
453 int i;
454
455 if (bank->target->state != TARGET_HALTED) {
456 LOG_ERROR("Target not halted");
457 return ERROR_TARGET_NOT_HALTED;
458 }
459
460 if ((first == 0) && (last == (bank->num_sectors - 1)))
461 return stm32x_mass_erase(bank);
462
463 /* unlock flash registers */
464 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
465 if (retval != ERROR_OK)
466 return retval;
467 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
468 if (retval != ERROR_OK)
469 return retval;
470
471 for (i = first; i <= last; i++) {
472 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
473 if (retval != ERROR_OK)
474 return retval;
475 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
476 bank->base + bank->sectors[i].offset);
477 if (retval != ERROR_OK)
478 return retval;
479 retval = target_write_u32(target,
480 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
481 if (retval != ERROR_OK)
482 return retval;
483
484 retval = stm32x_wait_status_busy(bank, 100);
485 if (retval != ERROR_OK)
486 return retval;
487
488 bank->sectors[i].is_erased = 1;
489 }
490
491 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
492 if (retval != ERROR_OK)
493 return retval;
494
495 return ERROR_OK;
496 }
497
498 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
499 {
500 struct stm32x_flash_bank *stm32x_info = NULL;
501 struct target *target = bank->target;
502 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
503 int i, reg, bit;
504 int status;
505 uint32_t protection;
506
507 stm32x_info = bank->driver_priv;
508
509 if (target->state != TARGET_HALTED) {
510 LOG_ERROR("Target not halted");
511 return ERROR_TARGET_NOT_HALTED;
512 }
513
514 int retval = stm32x_check_operation_supported(bank);
515 if (ERROR_OK != retval)
516 return retval;
517
518 if ((first % stm32x_info->ppage_size) != 0) {
519 LOG_WARNING("aligned start protect sector to a %d sector boundary",
520 stm32x_info->ppage_size);
521 first = first - (first % stm32x_info->ppage_size);
522 }
523 if (((last + 1) % stm32x_info->ppage_size) != 0) {
524 LOG_WARNING("aligned end protect sector to a %d sector boundary",
525 stm32x_info->ppage_size);
526 last++;
527 last = last - (last % stm32x_info->ppage_size);
528 last--;
529 }
530
531 /* medium density - each bit refers to a 4bank protection
532 * high density - each bit refers to a 2bank protection */
533 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
534 if (retval != ERROR_OK)
535 return retval;
536
537 prot_reg[0] = (uint16_t)protection;
538 prot_reg[1] = (uint16_t)(protection >> 8);
539 prot_reg[2] = (uint16_t)(protection >> 16);
540 prot_reg[3] = (uint16_t)(protection >> 24);
541
542 if (stm32x_info->ppage_size == 2) {
543 /* high density flash */
544
545 /* bit 7 controls sector 62 - 255 protection */
546 if (last > 61) {
547 if (set)
548 prot_reg[3] &= ~(1 << 7);
549 else
550 prot_reg[3] |= (1 << 7);
551 }
552
553 if (first > 61)
554 first = 62;
555 if (last > 61)
556 last = 61;
557
558 for (i = first; i <= last; i++) {
559 reg = (i / stm32x_info->ppage_size) / 8;
560 bit = (i / stm32x_info->ppage_size) - (reg * 8);
561
562 if (set)
563 prot_reg[reg] &= ~(1 << bit);
564 else
565 prot_reg[reg] |= (1 << bit);
566 }
567 } else {
568 /* medium density flash */
569 for (i = first; i <= last; i++) {
570 reg = (i / stm32x_info->ppage_size) / 8;
571 bit = (i / stm32x_info->ppage_size) - (reg * 8);
572
573 if (set)
574 prot_reg[reg] &= ~(1 << bit);
575 else
576 prot_reg[reg] |= (1 << bit);
577 }
578 }
579
580 status = stm32x_erase_options(bank);
581 if (status != ERROR_OK)
582 return status;
583
584 stm32x_info->option_bytes.protection[0] = prot_reg[0];
585 stm32x_info->option_bytes.protection[1] = prot_reg[1];
586 stm32x_info->option_bytes.protection[2] = prot_reg[2];
587 stm32x_info->option_bytes.protection[3] = prot_reg[3];
588
589 return stm32x_write_options(bank);
590 }
591
592 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
593 uint32_t offset, uint32_t count)
594 {
595 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
596 struct target *target = bank->target;
597 uint32_t buffer_size = 16384;
598 struct working_area *source;
599 uint32_t address = bank->base + offset;
600 struct reg_param reg_params[5];
601 struct armv7m_algorithm armv7m_info;
602 int retval = ERROR_OK;
603
604 /* see contrib/loaders/flash/stm32f1x.S for src */
605
606 static const uint8_t stm32x_flash_write_code[] = {
607 /* #define STM32_FLASH_CR_OFFSET 0x10 */
608 /* #define STM32_FLASH_SR_OFFSET 0x0C */
609 /* wait_fifo: */
610 0x16, 0x68, /* ldr r6, [r2, #0] */
611 0x00, 0x2e, /* cmp r6, #0 */
612 0x1a, 0xd0, /* beq exit */
613 0x55, 0x68, /* ldr r5, [r2, #4] */
614 0xb5, 0x42, /* cmp r5, r6 */
615 0xf9, 0xd0, /* beq wait_fifo */
616 0x01, 0x26, /* movs r6, #1 */
617 0x06, 0x61, /* str r6, [r0, #STM32_FLASH_CR_OFFSET] */
618 0x2e, 0x88, /* ldrh r6, [r5, #0] */
619 0x26, 0x80, /* strh r6, [r4, #0] */
620 0x02, 0x35, /* adds r5, #2 */
621 0x02, 0x34, /* adds r4, #2 */
622 /* busy: */
623 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
624 0x01, 0x27, /* movs r7, #1 */
625 0x3e, 0x42, /* tst r6, r7 */
626 0xfb, 0xd1, /* bne busy */
627 0x14, 0x27, /* movs r7, #0x14 */
628 0x3e, 0x42, /* tst r6, r7 */
629 0x08, 0xd1, /* bne error */
630 0x9d, 0x42, /* cmp r5, r3 */
631 0x01, 0xd3, /* bcc no_wrap */
632 0x15, 0x46, /* mov r5, r2 */
633 0x08, 0x35, /* adds r5, #8 */
634 /* no_wrap: */
635 0x55, 0x60, /* str r5, [r2, #4] */
636 0x01, 0x39, /* subs r1, r1, #1 */
637 0x00, 0x29, /* cmp r1, #0 */
638 0x02, 0xd0, /* beq exit */
639 0xe3, 0xe7, /* b wait_fifo */
640 /* error: */
641 0x00, 0x20, /* movs r0, #0 */
642 0x50, 0x60, /* str r0, [r2, #4] */
643 /* exit: */
644 0x30, 0x46, /* mov r0, r6 */
645 0x00, 0xbe, /* bkpt #0 */
646 };
647
648 /* flash write code */
649 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
650 &stm32x_info->write_algorithm) != ERROR_OK) {
651 LOG_WARNING("no working area available, can't do block memory writes");
652 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
653 };
654
655 retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
656 sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
657 if (retval != ERROR_OK)
658 return retval;
659
660 /* memory buffer */
661 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
662 buffer_size /= 2;
663 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
664 if (buffer_size <= 256) {
665 /* if we already allocated the writing code, but failed to get a
666 * buffer, free the algorithm */
667 if (stm32x_info->write_algorithm)
668 target_free_working_area(target, stm32x_info->write_algorithm);
669
670 LOG_WARNING("no large enough working area available, can't do block memory writes");
671 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
672 }
673 };
674
675 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
676 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
677 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
678 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
679 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
680
681 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
682 buf_set_u32(reg_params[1].value, 0, 32, count);
683 buf_set_u32(reg_params[2].value, 0, 32, source->address);
684 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
685 buf_set_u32(reg_params[4].value, 0, 32, address);
686
687 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
688 armv7m_info.core_mode = ARMV7M_MODE_ANY;
689
690 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
691 0, NULL,
692 5, reg_params,
693 source->address, source->size,
694 stm32x_info->write_algorithm->address, 0,
695 &armv7m_info);
696
697 if (retval == ERROR_FLASH_OPERATION_FAILED) {
698 LOG_ERROR("flash write failed at address 0x%"PRIx32,
699 buf_get_u32(reg_params[4].value, 0, 32));
700
701 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
702 LOG_ERROR("flash memory not erased before writing");
703 /* Clear but report errors */
704 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
705 }
706
707 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
708 LOG_ERROR("flash memory write protected");
709 /* Clear but report errors */
710 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
711 }
712 }
713
714 target_free_working_area(target, source);
715 target_free_working_area(target, stm32x_info->write_algorithm);
716
717 destroy_reg_param(&reg_params[0]);
718 destroy_reg_param(&reg_params[1]);
719 destroy_reg_param(&reg_params[2]);
720 destroy_reg_param(&reg_params[3]);
721 destroy_reg_param(&reg_params[4]);
722
723 return retval;
724 }
725
726 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
727 uint32_t offset, uint32_t count)
728 {
729 struct target *target = bank->target;
730 uint32_t words_remaining = (count / 2);
731 uint32_t bytes_remaining = (count & 0x00000001);
732 uint32_t address = bank->base + offset;
733 uint32_t bytes_written = 0;
734 int retval;
735
736 if (bank->target->state != TARGET_HALTED) {
737 LOG_ERROR("Target not halted");
738 return ERROR_TARGET_NOT_HALTED;
739 }
740
741 if (offset & 0x1) {
742 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
743 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
744 }
745
746 /* unlock flash registers */
747 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
748 if (retval != ERROR_OK)
749 return retval;
750 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
751 if (retval != ERROR_OK)
752 return retval;
753
754 /* multiple half words (2-byte) to be programmed? */
755 if (words_remaining > 0) {
756 /* try using a block write */
757 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
758 if (retval != ERROR_OK) {
759 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
760 /* if block write failed (no sufficient working area),
761 * we use normal (slow) single dword accesses */
762 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
763 }
764 } else {
765 buffer += words_remaining * 2;
766 address += words_remaining * 2;
767 words_remaining = 0;
768 }
769 }
770
771 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
772 return retval;
773
774 while (words_remaining > 0) {
775 uint16_t value;
776 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
777
778 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
779 if (retval != ERROR_OK)
780 return retval;
781 retval = target_write_u16(target, address, value);
782 if (retval != ERROR_OK)
783 return retval;
784
785 retval = stm32x_wait_status_busy(bank, 5);
786 if (retval != ERROR_OK)
787 return retval;
788
789 bytes_written += 2;
790 words_remaining--;
791 address += 2;
792 }
793
794 if (bytes_remaining) {
795 uint16_t value = 0xffff;
796 memcpy(&value, buffer + bytes_written, bytes_remaining);
797
798 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
799 if (retval != ERROR_OK)
800 return retval;
801 retval = target_write_u16(target, address, value);
802 if (retval != ERROR_OK)
803 return retval;
804
805 retval = stm32x_wait_status_busy(bank, 5);
806 if (retval != ERROR_OK)
807 return retval;
808 }
809
810 return target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
811 }
812
813 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
814 {
815 /* This check the device CPUID core register to detect
816 * the M0 from the M3 devices. */
817
818 struct target *target = bank->target;
819 uint32_t cpuid, device_id_register = 0;
820
821 /* Get the CPUID from the ARM Core
822 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
823 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
824 if (retval != ERROR_OK)
825 return retval;
826
827 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
828 /* 0xC20 is M0 devices */
829 device_id_register = 0x40015800;
830 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
831 /* 0xC23 is M3 devices */
832 device_id_register = 0xE0042000;
833 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
834 /* 0xC24 is M4 devices */
835 device_id_register = 0xE0042000;
836 } else {
837 LOG_ERROR("Cannot identify target as a stm32x");
838 return ERROR_FAIL;
839 }
840
841 /* read stm32 device id register */
842 retval = target_read_u32(target, device_id_register, device_id);
843 if (retval != ERROR_OK)
844 return retval;
845
846 return retval;
847 }
848
849 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
850 {
851 struct target *target = bank->target;
852 uint32_t cpuid, flash_size_reg;
853
854 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
855 if (retval != ERROR_OK)
856 return retval;
857
858 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
859 /* 0xC20 is M0 devices */
860 flash_size_reg = 0x1FFFF7CC;
861 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
862 /* 0xC23 is M3 devices */
863 flash_size_reg = 0x1FFFF7E0;
864 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
865 /* 0xC24 is M4 devices */
866 flash_size_reg = 0x1FFFF7CC;
867 } else {
868 LOG_ERROR("Cannot identify target as a stm32x");
869 return ERROR_FAIL;
870 }
871
872 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
873 if (retval != ERROR_OK)
874 return retval;
875
876 return retval;
877 }
878
879 static int stm32x_probe(struct flash_bank *bank)
880 {
881 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
882 int i;
883 uint16_t flash_size_in_kb;
884 uint32_t device_id;
885 int page_size;
886 uint32_t base_address = 0x08000000;
887
888 stm32x_info->probed = 0;
889 stm32x_info->register_base = FLASH_REG_BASE_B0;
890
891 /* read stm32 device id register */
892 int retval = stm32x_get_device_id(bank, &device_id);
893 if (retval != ERROR_OK)
894 return retval;
895
896 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
897
898 /* get flash size from target. */
899 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
900 if (retval != ERROR_OK) {
901 LOG_WARNING("failed reading flash size, default to max target family");
902 /* failed reading flash size, default to max target family */
903 flash_size_in_kb = 0xffff;
904 }
905
906 if ((device_id & 0xfff) == 0x410) {
907 /* medium density - we have 1k pages
908 * 4 pages for a protection area */
909 page_size = 1024;
910 stm32x_info->ppage_size = 4;
911
912 /* check for early silicon */
913 if (flash_size_in_kb == 0xffff) {
914 /* number of sectors incorrect on revA */
915 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
916 flash_size_in_kb = 128;
917 }
918 } else if ((device_id & 0xfff) == 0x412) {
919 /* low density - we have 1k pages
920 * 4 pages for a protection area */
921 page_size = 1024;
922 stm32x_info->ppage_size = 4;
923
924 /* check for early silicon */
925 if (flash_size_in_kb == 0xffff) {
926 /* number of sectors incorrect on revA */
927 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
928 flash_size_in_kb = 32;
929 }
930 } else if ((device_id & 0xfff) == 0x414) {
931 /* high density - we have 2k pages
932 * 2 pages for a protection area */
933 page_size = 2048;
934 stm32x_info->ppage_size = 2;
935
936 /* check for early silicon */
937 if (flash_size_in_kb == 0xffff) {
938 /* number of sectors incorrect on revZ */
939 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
940 flash_size_in_kb = 512;
941 }
942 } else if ((device_id & 0xfff) == 0x418) {
943 /* connectivity line density - we have 2k pages
944 * 2 pages for a protection area */
945 page_size = 2048;
946 stm32x_info->ppage_size = 2;
947
948 /* check for early silicon */
949 if (flash_size_in_kb == 0xffff) {
950 /* number of sectors incorrect on revZ */
951 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
952 flash_size_in_kb = 256;
953 }
954 } else if ((device_id & 0xfff) == 0x420) {
955 /* value line density - we have 1k pages
956 * 4 pages for a protection area */
957 page_size = 1024;
958 stm32x_info->ppage_size = 4;
959
960 /* check for early silicon */
961 if (flash_size_in_kb == 0xffff) {
962 /* number of sectors may be incorrrect on early silicon */
963 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
964 flash_size_in_kb = 128;
965 }
966 } else if ((device_id & 0xfff) == 0x422) {
967 /* stm32f30x - we have 2k pages
968 * 2 pages for a protection area */
969 page_size = 2048;
970 stm32x_info->ppage_size = 2;
971
972 /* check for early silicon */
973 if (flash_size_in_kb == 0xffff) {
974 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
975 flash_size_in_kb = 256;
976 }
977 } else if ((device_id & 0xfff) == 0x428) {
978 /* value line High density - we have 2k pages
979 * 4 pages for a protection area */
980 page_size = 2048;
981 stm32x_info->ppage_size = 4;
982
983 /* check for early silicon */
984 if (flash_size_in_kb == 0xffff) {
985 /* number of sectors may be incorrrect on early silicon */
986 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
987 flash_size_in_kb = 128;
988 }
989 } else if ((device_id & 0xfff) == 0x430) {
990 /* xl line density - we have 2k pages
991 * 2 pages for a protection area */
992 page_size = 2048;
993 stm32x_info->ppage_size = 2;
994 stm32x_info->has_dual_banks = true;
995
996 /* check for early silicon */
997 if (flash_size_in_kb == 0xffff) {
998 /* number of sectors may be incorrrect on early silicon */
999 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
1000 flash_size_in_kb = 1024;
1001 }
1002
1003 /* split reported size into matching bank */
1004 if (bank->base != 0x08080000) {
1005 /* bank 0 will be fixed 512k */
1006 flash_size_in_kb = 512;
1007 } else {
1008 flash_size_in_kb -= 512;
1009 /* bank1 also uses a register offset */
1010 stm32x_info->register_base = FLASH_REG_BASE_B1;
1011 base_address = 0x08080000;
1012 }
1013 } else if ((device_id & 0xfff) == 0x432) {
1014 /* stm32f37x - we have 2k pages
1015 * 2 pages for a protection area */
1016 page_size = 2048;
1017 stm32x_info->ppage_size = 2;
1018
1019 /* check for early silicon */
1020 if (flash_size_in_kb == 0xffff) {
1021 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
1022 flash_size_in_kb = 256;
1023 }
1024 } else if ((device_id & 0xfff) == 0x440) {
1025 /* stm32f0x - we have 1k pages
1026 * 4 pages for a protection area */
1027 page_size = 1024;
1028 stm32x_info->ppage_size = 4;
1029
1030 /* check for early silicon */
1031 if (flash_size_in_kb == 0xffff) {
1032 /* number of sectors incorrect on revZ */
1033 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 64k flash");
1034 flash_size_in_kb = 64;
1035 }
1036 } else {
1037 LOG_WARNING("Cannot identify target as a STM32 family.");
1038 return ERROR_FAIL;
1039 }
1040
1041 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
1042
1043 /* did we assign flash size? */
1044 assert(flash_size_in_kb != 0xffff);
1045
1046 /* calculate numbers of pages */
1047 int num_pages = flash_size_in_kb * 1024 / page_size;
1048
1049 /* check that calculation result makes sense */
1050 assert(num_pages > 0);
1051
1052 if (bank->sectors) {
1053 free(bank->sectors);
1054 bank->sectors = NULL;
1055 }
1056
1057 bank->base = base_address;
1058 bank->size = (num_pages * page_size);
1059 bank->num_sectors = num_pages;
1060 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1061
1062 for (i = 0; i < num_pages; i++) {
1063 bank->sectors[i].offset = i * page_size;
1064 bank->sectors[i].size = page_size;
1065 bank->sectors[i].is_erased = -1;
1066 bank->sectors[i].is_protected = 1;
1067 }
1068
1069 stm32x_info->probed = 1;
1070
1071 return ERROR_OK;
1072 }
1073
1074 static int stm32x_auto_probe(struct flash_bank *bank)
1075 {
1076 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1077 if (stm32x_info->probed)
1078 return ERROR_OK;
1079 return stm32x_probe(bank);
1080 }
1081
1082 #if 0
1083 COMMAND_HANDLER(stm32x_handle_part_id_command)
1084 {
1085 return ERROR_OK;
1086 }
1087 #endif
1088
1089 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1090 {
1091 uint32_t device_id;
1092 int printed;
1093
1094 /* read stm32 device id register */
1095 int retval = stm32x_get_device_id(bank, &device_id);
1096 if (retval != ERROR_OK)
1097 return retval;
1098
1099 if ((device_id & 0xfff) == 0x410) {
1100 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1101 buf += printed;
1102 buf_size -= printed;
1103
1104 switch (device_id >> 16) {
1105 case 0x0000:
1106 snprintf(buf, buf_size, "A");
1107 break;
1108
1109 case 0x2000:
1110 snprintf(buf, buf_size, "B");
1111 break;
1112
1113 case 0x2001:
1114 snprintf(buf, buf_size, "Z");
1115 break;
1116
1117 case 0x2003:
1118 snprintf(buf, buf_size, "Y");
1119 break;
1120
1121 default:
1122 snprintf(buf, buf_size, "unknown");
1123 break;
1124 }
1125 } else if ((device_id & 0xfff) == 0x412) {
1126 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1127 buf += printed;
1128 buf_size -= printed;
1129
1130 switch (device_id >> 16) {
1131 case 0x1000:
1132 snprintf(buf, buf_size, "A");
1133 break;
1134
1135 default:
1136 snprintf(buf, buf_size, "unknown");
1137 break;
1138 }
1139 } else if ((device_id & 0xfff) == 0x414) {
1140 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1141 buf += printed;
1142 buf_size -= printed;
1143
1144 switch (device_id >> 16) {
1145 case 0x1000:
1146 snprintf(buf, buf_size, "A");
1147 break;
1148
1149 case 0x1001:
1150 snprintf(buf, buf_size, "Z");
1151 break;
1152
1153 default:
1154 snprintf(buf, buf_size, "unknown");
1155 break;
1156 }
1157 } else if ((device_id & 0xfff) == 0x418) {
1158 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1159 buf += printed;
1160 buf_size -= printed;
1161
1162 switch (device_id >> 16) {
1163 case 0x1000:
1164 snprintf(buf, buf_size, "A");
1165 break;
1166
1167 case 0x1001:
1168 snprintf(buf, buf_size, "Z");
1169 break;
1170
1171 default:
1172 snprintf(buf, buf_size, "unknown");
1173 break;
1174 }
1175 } else if ((device_id & 0xfff) == 0x420) {
1176 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1177 buf += printed;
1178 buf_size -= printed;
1179
1180 switch (device_id >> 16) {
1181 case 0x1000:
1182 snprintf(buf, buf_size, "A");
1183 break;
1184
1185 case 0x1001:
1186 snprintf(buf, buf_size, "Z");
1187 break;
1188
1189 default:
1190 snprintf(buf, buf_size, "unknown");
1191 break;
1192 }
1193 } else if ((device_id & 0xfff) == 0x422) {
1194 printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
1195 buf += printed;
1196 buf_size -= printed;
1197
1198 switch (device_id >> 16) {
1199 case 0x1000:
1200 snprintf(buf, buf_size, "1.0");
1201 break;
1202
1203 default:
1204 snprintf(buf, buf_size, "unknown");
1205 break;
1206 }
1207 } else if ((device_id & 0xfff) == 0x428) {
1208 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1209 buf += printed;
1210 buf_size -= printed;
1211
1212 switch (device_id >> 16) {
1213 case 0x1000:
1214 snprintf(buf, buf_size, "A");
1215 break;
1216
1217 case 0x1001:
1218 snprintf(buf, buf_size, "Z");
1219 break;
1220
1221 default:
1222 snprintf(buf, buf_size, "unknown");
1223 break;
1224 }
1225 } else if ((device_id & 0xfff) == 0x430) {
1226 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1227 buf += printed;
1228 buf_size -= printed;
1229
1230 switch (device_id >> 16) {
1231 case 0x1000:
1232 snprintf(buf, buf_size, "A");
1233 break;
1234
1235 default:
1236 snprintf(buf, buf_size, "unknown");
1237 break;
1238 }
1239 } else if ((device_id & 0xfff) == 0x432) {
1240 printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
1241 buf += printed;
1242 buf_size -= printed;
1243
1244 switch (device_id >> 16) {
1245 case 0x1000:
1246 snprintf(buf, buf_size, "1.0");
1247 break;
1248
1249 default:
1250 snprintf(buf, buf_size, "unknown");
1251 break;
1252 }
1253 } else if ((device_id & 0xfff) == 0x440) {
1254 printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
1255 buf += printed;
1256 buf_size -= printed;
1257
1258 switch (device_id >> 16) {
1259 case 0x1000:
1260 snprintf(buf, buf_size, "1.0");
1261 break;
1262
1263 case 0x2000:
1264 snprintf(buf, buf_size, "2.0");
1265 break;
1266
1267 default:
1268 snprintf(buf, buf_size, "unknown");
1269 break;
1270 }
1271 } else {
1272 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1273 return ERROR_FAIL;
1274 }
1275
1276 return ERROR_OK;
1277 }
1278
1279 COMMAND_HANDLER(stm32x_handle_lock_command)
1280 {
1281 struct target *target = NULL;
1282 struct stm32x_flash_bank *stm32x_info = NULL;
1283
1284 if (CMD_ARGC < 1)
1285 return ERROR_COMMAND_SYNTAX_ERROR;
1286
1287 struct flash_bank *bank;
1288 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1289 if (ERROR_OK != retval)
1290 return retval;
1291
1292 stm32x_info = bank->driver_priv;
1293
1294 target = bank->target;
1295
1296 if (target->state != TARGET_HALTED) {
1297 LOG_ERROR("Target not halted");
1298 return ERROR_TARGET_NOT_HALTED;
1299 }
1300
1301 retval = stm32x_check_operation_supported(bank);
1302 if (ERROR_OK != retval)
1303 return retval;
1304
1305 if (stm32x_erase_options(bank) != ERROR_OK) {
1306 command_print(CMD_CTX, "stm32x failed to erase options");
1307 return ERROR_OK;
1308 }
1309
1310 /* set readout protection */
1311 stm32x_info->option_bytes.RDP = 0;
1312
1313 if (stm32x_write_options(bank) != ERROR_OK) {
1314 command_print(CMD_CTX, "stm32x failed to lock device");
1315 return ERROR_OK;
1316 }
1317
1318 command_print(CMD_CTX, "stm32x locked");
1319
1320 return ERROR_OK;
1321 }
1322
1323 COMMAND_HANDLER(stm32x_handle_unlock_command)
1324 {
1325 struct target *target = NULL;
1326
1327 if (CMD_ARGC < 1)
1328 return ERROR_COMMAND_SYNTAX_ERROR;
1329
1330 struct flash_bank *bank;
1331 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1332 if (ERROR_OK != retval)
1333 return retval;
1334
1335 target = bank->target;
1336
1337 if (target->state != TARGET_HALTED) {
1338 LOG_ERROR("Target not halted");
1339 return ERROR_TARGET_NOT_HALTED;
1340 }
1341
1342 retval = stm32x_check_operation_supported(bank);
1343 if (ERROR_OK != retval)
1344 return retval;
1345
1346 if (stm32x_erase_options(bank) != ERROR_OK) {
1347 command_print(CMD_CTX, "stm32x failed to unlock device");
1348 return ERROR_OK;
1349 }
1350
1351 if (stm32x_write_options(bank) != ERROR_OK) {
1352 command_print(CMD_CTX, "stm32x failed to lock device");
1353 return ERROR_OK;
1354 }
1355
1356 command_print(CMD_CTX, "stm32x unlocked.\n"
1357 "INFO: a reset or power cycle is required "
1358 "for the new settings to take effect.");
1359
1360 return ERROR_OK;
1361 }
1362
1363 COMMAND_HANDLER(stm32x_handle_options_read_command)
1364 {
1365 uint32_t optionbyte;
1366 struct target *target = NULL;
1367 struct stm32x_flash_bank *stm32x_info = NULL;
1368
1369 if (CMD_ARGC < 1)
1370 return ERROR_COMMAND_SYNTAX_ERROR;
1371
1372 struct flash_bank *bank;
1373 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1374 if (ERROR_OK != retval)
1375 return retval;
1376
1377 stm32x_info = bank->driver_priv;
1378
1379 target = bank->target;
1380
1381 if (target->state != TARGET_HALTED) {
1382 LOG_ERROR("Target not halted");
1383 return ERROR_TARGET_NOT_HALTED;
1384 }
1385
1386 retval = stm32x_check_operation_supported(bank);
1387 if (ERROR_OK != retval)
1388 return retval;
1389
1390 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1391 if (retval != ERROR_OK)
1392 return retval;
1393 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1394
1395 if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
1396 command_print(CMD_CTX, "Option Byte Complement Error");
1397
1398 if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
1399 command_print(CMD_CTX, "Readout Protection On");
1400 else
1401 command_print(CMD_CTX, "Readout Protection Off");
1402
1403 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
1404 command_print(CMD_CTX, "Software Watchdog");
1405 else
1406 command_print(CMD_CTX, "Hardware Watchdog");
1407
1408 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
1409 command_print(CMD_CTX, "Stop: No reset generated");
1410 else
1411 command_print(CMD_CTX, "Stop: Reset generated");
1412
1413 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
1414 command_print(CMD_CTX, "Standby: No reset generated");
1415 else
1416 command_print(CMD_CTX, "Standby: Reset generated");
1417
1418 if (stm32x_info->has_dual_banks) {
1419 if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
1420 command_print(CMD_CTX, "Boot: Bank 0");
1421 else
1422 command_print(CMD_CTX, "Boot: Bank 1");
1423 }
1424
1425 return ERROR_OK;
1426 }
1427
1428 COMMAND_HANDLER(stm32x_handle_options_write_command)
1429 {
1430 struct target *target = NULL;
1431 struct stm32x_flash_bank *stm32x_info = NULL;
1432 uint16_t optionbyte = 0xF8;
1433
1434 if (CMD_ARGC < 4)
1435 return ERROR_COMMAND_SYNTAX_ERROR;
1436
1437 struct flash_bank *bank;
1438 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1439 if (ERROR_OK != retval)
1440 return retval;
1441
1442 stm32x_info = bank->driver_priv;
1443
1444 target = bank->target;
1445
1446 if (target->state != TARGET_HALTED) {
1447 LOG_ERROR("Target not halted");
1448 return ERROR_TARGET_NOT_HALTED;
1449 }
1450
1451 retval = stm32x_check_operation_supported(bank);
1452 if (ERROR_OK != retval)
1453 return retval;
1454
1455 /* REVISIT: ignores some options which we will display...
1456 * and doesn't insist on the specified syntax.
1457 */
1458
1459 /* OPT_RDWDGSW */
1460 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1461 optionbyte |= (1 << 0);
1462 else /* REVISIT must be "HWWDG" then ... */
1463 optionbyte &= ~(1 << 0);
1464
1465 /* OPT_RDRSTSTOP */
1466 if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
1467 optionbyte |= (1 << 1);
1468 else /* REVISIT must be "RSTSTNDBY" then ... */
1469 optionbyte &= ~(1 << 1);
1470
1471 /* OPT_RDRSTSTDBY */
1472 if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
1473 optionbyte |= (1 << 2);
1474 else /* REVISIT must be "RSTSTOP" then ... */
1475 optionbyte &= ~(1 << 2);
1476
1477 if (CMD_ARGC > 4 && stm32x_info->has_dual_banks) {
1478 /* OPT_BFB2 */
1479 if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
1480 optionbyte |= (1 << 3);
1481 else
1482 optionbyte &= ~(1 << 3);
1483 }
1484
1485 if (stm32x_erase_options(bank) != ERROR_OK) {
1486 command_print(CMD_CTX, "stm32x failed to erase options");
1487 return ERROR_OK;
1488 }
1489
1490 stm32x_info->option_bytes.user_options = optionbyte;
1491
1492 if (stm32x_write_options(bank) != ERROR_OK) {
1493 command_print(CMD_CTX, "stm32x failed to write options");
1494 return ERROR_OK;
1495 }
1496
1497 command_print(CMD_CTX, "stm32x write options complete.\n"
1498 "INFO: a reset or power cycle is required "
1499 "for the new settings to take effect.");
1500
1501 return ERROR_OK;
1502 }
1503
1504 static int stm32x_mass_erase(struct flash_bank *bank)
1505 {
1506 struct target *target = bank->target;
1507
1508 if (target->state != TARGET_HALTED) {
1509 LOG_ERROR("Target not halted");
1510 return ERROR_TARGET_NOT_HALTED;
1511 }
1512
1513 /* unlock option flash registers */
1514 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1515 if (retval != ERROR_OK)
1516 return retval;
1517 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1518 if (retval != ERROR_OK)
1519 return retval;
1520
1521 /* mass erase flash memory */
1522 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1523 if (retval != ERROR_OK)
1524 return retval;
1525 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1526 FLASH_MER | FLASH_STRT);
1527 if (retval != ERROR_OK)
1528 return retval;
1529
1530 retval = stm32x_wait_status_busy(bank, 100);
1531 if (retval != ERROR_OK)
1532 return retval;
1533
1534 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1535 if (retval != ERROR_OK)
1536 return retval;
1537
1538 return ERROR_OK;
1539 }
1540
1541 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1542 {
1543 int i;
1544
1545 if (CMD_ARGC < 1)
1546 return ERROR_COMMAND_SYNTAX_ERROR;
1547
1548 struct flash_bank *bank;
1549 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1550 if (ERROR_OK != retval)
1551 return retval;
1552
1553 retval = stm32x_mass_erase(bank);
1554 if (retval == ERROR_OK) {
1555 /* set all sectors as erased */
1556 for (i = 0; i < bank->num_sectors; i++)
1557 bank->sectors[i].is_erased = 1;
1558
1559 command_print(CMD_CTX, "stm32x mass erase complete");
1560 } else
1561 command_print(CMD_CTX, "stm32x mass erase failed");
1562
1563 return retval;
1564 }
1565
1566 static const struct command_registration stm32x_exec_command_handlers[] = {
1567 {
1568 .name = "lock",
1569 .handler = stm32x_handle_lock_command,
1570 .mode = COMMAND_EXEC,
1571 .usage = "bank_id",
1572 .help = "Lock entire flash device.",
1573 },
1574 {
1575 .name = "unlock",
1576 .handler = stm32x_handle_unlock_command,
1577 .mode = COMMAND_EXEC,
1578 .usage = "bank_id",
1579 .help = "Unlock entire protected flash device.",
1580 },
1581 {
1582 .name = "mass_erase",
1583 .handler = stm32x_handle_mass_erase_command,
1584 .mode = COMMAND_EXEC,
1585 .usage = "bank_id",
1586 .help = "Erase entire flash device.",
1587 },
1588 {
1589 .name = "options_read",
1590 .handler = stm32x_handle_options_read_command,
1591 .mode = COMMAND_EXEC,
1592 .usage = "bank_id",
1593 .help = "Read and display device option byte.",
1594 },
1595 {
1596 .name = "options_write",
1597 .handler = stm32x_handle_options_write_command,
1598 .mode = COMMAND_EXEC,
1599 .usage = "bank_id ('SWWDG'|'HWWDG') "
1600 "('RSTSTNDBY'|'NORSTSTNDBY') "
1601 "('RSTSTOP'|'NORSTSTOP')",
1602 .help = "Replace bits in device option byte.",
1603 },
1604 COMMAND_REGISTRATION_DONE
1605 };
1606
1607 static const struct command_registration stm32x_command_handlers[] = {
1608 {
1609 .name = "stm32f1x",
1610 .mode = COMMAND_ANY,
1611 .help = "stm32f1x flash command group",
1612 .usage = "",
1613 .chain = stm32x_exec_command_handlers,
1614 },
1615 COMMAND_REGISTRATION_DONE
1616 };
1617
1618 struct flash_driver stm32f1x_flash = {
1619 .name = "stm32f1x",
1620 .commands = stm32x_command_handlers,
1621 .flash_bank_command = stm32x_flash_bank_command,
1622 .erase = stm32x_erase,
1623 .protect = stm32x_protect,
1624 .write = stm32x_write,
1625 .read = default_flash_read,
1626 .probe = stm32x_probe,
1627 .auto_probe = stm32x_auto_probe,
1628 .erase_check = default_flash_blank_check,
1629 .protect_check = stm32x_protect_check,
1630 .info = get_stm32x_info,
1631 };
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