d06016a4d849ff3ae46fd88115616cacd642e591
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35
36 /* stm32x register locations */
37
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
40
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
49
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
61
62 /* option byte location */
63
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
72
73 /* FLASH_CR register bits */
74
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
83
84 /* FLASH_SR register bits */
85
86 #define FLASH_BSY (1 << 0)
87 #define FLASH_PGERR (1 << 2)
88 #define FLASH_WRPRTERR (1 << 4)
89 #define FLASH_EOP (1 << 5)
90
91 /* STM32_FLASH_OBR bit definitions (reading) */
92
93 #define OPT_ERROR 0
94 #define OPT_READOUT 1
95 #define OPT_RDWDGSW 2
96 #define OPT_RDRSTSTOP 3
97 #define OPT_RDRSTSTDBY 4
98 #define OPT_BFB2 5 /* dual flash bank only */
99
100 /* register unlock keys */
101
102 #define KEY1 0x45670123
103 #define KEY2 0xCDEF89AB
104
105 struct stm32x_options {
106 uint16_t RDP;
107 uint16_t user_options;
108 uint16_t protection[4];
109 };
110
111 struct stm32x_flash_bank {
112 struct stm32x_options option_bytes;
113 struct working_area *write_algorithm;
114 int ppage_size;
115 int probed;
116
117 bool has_dual_banks;
118 /* used to access dual flash bank stm32xl */
119 uint32_t register_base;
120 };
121
122 static int stm32x_mass_erase(struct flash_bank *bank);
123 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
124
125 /* flash bank stm32x <base> <size> 0 0 <target#>
126 */
127 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
128 {
129 struct stm32x_flash_bank *stm32x_info;
130
131 if (CMD_ARGC < 6)
132 return ERROR_COMMAND_SYNTAX_ERROR;
133
134 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
135
136 bank->driver_priv = stm32x_info;
137 stm32x_info->write_algorithm = NULL;
138 stm32x_info->probed = 0;
139 stm32x_info->has_dual_banks = false;
140 stm32x_info->register_base = FLASH_REG_BASE_B0;
141
142 return ERROR_OK;
143 }
144
145 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
146 {
147 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
148 return reg + stm32x_info->register_base;
149 }
150
151 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
152 {
153 struct target *target = bank->target;
154 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
155 }
156
157 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
158 {
159 struct target *target = bank->target;
160 uint32_t status;
161 int retval = ERROR_OK;
162
163 /* wait for busy to clear */
164 for (;;) {
165 retval = stm32x_get_flash_status(bank, &status);
166 if (retval != ERROR_OK)
167 return retval;
168 LOG_DEBUG("status: 0x%" PRIx32 "", status);
169 if ((status & FLASH_BSY) == 0)
170 break;
171 if (timeout-- <= 0) {
172 LOG_ERROR("timed out waiting for flash");
173 return ERROR_FAIL;
174 }
175 alive_sleep(1);
176 }
177
178 if (status & FLASH_WRPRTERR) {
179 LOG_ERROR("stm32x device protected");
180 retval = ERROR_FAIL;
181 }
182
183 if (status & FLASH_PGERR) {
184 LOG_ERROR("stm32x device programming failed");
185 retval = ERROR_FAIL;
186 }
187
188 /* Clear but report errors */
189 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
190 /* If this operation fails, we ignore it and report the original
191 * retval
192 */
193 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
194 FLASH_WRPRTERR | FLASH_PGERR);
195 }
196 return retval;
197 }
198
199 int stm32x_check_operation_supported(struct flash_bank *bank)
200 {
201 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
202
203 /* if we have a dual flash bank device then
204 * we need to perform option byte stuff on bank0 only */
205 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
206 LOG_ERROR("Option Byte Operation's must use bank0");
207 return ERROR_FLASH_OPERATION_FAILED;
208 }
209
210 return ERROR_OK;
211 }
212
213 static int stm32x_read_options(struct flash_bank *bank)
214 {
215 uint32_t optiondata;
216 struct stm32x_flash_bank *stm32x_info = NULL;
217 struct target *target = bank->target;
218
219 stm32x_info = bank->driver_priv;
220
221 /* read current option bytes */
222 int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
223 if (retval != ERROR_OK)
224 return retval;
225
226 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
227 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
228
229 if (optiondata & (1 << OPT_READOUT))
230 LOG_INFO("Device Security Bit Set");
231
232 /* each bit refers to a 4bank protection */
233 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
238 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
239 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
240 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
241
242 return ERROR_OK;
243 }
244
245 static int stm32x_erase_options(struct flash_bank *bank)
246 {
247 struct stm32x_flash_bank *stm32x_info = NULL;
248 struct target *target = bank->target;
249
250 stm32x_info = bank->driver_priv;
251
252 /* read current options */
253 stm32x_read_options(bank);
254
255 /* unlock flash registers */
256 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
257 if (retval != ERROR_OK)
258 return retval;
259
260 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
261 if (retval != ERROR_OK)
262 return retval;
263
264 /* unlock option flash registers */
265 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
266 if (retval != ERROR_OK)
267 return retval;
268 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
269 if (retval != ERROR_OK)
270 return retval;
271
272 /* erase option bytes */
273 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
274 if (retval != ERROR_OK)
275 return retval;
276 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
277 if (retval != ERROR_OK)
278 return retval;
279
280 retval = stm32x_wait_status_busy(bank, 10);
281 if (retval != ERROR_OK)
282 return retval;
283
284 /* clear readout protection and complementary option bytes
285 * this will also force a device unlock if set */
286 stm32x_info->option_bytes.RDP = 0x5AA5;
287
288 return ERROR_OK;
289 }
290
291 static int stm32x_write_options(struct flash_bank *bank)
292 {
293 struct stm32x_flash_bank *stm32x_info = NULL;
294 struct target *target = bank->target;
295
296 stm32x_info = bank->driver_priv;
297
298 /* unlock flash registers */
299 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
300 if (retval != ERROR_OK)
301 return retval;
302 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
303 if (retval != ERROR_OK)
304 return retval;
305
306 /* unlock option flash registers */
307 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
308 if (retval != ERROR_OK)
309 return retval;
310 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
311 if (retval != ERROR_OK)
312 return retval;
313
314 /* program option bytes */
315 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
316 if (retval != ERROR_OK)
317 return retval;
318
319 /* write user option byte */
320 retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
321 if (retval != ERROR_OK)
322 return retval;
323
324 retval = stm32x_wait_status_busy(bank, 10);
325 if (retval != ERROR_OK)
326 return retval;
327
328 /* write protection byte 1 */
329 retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
330 if (retval != ERROR_OK)
331 return retval;
332
333 retval = stm32x_wait_status_busy(bank, 10);
334 if (retval != ERROR_OK)
335 return retval;
336
337 /* write protection byte 2 */
338 retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
339 if (retval != ERROR_OK)
340 return retval;
341
342 retval = stm32x_wait_status_busy(bank, 10);
343 if (retval != ERROR_OK)
344 return retval;
345
346 /* write protection byte 3 */
347 retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
348 if (retval != ERROR_OK)
349 return retval;
350
351 retval = stm32x_wait_status_busy(bank, 10);
352 if (retval != ERROR_OK)
353 return retval;
354
355 /* write protection byte 4 */
356 retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
357 if (retval != ERROR_OK)
358 return retval;
359
360 retval = stm32x_wait_status_busy(bank, 10);
361 if (retval != ERROR_OK)
362 return retval;
363
364 /* write readout protection bit */
365 retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
366 if (retval != ERROR_OK)
367 return retval;
368
369 retval = stm32x_wait_status_busy(bank, 10);
370 if (retval != ERROR_OK)
371 return retval;
372
373 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
374 if (retval != ERROR_OK)
375 return retval;
376
377 return ERROR_OK;
378 }
379
380 static int stm32x_protect_check(struct flash_bank *bank)
381 {
382 struct target *target = bank->target;
383 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
384
385 uint32_t protection;
386 int i, s;
387 int num_bits;
388 int set;
389
390 if (target->state != TARGET_HALTED) {
391 LOG_ERROR("Target not halted");
392 return ERROR_TARGET_NOT_HALTED;
393 }
394
395 int retval = stm32x_check_operation_supported(bank);
396 if (ERROR_OK != retval)
397 return retval;
398
399 /* medium density - each bit refers to a 4bank protection
400 * high density - each bit refers to a 2bank protection */
401 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
402 if (retval != ERROR_OK)
403 return retval;
404
405 /* medium density - each protection bit is for 4 * 1K pages
406 * high density - each protection bit is for 2 * 2K pages */
407 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
408
409 if (stm32x_info->ppage_size == 2) {
410 /* high density flash/connectivity line protection */
411
412 set = 1;
413
414 if (protection & (1 << 31))
415 set = 0;
416
417 /* bit 31 controls sector 62 - 255 protection for high density
418 * bit 31 controls sector 62 - 127 protection for connectivity line */
419 for (s = 62; s < bank->num_sectors; s++)
420 bank->sectors[s].is_protected = set;
421
422 if (bank->num_sectors > 61)
423 num_bits = 31;
424
425 for (i = 0; i < num_bits; i++) {
426 set = 1;
427
428 if (protection & (1 << i))
429 set = 0;
430
431 for (s = 0; s < stm32x_info->ppage_size; s++)
432 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
433 }
434 } else {
435 /* low/medium density flash protection */
436 for (i = 0; i < num_bits; i++) {
437 set = 1;
438
439 if (protection & (1 << i))
440 set = 0;
441
442 for (s = 0; s < stm32x_info->ppage_size; s++)
443 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
444 }
445 }
446
447 return ERROR_OK;
448 }
449
450 static int stm32x_erase(struct flash_bank *bank, int first, int last)
451 {
452 struct target *target = bank->target;
453 int i;
454
455 if (bank->target->state != TARGET_HALTED) {
456 LOG_ERROR("Target not halted");
457 return ERROR_TARGET_NOT_HALTED;
458 }
459
460 if ((first == 0) && (last == (bank->num_sectors - 1)))
461 return stm32x_mass_erase(bank);
462
463 /* unlock flash registers */
464 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
465 if (retval != ERROR_OK)
466 return retval;
467 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
468 if (retval != ERROR_OK)
469 return retval;
470
471 for (i = first; i <= last; i++) {
472 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
473 if (retval != ERROR_OK)
474 return retval;
475 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
476 bank->base + bank->sectors[i].offset);
477 if (retval != ERROR_OK)
478 return retval;
479 retval = target_write_u32(target,
480 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
481 if (retval != ERROR_OK)
482 return retval;
483
484 retval = stm32x_wait_status_busy(bank, 100);
485 if (retval != ERROR_OK)
486 return retval;
487
488 bank->sectors[i].is_erased = 1;
489 }
490
491 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
492 if (retval != ERROR_OK)
493 return retval;
494
495 return ERROR_OK;
496 }
497
498 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
499 {
500 struct stm32x_flash_bank *stm32x_info = NULL;
501 struct target *target = bank->target;
502 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
503 int i, reg, bit;
504 int status;
505 uint32_t protection;
506
507 stm32x_info = bank->driver_priv;
508
509 if (target->state != TARGET_HALTED) {
510 LOG_ERROR("Target not halted");
511 return ERROR_TARGET_NOT_HALTED;
512 }
513
514 int retval = stm32x_check_operation_supported(bank);
515 if (ERROR_OK != retval)
516 return retval;
517
518 if ((first % stm32x_info->ppage_size) != 0) {
519 LOG_WARNING("aligned start protect sector to a %d sector boundary",
520 stm32x_info->ppage_size);
521 first = first - (first % stm32x_info->ppage_size);
522 }
523 if (((last + 1) % stm32x_info->ppage_size) != 0) {
524 LOG_WARNING("aligned end protect sector to a %d sector boundary",
525 stm32x_info->ppage_size);
526 last++;
527 last = last - (last % stm32x_info->ppage_size);
528 last--;
529 }
530
531 /* medium density - each bit refers to a 4bank protection
532 * high density - each bit refers to a 2bank protection */
533 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
534 if (retval != ERROR_OK)
535 return retval;
536
537 prot_reg[0] = (uint16_t)protection;
538 prot_reg[1] = (uint16_t)(protection >> 8);
539 prot_reg[2] = (uint16_t)(protection >> 16);
540 prot_reg[3] = (uint16_t)(protection >> 24);
541
542 if (stm32x_info->ppage_size == 2) {
543 /* high density flash */
544
545 /* bit 7 controls sector 62 - 255 protection */
546 if (last > 61) {
547 if (set)
548 prot_reg[3] &= ~(1 << 7);
549 else
550 prot_reg[3] |= (1 << 7);
551 }
552
553 if (first > 61)
554 first = 62;
555 if (last > 61)
556 last = 61;
557
558 for (i = first; i <= last; i++) {
559 reg = (i / stm32x_info->ppage_size) / 8;
560 bit = (i / stm32x_info->ppage_size) - (reg * 8);
561
562 if (set)
563 prot_reg[reg] &= ~(1 << bit);
564 else
565 prot_reg[reg] |= (1 << bit);
566 }
567 } else {
568 /* medium density flash */
569 for (i = first; i <= last; i++) {
570 reg = (i / stm32x_info->ppage_size) / 8;
571 bit = (i / stm32x_info->ppage_size) - (reg * 8);
572
573 if (set)
574 prot_reg[reg] &= ~(1 << bit);
575 else
576 prot_reg[reg] |= (1 << bit);
577 }
578 }
579
580 status = stm32x_erase_options(bank);
581 if (status != ERROR_OK)
582 return status;
583
584 stm32x_info->option_bytes.protection[0] = prot_reg[0];
585 stm32x_info->option_bytes.protection[1] = prot_reg[1];
586 stm32x_info->option_bytes.protection[2] = prot_reg[2];
587 stm32x_info->option_bytes.protection[3] = prot_reg[3];
588
589 return stm32x_write_options(bank);
590 }
591
592 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
593 uint32_t offset, uint32_t count)
594 {
595 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
596 struct target *target = bank->target;
597 uint32_t buffer_size = 16384;
598 struct working_area *source;
599 uint32_t address = bank->base + offset;
600 struct reg_param reg_params[5];
601 struct armv7m_algorithm armv7m_info;
602 int retval = ERROR_OK;
603
604 /* see contrib/loaders/flash/stm32f1x.S for src */
605
606 static const uint8_t stm32x_flash_write_code[] = {
607 /* #define STM32_FLASH_SR_OFFSET 0x0C */
608 /* wait_fifo: */
609 0x16, 0x68, /* ldr r6, [r2, #0] */
610 0x00, 0x2e, /* cmp r6, #0 */
611 0x18, 0xd0, /* beq exit */
612 0x55, 0x68, /* ldr r5, [r2, #4] */
613 0xb5, 0x42, /* cmp r5, r6 */
614 0xf9, 0xd0, /* beq wait_fifo */
615 0x2e, 0x88, /* ldrh r6, [r5, #0] */
616 0x26, 0x80, /* strh r6, [r4, #0] */
617 0x02, 0x35, /* adds r5, #2 */
618 0x02, 0x34, /* adds r4, #2 */
619 /* busy: */
620 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
621 0x01, 0x27, /* movs r7, #1 */
622 0x3e, 0x42, /* tst r6, r7 */
623 0xfb, 0xd1, /* bne busy */
624 0x14, 0x27, /* movs r7, #0x14 */
625 0x3e, 0x42, /* tst r6, r7 */
626 0x08, 0xd1, /* bne error */
627 0x9d, 0x42, /* cmp r5, r3 */
628 0x01, 0xd3, /* bcc no_wrap */
629 0x15, 0x46, /* mov r5, r2 */
630 0x08, 0x35, /* adds r5, #8 */
631 /* no_wrap: */
632 0x55, 0x60, /* str r5, [r2, #4] */
633 0x01, 0x39, /* subs r1, r1, #1 */
634 0x00, 0x29, /* cmp r1, #0 */
635 0x02, 0xd0, /* beq exit */
636 0xe5, 0xe7, /* b wait_fifo */
637 /* error: */
638 0x00, 0x20, /* movs r0, #0 */
639 0x50, 0x60, /* str r0, [r2, #4] */
640 /* exit: */
641 0x30, 0x46, /* mov r0, r6 */
642 0x00, 0xbe, /* bkpt #0 */
643 };
644
645 /* flash write code */
646 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
647 &stm32x_info->write_algorithm) != ERROR_OK) {
648 LOG_WARNING("no working area available, can't do block memory writes");
649 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
650 };
651
652 retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
653 sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
654 if (retval != ERROR_OK)
655 return retval;
656
657 /* memory buffer */
658 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
659 buffer_size /= 2;
660 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
661 if (buffer_size <= 256) {
662 /* if we already allocated the writing code, but failed to get a
663 * buffer, free the algorithm */
664 if (stm32x_info->write_algorithm)
665 target_free_working_area(target, stm32x_info->write_algorithm);
666
667 LOG_WARNING("no large enough working area available, can't do block memory writes");
668 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
669 }
670 };
671
672 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
673 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
674 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
675 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
676 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
677
678 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
679 buf_set_u32(reg_params[1].value, 0, 32, count);
680 buf_set_u32(reg_params[2].value, 0, 32, source->address);
681 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
682 buf_set_u32(reg_params[4].value, 0, 32, address);
683
684 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
685 armv7m_info.core_mode = ARMV7M_MODE_ANY;
686
687 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
688 0, NULL,
689 5, reg_params,
690 source->address, source->size,
691 stm32x_info->write_algorithm->address, 0,
692 &armv7m_info);
693
694 if (retval == ERROR_FLASH_OPERATION_FAILED) {
695 LOG_ERROR("flash write failed at address 0x%"PRIx32,
696 buf_get_u32(reg_params[4].value, 0, 32));
697
698 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
699 LOG_ERROR("flash memory not erased before writing");
700 /* Clear but report errors */
701 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
702 }
703
704 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
705 LOG_ERROR("flash memory write protected");
706 /* Clear but report errors */
707 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
708 }
709 }
710
711 target_free_working_area(target, source);
712 target_free_working_area(target, stm32x_info->write_algorithm);
713
714 destroy_reg_param(&reg_params[0]);
715 destroy_reg_param(&reg_params[1]);
716 destroy_reg_param(&reg_params[2]);
717 destroy_reg_param(&reg_params[3]);
718 destroy_reg_param(&reg_params[4]);
719
720 return retval;
721 }
722
723 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
724 uint32_t offset, uint32_t count)
725 {
726 struct target *target = bank->target;
727 uint32_t words_remaining = (count / 2);
728 uint32_t bytes_remaining = (count & 0x00000001);
729 uint32_t address = bank->base + offset;
730 uint32_t bytes_written = 0;
731 int retval;
732
733 if (bank->target->state != TARGET_HALTED) {
734 LOG_ERROR("Target not halted");
735 return ERROR_TARGET_NOT_HALTED;
736 }
737
738 if (offset & 0x1) {
739 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
740 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
741 }
742
743 /* unlock flash registers */
744 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
745 if (retval != ERROR_OK)
746 return retval;
747 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
748 if (retval != ERROR_OK)
749 return retval;
750
751 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
752 if (retval != ERROR_OK)
753 return retval;
754
755 /* multiple half words (2-byte) to be programmed? */
756 if (words_remaining > 0) {
757 /* try using a block write */
758 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
759 if (retval != ERROR_OK) {
760 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
761 /* if block write failed (no sufficient working area),
762 * we use normal (slow) single dword accesses */
763 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
764 }
765 } else {
766 buffer += words_remaining * 2;
767 address += words_remaining * 2;
768 words_remaining = 0;
769 }
770 }
771
772 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
773 goto reset_pg_and_lock;
774
775 while (words_remaining > 0) {
776 uint16_t value;
777 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
778
779 retval = target_write_u16(target, address, value);
780 if (retval != ERROR_OK)
781 goto reset_pg_and_lock;
782
783 retval = stm32x_wait_status_busy(bank, 5);
784 if (retval != ERROR_OK)
785 goto reset_pg_and_lock;
786
787 bytes_written += 2;
788 words_remaining--;
789 address += 2;
790 }
791
792 if (bytes_remaining) {
793 uint16_t value = 0xffff;
794 memcpy(&value, buffer + bytes_written, bytes_remaining);
795
796 retval = target_write_u16(target, address, value);
797 if (retval != ERROR_OK)
798 goto reset_pg_and_lock;
799
800 retval = stm32x_wait_status_busy(bank, 5);
801 if (retval != ERROR_OK)
802 goto reset_pg_and_lock;
803 }
804
805 return target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
806
807 reset_pg_and_lock:
808 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
809 return retval;
810 }
811
812 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
813 {
814 /* This check the device CPUID core register to detect
815 * the M0 from the M3 devices. */
816
817 struct target *target = bank->target;
818 uint32_t cpuid, device_id_register = 0;
819
820 /* Get the CPUID from the ARM Core
821 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
822 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
823 if (retval != ERROR_OK)
824 return retval;
825
826 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
827 /* 0xC20 is M0 devices */
828 device_id_register = 0x40015800;
829 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
830 /* 0xC23 is M3 devices */
831 device_id_register = 0xE0042000;
832 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
833 /* 0xC24 is M4 devices */
834 device_id_register = 0xE0042000;
835 } else {
836 LOG_ERROR("Cannot identify target as a stm32x");
837 return ERROR_FAIL;
838 }
839
840 /* read stm32 device id register */
841 retval = target_read_u32(target, device_id_register, device_id);
842 if (retval != ERROR_OK)
843 return retval;
844
845 return retval;
846 }
847
848 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
849 {
850 struct target *target = bank->target;
851 uint32_t cpuid, flash_size_reg;
852
853 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
854 if (retval != ERROR_OK)
855 return retval;
856
857 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
858 /* 0xC20 is M0 devices */
859 flash_size_reg = 0x1FFFF7CC;
860 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
861 /* 0xC23 is M3 devices */
862 flash_size_reg = 0x1FFFF7E0;
863 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
864 /* 0xC24 is M4 devices */
865 flash_size_reg = 0x1FFFF7CC;
866 } else {
867 LOG_ERROR("Cannot identify target as a stm32x");
868 return ERROR_FAIL;
869 }
870
871 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
872 if (retval != ERROR_OK)
873 return retval;
874
875 return retval;
876 }
877
878 static int stm32x_probe(struct flash_bank *bank)
879 {
880 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
881 int i;
882 uint16_t flash_size_in_kb;
883 uint16_t max_flash_size_in_kb;
884 uint32_t device_id;
885 int page_size;
886 uint32_t base_address = 0x08000000;
887
888 stm32x_info->probed = 0;
889 stm32x_info->register_base = FLASH_REG_BASE_B0;
890
891 /* read stm32 device id register */
892 int retval = stm32x_get_device_id(bank, &device_id);
893 if (retval != ERROR_OK)
894 return retval;
895
896 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
897
898 /* set page size, protection granularity and max flash size depending on family */
899 switch (device_id & 0xfff) {
900 case 0x410: /* medium density */
901 page_size = 1024;
902 stm32x_info->ppage_size = 4;
903 max_flash_size_in_kb = 128;
904 break;
905 case 0x412: /* low density */
906 page_size = 1024;
907 stm32x_info->ppage_size = 4;
908 max_flash_size_in_kb = 32;
909 break;
910 case 0x414: /* high density */
911 page_size = 2048;
912 stm32x_info->ppage_size = 2;
913 max_flash_size_in_kb = 512;
914 break;
915 case 0x418: /* connectivity line density */
916 page_size = 2048;
917 stm32x_info->ppage_size = 2;
918 max_flash_size_in_kb = 256;
919 break;
920 case 0x420: /* value line density */
921 page_size = 1024;
922 stm32x_info->ppage_size = 4;
923 max_flash_size_in_kb = 128;
924 break;
925 case 0x422: /* stm32f30x */
926 page_size = 2048;
927 stm32x_info->ppage_size = 2;
928 max_flash_size_in_kb = 256;
929 break;
930 case 0x428: /* value line High density */
931 page_size = 2048;
932 stm32x_info->ppage_size = 4;
933 max_flash_size_in_kb = 128;
934 break;
935 case 0x430: /* xl line density (dual flash banks) */
936 page_size = 2048;
937 stm32x_info->ppage_size = 2;
938 max_flash_size_in_kb = 1024;
939 stm32x_info->has_dual_banks = true;
940 break;
941 case 0x432: /* stm32f37x */
942 page_size = 2048;
943 stm32x_info->ppage_size = 2;
944 max_flash_size_in_kb = 256;
945 break;
946 case 0x440: /* stm32f0x */
947 page_size = 1024;
948 stm32x_info->ppage_size = 4;
949 max_flash_size_in_kb = 64;
950 break;
951 default:
952 LOG_WARNING("Cannot identify target as a STM32 family.");
953 return ERROR_FAIL;
954 }
955
956 /* get flash size from target. */
957 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
958
959 /* failed reading flash size or flash size invalid (early silicon),
960 * default to max target family */
961 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
962 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
963 max_flash_size_in_kb);
964 flash_size_in_kb = max_flash_size_in_kb;
965 }
966
967 if (stm32x_info->has_dual_banks) {
968 /* split reported size into matching bank */
969 if (bank->base != 0x08080000) {
970 /* bank 0 will be fixed 512k */
971 flash_size_in_kb = 512;
972 } else {
973 flash_size_in_kb -= 512;
974 /* bank1 also uses a register offset */
975 stm32x_info->register_base = FLASH_REG_BASE_B1;
976 base_address = 0x08080000;
977 }
978 }
979
980 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
981
982 /* did we assign flash size? */
983 assert(flash_size_in_kb != 0xffff);
984
985 /* calculate numbers of pages */
986 int num_pages = flash_size_in_kb * 1024 / page_size;
987
988 /* check that calculation result makes sense */
989 assert(num_pages > 0);
990
991 if (bank->sectors) {
992 free(bank->sectors);
993 bank->sectors = NULL;
994 }
995
996 bank->base = base_address;
997 bank->size = (num_pages * page_size);
998 bank->num_sectors = num_pages;
999 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1000
1001 for (i = 0; i < num_pages; i++) {
1002 bank->sectors[i].offset = i * page_size;
1003 bank->sectors[i].size = page_size;
1004 bank->sectors[i].is_erased = -1;
1005 bank->sectors[i].is_protected = 1;
1006 }
1007
1008 stm32x_info->probed = 1;
1009
1010 return ERROR_OK;
1011 }
1012
1013 static int stm32x_auto_probe(struct flash_bank *bank)
1014 {
1015 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1016 if (stm32x_info->probed)
1017 return ERROR_OK;
1018 return stm32x_probe(bank);
1019 }
1020
1021 #if 0
1022 COMMAND_HANDLER(stm32x_handle_part_id_command)
1023 {
1024 return ERROR_OK;
1025 }
1026 #endif
1027
1028 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1029 {
1030 uint32_t device_id;
1031 int printed;
1032
1033 /* read stm32 device id register */
1034 int retval = stm32x_get_device_id(bank, &device_id);
1035 if (retval != ERROR_OK)
1036 return retval;
1037
1038 if ((device_id & 0xfff) == 0x410) {
1039 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1040 buf += printed;
1041 buf_size -= printed;
1042
1043 switch (device_id >> 16) {
1044 case 0x0000:
1045 snprintf(buf, buf_size, "A");
1046 break;
1047
1048 case 0x2000:
1049 snprintf(buf, buf_size, "B");
1050 break;
1051
1052 case 0x2001:
1053 snprintf(buf, buf_size, "Z");
1054 break;
1055
1056 case 0x2003:
1057 snprintf(buf, buf_size, "Y");
1058 break;
1059
1060 default:
1061 snprintf(buf, buf_size, "unknown");
1062 break;
1063 }
1064 } else if ((device_id & 0xfff) == 0x412) {
1065 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1066 buf += printed;
1067 buf_size -= printed;
1068
1069 switch (device_id >> 16) {
1070 case 0x1000:
1071 snprintf(buf, buf_size, "A");
1072 break;
1073
1074 default:
1075 snprintf(buf, buf_size, "unknown");
1076 break;
1077 }
1078 } else if ((device_id & 0xfff) == 0x414) {
1079 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1080 buf += printed;
1081 buf_size -= printed;
1082
1083 switch (device_id >> 16) {
1084 case 0x1000:
1085 snprintf(buf, buf_size, "A");
1086 break;
1087
1088 case 0x1001:
1089 snprintf(buf, buf_size, "Z");
1090 break;
1091
1092 default:
1093 snprintf(buf, buf_size, "unknown");
1094 break;
1095 }
1096 } else if ((device_id & 0xfff) == 0x418) {
1097 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1098 buf += printed;
1099 buf_size -= printed;
1100
1101 switch (device_id >> 16) {
1102 case 0x1000:
1103 snprintf(buf, buf_size, "A");
1104 break;
1105
1106 case 0x1001:
1107 snprintf(buf, buf_size, "Z");
1108 break;
1109
1110 default:
1111 snprintf(buf, buf_size, "unknown");
1112 break;
1113 }
1114 } else if ((device_id & 0xfff) == 0x420) {
1115 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1116 buf += printed;
1117 buf_size -= printed;
1118
1119 switch (device_id >> 16) {
1120 case 0x1000:
1121 snprintf(buf, buf_size, "A");
1122 break;
1123
1124 case 0x1001:
1125 snprintf(buf, buf_size, "Z");
1126 break;
1127
1128 default:
1129 snprintf(buf, buf_size, "unknown");
1130 break;
1131 }
1132 } else if ((device_id & 0xfff) == 0x422) {
1133 printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
1134 buf += printed;
1135 buf_size -= printed;
1136
1137 switch (device_id >> 16) {
1138 case 0x1000:
1139 snprintf(buf, buf_size, "1.0");
1140 break;
1141
1142 default:
1143 snprintf(buf, buf_size, "unknown");
1144 break;
1145 }
1146 } else if ((device_id & 0xfff) == 0x428) {
1147 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1148 buf += printed;
1149 buf_size -= printed;
1150
1151 switch (device_id >> 16) {
1152 case 0x1000:
1153 snprintf(buf, buf_size, "A");
1154 break;
1155
1156 case 0x1001:
1157 snprintf(buf, buf_size, "Z");
1158 break;
1159
1160 default:
1161 snprintf(buf, buf_size, "unknown");
1162 break;
1163 }
1164 } else if ((device_id & 0xfff) == 0x430) {
1165 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1166 buf += printed;
1167 buf_size -= printed;
1168
1169 switch (device_id >> 16) {
1170 case 0x1000:
1171 snprintf(buf, buf_size, "A");
1172 break;
1173
1174 default:
1175 snprintf(buf, buf_size, "unknown");
1176 break;
1177 }
1178 } else if ((device_id & 0xfff) == 0x432) {
1179 printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
1180 buf += printed;
1181 buf_size -= printed;
1182
1183 switch (device_id >> 16) {
1184 case 0x1000:
1185 snprintf(buf, buf_size, "1.0");
1186 break;
1187
1188 default:
1189 snprintf(buf, buf_size, "unknown");
1190 break;
1191 }
1192 } else if ((device_id & 0xfff) == 0x440) {
1193 printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
1194 buf += printed;
1195 buf_size -= printed;
1196
1197 switch (device_id >> 16) {
1198 case 0x1000:
1199 snprintf(buf, buf_size, "1.0");
1200 break;
1201
1202 case 0x2000:
1203 snprintf(buf, buf_size, "2.0");
1204 break;
1205
1206 default:
1207 snprintf(buf, buf_size, "unknown");
1208 break;
1209 }
1210 } else {
1211 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1212 return ERROR_FAIL;
1213 }
1214
1215 return ERROR_OK;
1216 }
1217
1218 COMMAND_HANDLER(stm32x_handle_lock_command)
1219 {
1220 struct target *target = NULL;
1221 struct stm32x_flash_bank *stm32x_info = NULL;
1222
1223 if (CMD_ARGC < 1)
1224 return ERROR_COMMAND_SYNTAX_ERROR;
1225
1226 struct flash_bank *bank;
1227 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1228 if (ERROR_OK != retval)
1229 return retval;
1230
1231 stm32x_info = bank->driver_priv;
1232
1233 target = bank->target;
1234
1235 if (target->state != TARGET_HALTED) {
1236 LOG_ERROR("Target not halted");
1237 return ERROR_TARGET_NOT_HALTED;
1238 }
1239
1240 retval = stm32x_check_operation_supported(bank);
1241 if (ERROR_OK != retval)
1242 return retval;
1243
1244 if (stm32x_erase_options(bank) != ERROR_OK) {
1245 command_print(CMD_CTX, "stm32x failed to erase options");
1246 return ERROR_OK;
1247 }
1248
1249 /* set readout protection */
1250 stm32x_info->option_bytes.RDP = 0;
1251
1252 if (stm32x_write_options(bank) != ERROR_OK) {
1253 command_print(CMD_CTX, "stm32x failed to lock device");
1254 return ERROR_OK;
1255 }
1256
1257 command_print(CMD_CTX, "stm32x locked");
1258
1259 return ERROR_OK;
1260 }
1261
1262 COMMAND_HANDLER(stm32x_handle_unlock_command)
1263 {
1264 struct target *target = NULL;
1265
1266 if (CMD_ARGC < 1)
1267 return ERROR_COMMAND_SYNTAX_ERROR;
1268
1269 struct flash_bank *bank;
1270 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1271 if (ERROR_OK != retval)
1272 return retval;
1273
1274 target = bank->target;
1275
1276 if (target->state != TARGET_HALTED) {
1277 LOG_ERROR("Target not halted");
1278 return ERROR_TARGET_NOT_HALTED;
1279 }
1280
1281 retval = stm32x_check_operation_supported(bank);
1282 if (ERROR_OK != retval)
1283 return retval;
1284
1285 if (stm32x_erase_options(bank) != ERROR_OK) {
1286 command_print(CMD_CTX, "stm32x failed to unlock device");
1287 return ERROR_OK;
1288 }
1289
1290 if (stm32x_write_options(bank) != ERROR_OK) {
1291 command_print(CMD_CTX, "stm32x failed to lock device");
1292 return ERROR_OK;
1293 }
1294
1295 command_print(CMD_CTX, "stm32x unlocked.\n"
1296 "INFO: a reset or power cycle is required "
1297 "for the new settings to take effect.");
1298
1299 return ERROR_OK;
1300 }
1301
1302 COMMAND_HANDLER(stm32x_handle_options_read_command)
1303 {
1304 uint32_t optionbyte;
1305 struct target *target = NULL;
1306 struct stm32x_flash_bank *stm32x_info = NULL;
1307
1308 if (CMD_ARGC < 1)
1309 return ERROR_COMMAND_SYNTAX_ERROR;
1310
1311 struct flash_bank *bank;
1312 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1313 if (ERROR_OK != retval)
1314 return retval;
1315
1316 stm32x_info = bank->driver_priv;
1317
1318 target = bank->target;
1319
1320 if (target->state != TARGET_HALTED) {
1321 LOG_ERROR("Target not halted");
1322 return ERROR_TARGET_NOT_HALTED;
1323 }
1324
1325 retval = stm32x_check_operation_supported(bank);
1326 if (ERROR_OK != retval)
1327 return retval;
1328
1329 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1330 if (retval != ERROR_OK)
1331 return retval;
1332 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1333
1334 if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
1335 command_print(CMD_CTX, "Option Byte Complement Error");
1336
1337 if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
1338 command_print(CMD_CTX, "Readout Protection On");
1339 else
1340 command_print(CMD_CTX, "Readout Protection Off");
1341
1342 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
1343 command_print(CMD_CTX, "Software Watchdog");
1344 else
1345 command_print(CMD_CTX, "Hardware Watchdog");
1346
1347 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
1348 command_print(CMD_CTX, "Stop: No reset generated");
1349 else
1350 command_print(CMD_CTX, "Stop: Reset generated");
1351
1352 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
1353 command_print(CMD_CTX, "Standby: No reset generated");
1354 else
1355 command_print(CMD_CTX, "Standby: Reset generated");
1356
1357 if (stm32x_info->has_dual_banks) {
1358 if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
1359 command_print(CMD_CTX, "Boot: Bank 0");
1360 else
1361 command_print(CMD_CTX, "Boot: Bank 1");
1362 }
1363
1364 return ERROR_OK;
1365 }
1366
1367 COMMAND_HANDLER(stm32x_handle_options_write_command)
1368 {
1369 struct target *target = NULL;
1370 struct stm32x_flash_bank *stm32x_info = NULL;
1371 uint16_t optionbyte = 0xF8;
1372
1373 if (CMD_ARGC < 4)
1374 return ERROR_COMMAND_SYNTAX_ERROR;
1375
1376 struct flash_bank *bank;
1377 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1378 if (ERROR_OK != retval)
1379 return retval;
1380
1381 stm32x_info = bank->driver_priv;
1382
1383 target = bank->target;
1384
1385 if (target->state != TARGET_HALTED) {
1386 LOG_ERROR("Target not halted");
1387 return ERROR_TARGET_NOT_HALTED;
1388 }
1389
1390 retval = stm32x_check_operation_supported(bank);
1391 if (ERROR_OK != retval)
1392 return retval;
1393
1394 /* REVISIT: ignores some options which we will display...
1395 * and doesn't insist on the specified syntax.
1396 */
1397
1398 /* OPT_RDWDGSW */
1399 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1400 optionbyte |= (1 << 0);
1401 else /* REVISIT must be "HWWDG" then ... */
1402 optionbyte &= ~(1 << 0);
1403
1404 /* OPT_RDRSTSTOP */
1405 if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
1406 optionbyte |= (1 << 1);
1407 else /* REVISIT must be "RSTSTNDBY" then ... */
1408 optionbyte &= ~(1 << 1);
1409
1410 /* OPT_RDRSTSTDBY */
1411 if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
1412 optionbyte |= (1 << 2);
1413 else /* REVISIT must be "RSTSTOP" then ... */
1414 optionbyte &= ~(1 << 2);
1415
1416 if (CMD_ARGC > 4 && stm32x_info->has_dual_banks) {
1417 /* OPT_BFB2 */
1418 if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
1419 optionbyte |= (1 << 3);
1420 else
1421 optionbyte &= ~(1 << 3);
1422 }
1423
1424 if (stm32x_erase_options(bank) != ERROR_OK) {
1425 command_print(CMD_CTX, "stm32x failed to erase options");
1426 return ERROR_OK;
1427 }
1428
1429 stm32x_info->option_bytes.user_options = optionbyte;
1430
1431 if (stm32x_write_options(bank) != ERROR_OK) {
1432 command_print(CMD_CTX, "stm32x failed to write options");
1433 return ERROR_OK;
1434 }
1435
1436 command_print(CMD_CTX, "stm32x write options complete.\n"
1437 "INFO: a reset or power cycle is required "
1438 "for the new settings to take effect.");
1439
1440 return ERROR_OK;
1441 }
1442
1443 static int stm32x_mass_erase(struct flash_bank *bank)
1444 {
1445 struct target *target = bank->target;
1446
1447 if (target->state != TARGET_HALTED) {
1448 LOG_ERROR("Target not halted");
1449 return ERROR_TARGET_NOT_HALTED;
1450 }
1451
1452 /* unlock option flash registers */
1453 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1454 if (retval != ERROR_OK)
1455 return retval;
1456 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1457 if (retval != ERROR_OK)
1458 return retval;
1459
1460 /* mass erase flash memory */
1461 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1462 if (retval != ERROR_OK)
1463 return retval;
1464 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1465 FLASH_MER | FLASH_STRT);
1466 if (retval != ERROR_OK)
1467 return retval;
1468
1469 retval = stm32x_wait_status_busy(bank, 100);
1470 if (retval != ERROR_OK)
1471 return retval;
1472
1473 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1474 if (retval != ERROR_OK)
1475 return retval;
1476
1477 return ERROR_OK;
1478 }
1479
1480 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1481 {
1482 int i;
1483
1484 if (CMD_ARGC < 1)
1485 return ERROR_COMMAND_SYNTAX_ERROR;
1486
1487 struct flash_bank *bank;
1488 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1489 if (ERROR_OK != retval)
1490 return retval;
1491
1492 retval = stm32x_mass_erase(bank);
1493 if (retval == ERROR_OK) {
1494 /* set all sectors as erased */
1495 for (i = 0; i < bank->num_sectors; i++)
1496 bank->sectors[i].is_erased = 1;
1497
1498 command_print(CMD_CTX, "stm32x mass erase complete");
1499 } else
1500 command_print(CMD_CTX, "stm32x mass erase failed");
1501
1502 return retval;
1503 }
1504
1505 static const struct command_registration stm32x_exec_command_handlers[] = {
1506 {
1507 .name = "lock",
1508 .handler = stm32x_handle_lock_command,
1509 .mode = COMMAND_EXEC,
1510 .usage = "bank_id",
1511 .help = "Lock entire flash device.",
1512 },
1513 {
1514 .name = "unlock",
1515 .handler = stm32x_handle_unlock_command,
1516 .mode = COMMAND_EXEC,
1517 .usage = "bank_id",
1518 .help = "Unlock entire protected flash device.",
1519 },
1520 {
1521 .name = "mass_erase",
1522 .handler = stm32x_handle_mass_erase_command,
1523 .mode = COMMAND_EXEC,
1524 .usage = "bank_id",
1525 .help = "Erase entire flash device.",
1526 },
1527 {
1528 .name = "options_read",
1529 .handler = stm32x_handle_options_read_command,
1530 .mode = COMMAND_EXEC,
1531 .usage = "bank_id",
1532 .help = "Read and display device option byte.",
1533 },
1534 {
1535 .name = "options_write",
1536 .handler = stm32x_handle_options_write_command,
1537 .mode = COMMAND_EXEC,
1538 .usage = "bank_id ('SWWDG'|'HWWDG') "
1539 "('RSTSTNDBY'|'NORSTSTNDBY') "
1540 "('RSTSTOP'|'NORSTSTOP')",
1541 .help = "Replace bits in device option byte.",
1542 },
1543 COMMAND_REGISTRATION_DONE
1544 };
1545
1546 static const struct command_registration stm32x_command_handlers[] = {
1547 {
1548 .name = "stm32f1x",
1549 .mode = COMMAND_ANY,
1550 .help = "stm32f1x flash command group",
1551 .usage = "",
1552 .chain = stm32x_exec_command_handlers,
1553 },
1554 COMMAND_REGISTRATION_DONE
1555 };
1556
1557 struct flash_driver stm32f1x_flash = {
1558 .name = "stm32f1x",
1559 .commands = stm32x_command_handlers,
1560 .flash_bank_command = stm32x_flash_bank_command,
1561 .erase = stm32x_erase,
1562 .protect = stm32x_protect,
1563 .write = stm32x_write,
1564 .read = default_flash_read,
1565 .probe = stm32x_probe,
1566 .auto_probe = stm32x_auto_probe,
1567 .erase_check = default_flash_blank_check,
1568 .protect_check = stm32x_protect_check,
1569 .info = get_stm32x_info,
1570 };