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[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 /* timeout values */
105
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
108
109 struct stm32x_options {
110 uint8_t rdp;
111 uint8_t user;
112 uint16_t data;
113 uint32_t protection;
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 int probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
125 uint8_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = 0;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
153
154 return ERROR_OK;
155 }
156
157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
158 {
159 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
160 return reg + stm32x_info->register_base;
161 }
162
163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
164 {
165 struct target *target = bank->target;
166 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
167 }
168
169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
170 {
171 struct target *target = bank->target;
172 uint32_t status;
173 int retval = ERROR_OK;
174
175 /* wait for busy to clear */
176 for (;;) {
177 retval = stm32x_get_flash_status(bank, &status);
178 if (retval != ERROR_OK)
179 return retval;
180 LOG_DEBUG("status: 0x%" PRIx32 "", status);
181 if ((status & FLASH_BSY) == 0)
182 break;
183 if (timeout-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
185 return ERROR_FAIL;
186 }
187 alive_sleep(1);
188 }
189
190 if (status & FLASH_WRPRTERR) {
191 LOG_ERROR("stm32x device protected");
192 retval = ERROR_FAIL;
193 }
194
195 if (status & FLASH_PGERR) {
196 LOG_ERROR("stm32x device programming failed");
197 retval = ERROR_FAIL;
198 }
199
200 /* Clear but report errors */
201 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
202 /* If this operation fails, we ignore it and report the original
203 * retval
204 */
205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
206 FLASH_WRPRTERR | FLASH_PGERR);
207 }
208 return retval;
209 }
210
211 static int stm32x_check_operation_supported(struct flash_bank *bank)
212 {
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
214
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
218 LOG_ERROR("Option Byte Operation's must use bank0");
219 return ERROR_FLASH_OPERATION_FAILED;
220 }
221
222 return ERROR_OK;
223 }
224
225 static int stm32x_read_options(struct flash_bank *bank)
226 {
227 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
228 struct target *target = bank->target;
229 uint32_t option_bytes;
230 int retval;
231
232 /* read user and read protection option bytes */
233 retval = target_read_u32(target, STM32_OB_RDP, &option_bytes);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.rdp = option_bytes & 0xFF;
238 stm32x_info->option_bytes.user = (option_bytes >> 16) & 0xFF;
239
240 /* read user data option bytes */
241 retval = target_read_u32(target, STM32_OB_DATA0, &option_bytes);
242 if (retval != ERROR_OK)
243 return retval;
244
245 stm32x_info->option_bytes.data = ((option_bytes >> 8) & 0xFF00) | (option_bytes & 0xFF);
246
247 /* read write protection option bytes */
248 retval = target_read_u32(target, STM32_OB_WRP0, &option_bytes);
249 if (retval != ERROR_OK)
250 return retval;
251
252 stm32x_info->option_bytes.protection = ((option_bytes >> 8) & 0xFF00) | (option_bytes & 0xFF);
253
254 retval = target_read_u32(target, STM32_OB_WRP2, &option_bytes);
255 if (retval != ERROR_OK)
256 return retval;
257
258 stm32x_info->option_bytes.protection |= (((option_bytes >> 8) & 0xFF00) | (option_bytes & 0xFF)) << 16;
259
260 return ERROR_OK;
261 }
262
263 static int stm32x_erase_options(struct flash_bank *bank)
264 {
265 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
266 struct target *target = bank->target;
267
268 /* read current options */
269 stm32x_read_options(bank);
270
271 /* unlock flash registers */
272 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
273 if (retval != ERROR_OK)
274 return retval;
275
276 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
277 if (retval != ERROR_OK)
278 return retval;
279
280 /* unlock option flash registers */
281 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
282 if (retval != ERROR_OK)
283 return retval;
284 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
285 if (retval != ERROR_OK)
286 return retval;
287
288 /* erase option bytes */
289 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
290 if (retval != ERROR_OK)
291 return retval;
292 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
293 if (retval != ERROR_OK)
294 return retval;
295
296 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
297 if (retval != ERROR_OK)
298 return retval;
299
300 /* clear read protection option byte
301 * this will also force a device unlock if set */
302 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
303
304 return ERROR_OK;
305 }
306
307 static int stm32x_write_options(struct flash_bank *bank)
308 {
309 struct stm32x_flash_bank *stm32x_info = NULL;
310 struct target *target = bank->target;
311
312 stm32x_info = bank->driver_priv;
313
314 /* unlock flash registers */
315 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
316 if (retval != ERROR_OK)
317 return retval;
318 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
319 if (retval != ERROR_OK)
320 return retval;
321
322 /* unlock option flash registers */
323 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
324 if (retval != ERROR_OK)
325 return retval;
326 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
327 if (retval != ERROR_OK)
328 return retval;
329
330 /* program option bytes */
331 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
332 if (retval != ERROR_OK)
333 return retval;
334
335 uint8_t opt_bytes[16];
336
337 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
338 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
339 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
340 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
341 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
342 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
343 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
344 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
345
346 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
347 if (retval != ERROR_OK) {
348 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
349 LOG_ERROR("working area required to erase options bytes");
350 return retval;
351 }
352
353 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
354 if (retval != ERROR_OK)
355 return retval;
356
357 return ERROR_OK;
358 }
359
360 static int stm32x_protect_check(struct flash_bank *bank)
361 {
362 struct target *target = bank->target;
363 uint32_t protection;
364
365 int retval = stm32x_check_operation_supported(bank);
366 if (ERROR_OK != retval)
367 return retval;
368
369 /* medium density - each bit refers to a 4 sector protection block
370 * high density - each bit refers to a 2 sector protection block
371 * bit 31 refers to all remaining sectors in a bank */
372 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
373 if (retval != ERROR_OK)
374 return retval;
375
376 for (int i = 0; i < bank->num_prot_blocks; i++)
377 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
378
379 return ERROR_OK;
380 }
381
382 static int stm32x_erase(struct flash_bank *bank, int first, int last)
383 {
384 struct target *target = bank->target;
385 int i;
386
387 if (bank->target->state != TARGET_HALTED) {
388 LOG_ERROR("Target not halted");
389 return ERROR_TARGET_NOT_HALTED;
390 }
391
392 if ((first == 0) && (last == (bank->num_sectors - 1)))
393 return stm32x_mass_erase(bank);
394
395 /* unlock flash registers */
396 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
397 if (retval != ERROR_OK)
398 return retval;
399 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
400 if (retval != ERROR_OK)
401 return retval;
402
403 for (i = first; i <= last; i++) {
404 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
405 if (retval != ERROR_OK)
406 return retval;
407 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
408 bank->base + bank->sectors[i].offset);
409 if (retval != ERROR_OK)
410 return retval;
411 retval = target_write_u32(target,
412 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
413 if (retval != ERROR_OK)
414 return retval;
415
416 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
417 if (retval != ERROR_OK)
418 return retval;
419
420 bank->sectors[i].is_erased = 1;
421 }
422
423 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
424 if (retval != ERROR_OK)
425 return retval;
426
427 return ERROR_OK;
428 }
429
430 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
431 {
432 struct target *target = bank->target;
433 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
434
435 if (target->state != TARGET_HALTED) {
436 LOG_ERROR("Target not halted");
437 return ERROR_TARGET_NOT_HALTED;
438 }
439
440 int retval = stm32x_check_operation_supported(bank);
441 if (retval != ERROR_OK)
442 return retval;
443
444 retval = stm32x_erase_options(bank);
445 if (retval != ERROR_OK) {
446 LOG_ERROR("stm32x failed to erase options");
447 return retval;
448 }
449
450 for (int i = first; i <= last; i++) {
451 if (set)
452 stm32x_info->option_bytes.protection &= ~(1 << i);
453 else
454 stm32x_info->option_bytes.protection |= (1 << i);
455 }
456
457 return stm32x_write_options(bank);
458 }
459
460 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
461 uint32_t address, uint32_t count)
462 {
463 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
464 struct target *target = bank->target;
465 uint32_t buffer_size = 16384;
466 struct working_area *write_algorithm;
467 struct working_area *source;
468 struct reg_param reg_params[5];
469 struct armv7m_algorithm armv7m_info;
470 int retval = ERROR_OK;
471
472 static const uint8_t stm32x_flash_write_code[] = {
473 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
474 };
475
476 /* flash write code */
477 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
478 &write_algorithm) != ERROR_OK) {
479 LOG_WARNING("no working area available, can't do block memory writes");
480 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
481 }
482
483 retval = target_write_buffer(target, write_algorithm->address,
484 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
485 if (retval != ERROR_OK) {
486 target_free_working_area(target, write_algorithm);
487 return retval;
488 }
489
490 /* memory buffer */
491 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
492 buffer_size /= 2;
493 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
494 if (buffer_size <= 256) {
495 /* we already allocated the writing code, but failed to get a
496 * buffer, free the algorithm */
497 target_free_working_area(target, write_algorithm);
498
499 LOG_WARNING("no large enough working area available, can't do block memory writes");
500 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
501 }
502 }
503
504 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
505 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
506 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
507 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
508 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
509
510 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
511 buf_set_u32(reg_params[1].value, 0, 32, count);
512 buf_set_u32(reg_params[2].value, 0, 32, source->address);
513 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
514 buf_set_u32(reg_params[4].value, 0, 32, address);
515
516 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
517 armv7m_info.core_mode = ARM_MODE_THREAD;
518
519 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
520 0, NULL,
521 5, reg_params,
522 source->address, source->size,
523 write_algorithm->address, 0,
524 &armv7m_info);
525
526 if (retval == ERROR_FLASH_OPERATION_FAILED) {
527 LOG_ERROR("flash write failed at address 0x%"PRIx32,
528 buf_get_u32(reg_params[4].value, 0, 32));
529
530 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
531 LOG_ERROR("flash memory not erased before writing");
532 /* Clear but report errors */
533 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
534 }
535
536 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
537 LOG_ERROR("flash memory write protected");
538 /* Clear but report errors */
539 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
540 }
541 }
542
543 target_free_working_area(target, source);
544 target_free_working_area(target, write_algorithm);
545
546 destroy_reg_param(&reg_params[0]);
547 destroy_reg_param(&reg_params[1]);
548 destroy_reg_param(&reg_params[2]);
549 destroy_reg_param(&reg_params[3]);
550 destroy_reg_param(&reg_params[4]);
551
552 return retval;
553 }
554
555 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
556 uint32_t offset, uint32_t count)
557 {
558 struct target *target = bank->target;
559 uint8_t *new_buffer = NULL;
560
561 if (bank->target->state != TARGET_HALTED) {
562 LOG_ERROR("Target not halted");
563 return ERROR_TARGET_NOT_HALTED;
564 }
565
566 if (offset & 0x1) {
567 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
568 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
569 }
570
571 /* If there's an odd number of bytes, the data has to be padded. Duplicate
572 * the buffer and use the normal code path with a single block write since
573 * it's probably cheaper than to special case the last odd write using
574 * discrete accesses. */
575 if (count & 1) {
576 new_buffer = malloc(count + 1);
577 if (new_buffer == NULL) {
578 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
579 return ERROR_FAIL;
580 }
581 LOG_INFO("odd number of bytes to write, padding with 0xff");
582 buffer = memcpy(new_buffer, buffer, count);
583 new_buffer[count++] = 0xff;
584 }
585
586 uint32_t words_remaining = count / 2;
587 int retval, retval2;
588
589 /* unlock flash registers */
590 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
591 if (retval != ERROR_OK)
592 goto cleanup;
593 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
594 if (retval != ERROR_OK)
595 goto cleanup;
596
597 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
598 if (retval != ERROR_OK)
599 goto cleanup;
600
601 /* try using a block write */
602 retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
603
604 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
605 /* if block write failed (no sufficient working area),
606 * we use normal (slow) single halfword accesses */
607 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
608
609 while (words_remaining > 0) {
610 uint16_t value;
611 memcpy(&value, buffer, sizeof(uint16_t));
612
613 retval = target_write_u16(target, bank->base + offset, value);
614 if (retval != ERROR_OK)
615 goto reset_pg_and_lock;
616
617 retval = stm32x_wait_status_busy(bank, 5);
618 if (retval != ERROR_OK)
619 goto reset_pg_and_lock;
620
621 words_remaining--;
622 buffer += 2;
623 offset += 2;
624 }
625 }
626
627 reset_pg_and_lock:
628 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
629 if (retval == ERROR_OK)
630 retval = retval2;
631
632 cleanup:
633 if (new_buffer)
634 free(new_buffer);
635
636 return retval;
637 }
638
639 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
640 {
641 /* This check the device CPUID core register to detect
642 * the M0 from the M3 devices. */
643
644 struct target *target = bank->target;
645 uint32_t cpuid, device_id_register = 0;
646
647 /* Get the CPUID from the ARM Core
648 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
649 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
650 if (retval != ERROR_OK)
651 return retval;
652
653 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
654 /* 0xC20 is M0 devices */
655 device_id_register = 0x40015800;
656 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
657 /* 0xC23 is M3 devices */
658 device_id_register = 0xE0042000;
659 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
660 /* 0xC24 is M4 devices */
661 device_id_register = 0xE0042000;
662 } else {
663 LOG_ERROR("Cannot identify target as a stm32x");
664 return ERROR_FAIL;
665 }
666
667 /* read stm32 device id register */
668 retval = target_read_u32(target, device_id_register, device_id);
669 if (retval != ERROR_OK)
670 return retval;
671
672 return retval;
673 }
674
675 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
676 {
677 struct target *target = bank->target;
678 uint32_t cpuid, flash_size_reg;
679
680 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
681 if (retval != ERROR_OK)
682 return retval;
683
684 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
685 /* 0xC20 is M0 devices */
686 flash_size_reg = 0x1FFFF7CC;
687 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
688 /* 0xC23 is M3 devices */
689 flash_size_reg = 0x1FFFF7E0;
690 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
691 /* 0xC24 is M4 devices */
692 flash_size_reg = 0x1FFFF7CC;
693 } else {
694 LOG_ERROR("Cannot identify target as a stm32x");
695 return ERROR_FAIL;
696 }
697
698 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
699 if (retval != ERROR_OK)
700 return retval;
701
702 return retval;
703 }
704
705 static int stm32x_probe(struct flash_bank *bank)
706 {
707 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
708 uint16_t flash_size_in_kb;
709 uint16_t max_flash_size_in_kb;
710 uint32_t device_id;
711 int page_size;
712 uint32_t base_address = 0x08000000;
713
714 stm32x_info->probed = 0;
715 stm32x_info->register_base = FLASH_REG_BASE_B0;
716 stm32x_info->user_data_offset = 10;
717 stm32x_info->option_offset = 0;
718
719 /* default factory read protection level 0 */
720 stm32x_info->default_rdp = 0xA5;
721
722 /* read stm32 device id register */
723 int retval = stm32x_get_device_id(bank, &device_id);
724 if (retval != ERROR_OK)
725 return retval;
726
727 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
728
729 /* set page size, protection granularity and max flash size depending on family */
730 switch (device_id & 0xfff) {
731 case 0x410: /* medium density */
732 page_size = 1024;
733 stm32x_info->ppage_size = 4;
734 max_flash_size_in_kb = 128;
735 break;
736 case 0x412: /* low density */
737 page_size = 1024;
738 stm32x_info->ppage_size = 4;
739 max_flash_size_in_kb = 32;
740 break;
741 case 0x414: /* high density */
742 page_size = 2048;
743 stm32x_info->ppage_size = 2;
744 max_flash_size_in_kb = 512;
745 break;
746 case 0x418: /* connectivity line density */
747 page_size = 2048;
748 stm32x_info->ppage_size = 2;
749 max_flash_size_in_kb = 256;
750 break;
751 case 0x420: /* value line density */
752 page_size = 1024;
753 stm32x_info->ppage_size = 4;
754 max_flash_size_in_kb = 128;
755 break;
756 case 0x422: /* stm32f302/3xb/c */
757 page_size = 2048;
758 stm32x_info->ppage_size = 2;
759 max_flash_size_in_kb = 256;
760 stm32x_info->user_data_offset = 16;
761 stm32x_info->option_offset = 6;
762 stm32x_info->default_rdp = 0xAA;
763 stm32x_info->can_load_options = true;
764 break;
765 case 0x446: /* stm32f303xD/E */
766 page_size = 2048;
767 stm32x_info->ppage_size = 2;
768 max_flash_size_in_kb = 512;
769 stm32x_info->user_data_offset = 16;
770 stm32x_info->option_offset = 6;
771 stm32x_info->default_rdp = 0xAA;
772 stm32x_info->can_load_options = true;
773 break;
774 case 0x428: /* value line High density */
775 page_size = 2048;
776 stm32x_info->ppage_size = 4;
777 max_flash_size_in_kb = 128;
778 break;
779 case 0x430: /* xl line density (dual flash banks) */
780 page_size = 2048;
781 stm32x_info->ppage_size = 2;
782 max_flash_size_in_kb = 1024;
783 stm32x_info->has_dual_banks = true;
784 break;
785 case 0x432: /* stm32f37x */
786 page_size = 2048;
787 stm32x_info->ppage_size = 2;
788 max_flash_size_in_kb = 256;
789 stm32x_info->user_data_offset = 16;
790 stm32x_info->option_offset = 6;
791 stm32x_info->default_rdp = 0xAA;
792 stm32x_info->can_load_options = true;
793 break;
794 case 0x438: /* stm32f33x */
795 case 0x439: /* stm32f302x6/8 */
796 page_size = 2048;
797 stm32x_info->ppage_size = 2;
798 max_flash_size_in_kb = 64;
799 stm32x_info->user_data_offset = 16;
800 stm32x_info->option_offset = 6;
801 stm32x_info->default_rdp = 0xAA;
802 stm32x_info->can_load_options = true;
803 break;
804 case 0x440: /* stm32f05x */
805 case 0x444: /* stm32f03x */
806 case 0x445: /* stm32f04x */
807 page_size = 1024;
808 stm32x_info->ppage_size = 4;
809 max_flash_size_in_kb = 64;
810 stm32x_info->user_data_offset = 16;
811 stm32x_info->option_offset = 6;
812 stm32x_info->default_rdp = 0xAA;
813 stm32x_info->can_load_options = true;
814 break;
815 case 0x448: /* stm32f07x */
816 case 0x442: /* stm32f09x */
817 page_size = 2048;
818 stm32x_info->ppage_size = 4;
819 max_flash_size_in_kb = 256;
820 stm32x_info->user_data_offset = 16;
821 stm32x_info->option_offset = 6;
822 stm32x_info->default_rdp = 0xAA;
823 stm32x_info->can_load_options = true;
824 break;
825 default:
826 LOG_WARNING("Cannot identify target as a STM32 family.");
827 return ERROR_FAIL;
828 }
829
830 /* get flash size from target. */
831 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
832
833 /* failed reading flash size or flash size invalid (early silicon),
834 * default to max target family */
835 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
836 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
837 max_flash_size_in_kb);
838 flash_size_in_kb = max_flash_size_in_kb;
839 }
840
841 if (stm32x_info->has_dual_banks) {
842 /* split reported size into matching bank */
843 if (bank->base != 0x08080000) {
844 /* bank 0 will be fixed 512k */
845 flash_size_in_kb = 512;
846 } else {
847 flash_size_in_kb -= 512;
848 /* bank1 also uses a register offset */
849 stm32x_info->register_base = FLASH_REG_BASE_B1;
850 base_address = 0x08080000;
851 }
852 }
853
854 /* if the user sets the size manually then ignore the probed value
855 * this allows us to work around devices that have a invalid flash size register value */
856 if (stm32x_info->user_bank_size) {
857 LOG_INFO("ignoring flash probed value, using configured bank size");
858 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
859 }
860
861 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
862
863 /* did we assign flash size? */
864 assert(flash_size_in_kb != 0xffff);
865
866 /* calculate numbers of pages */
867 int num_pages = flash_size_in_kb * 1024 / page_size;
868
869 /* check that calculation result makes sense */
870 assert(num_pages > 0);
871
872 if (bank->sectors) {
873 free(bank->sectors);
874 bank->sectors = NULL;
875 }
876
877 if (bank->prot_blocks) {
878 free(bank->prot_blocks);
879 bank->prot_blocks = NULL;
880 }
881
882 bank->base = base_address;
883 bank->size = (num_pages * page_size);
884
885 bank->num_sectors = num_pages;
886 bank->sectors = alloc_block_array(0, page_size, num_pages);
887 if (!bank->sectors)
888 return ERROR_FAIL;
889
890 /* calculate number of write protection blocks */
891 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
892 if (num_prot_blocks > 32)
893 num_prot_blocks = 32;
894
895 bank->num_prot_blocks = num_prot_blocks;
896 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
897 if (!bank->prot_blocks)
898 return ERROR_FAIL;
899
900 if (num_prot_blocks == 32)
901 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
902
903 stm32x_info->probed = 1;
904
905 return ERROR_OK;
906 }
907
908 static int stm32x_auto_probe(struct flash_bank *bank)
909 {
910 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
911 if (stm32x_info->probed)
912 return ERROR_OK;
913 return stm32x_probe(bank);
914 }
915
916 #if 0
917 COMMAND_HANDLER(stm32x_handle_part_id_command)
918 {
919 return ERROR_OK;
920 }
921 #endif
922
923 static const char *get_stm32f0_revision(uint16_t rev_id)
924 {
925 const char *rev_str = NULL;
926
927 switch (rev_id) {
928 case 0x1000:
929 rev_str = "1.0";
930 break;
931 case 0x2000:
932 rev_str = "2.0";
933 break;
934 }
935 return rev_str;
936 }
937
938 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
939 {
940 uint32_t dbgmcu_idcode;
941
942 /* read stm32 device id register */
943 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
944 if (retval != ERROR_OK)
945 return retval;
946
947 uint16_t device_id = dbgmcu_idcode & 0xfff;
948 uint16_t rev_id = dbgmcu_idcode >> 16;
949 const char *device_str;
950 const char *rev_str = NULL;
951
952 switch (device_id) {
953 case 0x410:
954 device_str = "STM32F10x (Medium Density)";
955
956 switch (rev_id) {
957 case 0x0000:
958 rev_str = "A";
959 break;
960
961 case 0x2000:
962 rev_str = "B";
963 break;
964
965 case 0x2001:
966 rev_str = "Z";
967 break;
968
969 case 0x2003:
970 rev_str = "Y";
971 break;
972 }
973 break;
974
975 case 0x412:
976 device_str = "STM32F10x (Low Density)";
977
978 switch (rev_id) {
979 case 0x1000:
980 rev_str = "A";
981 break;
982 }
983 break;
984
985 case 0x414:
986 device_str = "STM32F10x (High Density)";
987
988 switch (rev_id) {
989 case 0x1000:
990 rev_str = "A";
991 break;
992
993 case 0x1001:
994 rev_str = "Z";
995 break;
996
997 case 0x1003:
998 rev_str = "Y";
999 break;
1000 }
1001 break;
1002
1003 case 0x418:
1004 device_str = "STM32F10x (Connectivity)";
1005
1006 switch (rev_id) {
1007 case 0x1000:
1008 rev_str = "A";
1009 break;
1010
1011 case 0x1001:
1012 rev_str = "Z";
1013 break;
1014 }
1015 break;
1016
1017 case 0x420:
1018 device_str = "STM32F100 (Low/Medium Density)";
1019
1020 switch (rev_id) {
1021 case 0x1000:
1022 rev_str = "A";
1023 break;
1024
1025 case 0x1001:
1026 rev_str = "Z";
1027 break;
1028 }
1029 break;
1030
1031 case 0x422:
1032 device_str = "STM32F302xB/C";
1033
1034 switch (rev_id) {
1035 case 0x1000:
1036 rev_str = "A";
1037 break;
1038
1039 case 0x1001:
1040 rev_str = "Z";
1041 break;
1042
1043 case 0x1003:
1044 rev_str = "Y";
1045 break;
1046
1047 case 0x2000:
1048 rev_str = "B";
1049 break;
1050 }
1051 break;
1052
1053 case 0x428:
1054 device_str = "STM32F100 (High Density)";
1055
1056 switch (rev_id) {
1057 case 0x1000:
1058 rev_str = "A";
1059 break;
1060
1061 case 0x1001:
1062 rev_str = "Z";
1063 break;
1064 }
1065 break;
1066
1067 case 0x430:
1068 device_str = "STM32F10x (XL Density)";
1069
1070 switch (rev_id) {
1071 case 0x1000:
1072 rev_str = "A";
1073 break;
1074 }
1075 break;
1076
1077 case 0x432:
1078 device_str = "STM32F37x";
1079
1080 switch (rev_id) {
1081 case 0x1000:
1082 rev_str = "A";
1083 break;
1084
1085 case 0x2000:
1086 rev_str = "B";
1087 break;
1088 }
1089 break;
1090
1091 case 0x438:
1092 device_str = "STM32F33x";
1093
1094 switch (rev_id) {
1095 case 0x1000:
1096 rev_str = "A";
1097 break;
1098 }
1099 break;
1100
1101 case 0x439:
1102 device_str = "STM32F302x6/8";
1103
1104 switch (rev_id) {
1105 case 0x1000:
1106 rev_str = "A";
1107 break;
1108
1109 case 0x1001:
1110 rev_str = "Z";
1111 break;
1112 }
1113 break;
1114
1115 case 0x444:
1116 device_str = "STM32F03x";
1117 rev_str = get_stm32f0_revision(rev_id);
1118 break;
1119
1120 case 0x440:
1121 device_str = "STM32F05x";
1122 rev_str = get_stm32f0_revision(rev_id);
1123 break;
1124
1125 case 0x445:
1126 device_str = "STM32F04x";
1127 rev_str = get_stm32f0_revision(rev_id);
1128 break;
1129
1130 case 0x446:
1131 device_str = "STM32F303xD/E";
1132 switch (rev_id) {
1133 case 0x1000:
1134 rev_str = "A";
1135 break;
1136 }
1137 break;
1138
1139 case 0x448:
1140 device_str = "STM32F07x";
1141 rev_str = get_stm32f0_revision(rev_id);
1142 break;
1143
1144 case 0x442:
1145 device_str = "STM32F09x";
1146 rev_str = get_stm32f0_revision(rev_id);
1147 break;
1148
1149 default:
1150 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1151 return ERROR_FAIL;
1152 }
1153
1154 if (rev_str != NULL)
1155 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1156 else
1157 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1158
1159 return ERROR_OK;
1160 }
1161
1162 COMMAND_HANDLER(stm32x_handle_lock_command)
1163 {
1164 struct target *target = NULL;
1165 struct stm32x_flash_bank *stm32x_info = NULL;
1166
1167 if (CMD_ARGC < 1)
1168 return ERROR_COMMAND_SYNTAX_ERROR;
1169
1170 struct flash_bank *bank;
1171 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1172 if (ERROR_OK != retval)
1173 return retval;
1174
1175 stm32x_info = bank->driver_priv;
1176
1177 target = bank->target;
1178
1179 if (target->state != TARGET_HALTED) {
1180 LOG_ERROR("Target not halted");
1181 return ERROR_TARGET_NOT_HALTED;
1182 }
1183
1184 retval = stm32x_check_operation_supported(bank);
1185 if (ERROR_OK != retval)
1186 return retval;
1187
1188 if (stm32x_erase_options(bank) != ERROR_OK) {
1189 command_print(CMD_CTX, "stm32x failed to erase options");
1190 return ERROR_OK;
1191 }
1192
1193 /* set readout protection */
1194 stm32x_info->option_bytes.rdp = 0;
1195
1196 if (stm32x_write_options(bank) != ERROR_OK) {
1197 command_print(CMD_CTX, "stm32x failed to lock device");
1198 return ERROR_OK;
1199 }
1200
1201 command_print(CMD_CTX, "stm32x locked");
1202
1203 return ERROR_OK;
1204 }
1205
1206 COMMAND_HANDLER(stm32x_handle_unlock_command)
1207 {
1208 struct target *target = NULL;
1209
1210 if (CMD_ARGC < 1)
1211 return ERROR_COMMAND_SYNTAX_ERROR;
1212
1213 struct flash_bank *bank;
1214 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1215 if (ERROR_OK != retval)
1216 return retval;
1217
1218 target = bank->target;
1219
1220 if (target->state != TARGET_HALTED) {
1221 LOG_ERROR("Target not halted");
1222 return ERROR_TARGET_NOT_HALTED;
1223 }
1224
1225 retval = stm32x_check_operation_supported(bank);
1226 if (ERROR_OK != retval)
1227 return retval;
1228
1229 if (stm32x_erase_options(bank) != ERROR_OK) {
1230 command_print(CMD_CTX, "stm32x failed to erase options");
1231 return ERROR_OK;
1232 }
1233
1234 if (stm32x_write_options(bank) != ERROR_OK) {
1235 command_print(CMD_CTX, "stm32x failed to unlock device");
1236 return ERROR_OK;
1237 }
1238
1239 command_print(CMD_CTX, "stm32x unlocked.\n"
1240 "INFO: a reset or power cycle is required "
1241 "for the new settings to take effect.");
1242
1243 return ERROR_OK;
1244 }
1245
1246 COMMAND_HANDLER(stm32x_handle_options_read_command)
1247 {
1248 uint32_t optionbyte, protection;
1249 struct target *target = NULL;
1250 struct stm32x_flash_bank *stm32x_info = NULL;
1251
1252 if (CMD_ARGC < 1)
1253 return ERROR_COMMAND_SYNTAX_ERROR;
1254
1255 struct flash_bank *bank;
1256 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1257 if (ERROR_OK != retval)
1258 return retval;
1259
1260 stm32x_info = bank->driver_priv;
1261
1262 target = bank->target;
1263
1264 if (target->state != TARGET_HALTED) {
1265 LOG_ERROR("Target not halted");
1266 return ERROR_TARGET_NOT_HALTED;
1267 }
1268
1269 retval = stm32x_check_operation_supported(bank);
1270 if (ERROR_OK != retval)
1271 return retval;
1272
1273 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1274 if (retval != ERROR_OK)
1275 return retval;
1276
1277 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1278
1279 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1280 if (retval != ERROR_OK)
1281 return retval;
1282
1283 if (optionbyte & (1 << OPT_ERROR))
1284 command_print(CMD_CTX, "option byte complement error");
1285
1286 command_print(CMD_CTX, "option byte register = 0x%" PRIx32 "", optionbyte);
1287 command_print(CMD_CTX, "write protection register = 0x%" PRIx32 "", protection);
1288
1289 command_print(CMD_CTX, "read protection: %s",
1290 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1291
1292 /* user option bytes are offset depending on variant */
1293 optionbyte >>= stm32x_info->option_offset;
1294
1295 command_print(CMD_CTX, "watchdog: %sware",
1296 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1297
1298 command_print(CMD_CTX, "stop mode: %sreset generated upon entry",
1299 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1300
1301 command_print(CMD_CTX, "standby mode: %sreset generated upon entry",
1302 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1303
1304 if (stm32x_info->has_dual_banks)
1305 command_print(CMD_CTX, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1306
1307 command_print(CMD_CTX, "user data = 0x%02" PRIx16 "", user_data);
1308
1309 return ERROR_OK;
1310 }
1311
1312 COMMAND_HANDLER(stm32x_handle_options_write_command)
1313 {
1314 struct target *target = NULL;
1315 struct stm32x_flash_bank *stm32x_info = NULL;
1316 uint8_t optionbyte;
1317 uint16_t useropt;
1318
1319 if (CMD_ARGC < 2)
1320 return ERROR_COMMAND_SYNTAX_ERROR;
1321
1322 struct flash_bank *bank;
1323 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1324 if (ERROR_OK != retval)
1325 return retval;
1326
1327 stm32x_info = bank->driver_priv;
1328
1329 target = bank->target;
1330
1331 if (target->state != TARGET_HALTED) {
1332 LOG_ERROR("Target not halted");
1333 return ERROR_TARGET_NOT_HALTED;
1334 }
1335
1336 retval = stm32x_check_operation_supported(bank);
1337 if (ERROR_OK != retval)
1338 return retval;
1339
1340 retval = stm32x_read_options(bank);
1341 if (ERROR_OK != retval)
1342 return retval;
1343
1344 /* start with current options */
1345 optionbyte = stm32x_info->option_bytes.user;
1346 useropt = stm32x_info->option_bytes.data;
1347
1348 /* skip over flash bank */
1349 CMD_ARGC--;
1350 CMD_ARGV++;
1351
1352 while (CMD_ARGC) {
1353 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1354 optionbyte |= (1 << 0);
1355 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1356 optionbyte &= ~(1 << 0);
1357 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1358 optionbyte |= (1 << 1);
1359 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1360 optionbyte &= ~(1 << 1);
1361 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1362 optionbyte |= (1 << 2);
1363 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1364 optionbyte &= ~(1 << 2);
1365 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1366 if (CMD_ARGC < 2)
1367 return ERROR_COMMAND_SYNTAX_ERROR;
1368 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1369 CMD_ARGC--;
1370 CMD_ARGV++;
1371 }
1372 else if (stm32x_info->has_dual_banks) {
1373 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1374 optionbyte |= (1 << 3);
1375 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1376 optionbyte &= ~(1 << 3);
1377 else
1378 return ERROR_COMMAND_SYNTAX_ERROR;
1379 } else
1380 return ERROR_COMMAND_SYNTAX_ERROR;
1381 CMD_ARGC--;
1382 CMD_ARGV++;
1383 }
1384
1385 if (stm32x_erase_options(bank) != ERROR_OK) {
1386 command_print(CMD_CTX, "stm32x failed to erase options");
1387 return ERROR_OK;
1388 }
1389
1390 stm32x_info->option_bytes.user = optionbyte;
1391 stm32x_info->option_bytes.data = useropt;
1392
1393 if (stm32x_write_options(bank) != ERROR_OK) {
1394 command_print(CMD_CTX, "stm32x failed to write options");
1395 return ERROR_OK;
1396 }
1397
1398 command_print(CMD_CTX, "stm32x write options complete.\n"
1399 "INFO: %spower cycle is required "
1400 "for the new settings to take effect.",
1401 stm32x_info->can_load_options
1402 ? "'stm32f1x options_load' command or " : "");
1403
1404 return ERROR_OK;
1405 }
1406
1407 COMMAND_HANDLER(stm32x_handle_options_load_command)
1408 {
1409 if (CMD_ARGC < 1)
1410 return ERROR_COMMAND_SYNTAX_ERROR;
1411
1412 struct flash_bank *bank;
1413 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1414 if (ERROR_OK != retval)
1415 return retval;
1416
1417 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1418
1419 if (!stm32x_info->can_load_options) {
1420 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1421 "required instead.");
1422 return ERROR_FAIL;
1423 }
1424
1425 struct target *target = bank->target;
1426
1427 if (target->state != TARGET_HALTED) {
1428 LOG_ERROR("Target not halted");
1429 return ERROR_TARGET_NOT_HALTED;
1430 }
1431
1432 retval = stm32x_check_operation_supported(bank);
1433 if (ERROR_OK != retval)
1434 return retval;
1435
1436 /* unlock option flash registers */
1437 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1438 if (retval != ERROR_OK)
1439 return retval;
1440 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1441 if (retval != ERROR_OK)
1442 return retval;
1443
1444 /* force re-load of option bytes - generates software reset */
1445 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1446 if (retval != ERROR_OK)
1447 return retval;
1448
1449 return ERROR_OK;
1450 }
1451
1452 static int stm32x_mass_erase(struct flash_bank *bank)
1453 {
1454 struct target *target = bank->target;
1455
1456 if (target->state != TARGET_HALTED) {
1457 LOG_ERROR("Target not halted");
1458 return ERROR_TARGET_NOT_HALTED;
1459 }
1460
1461 /* unlock option flash registers */
1462 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1463 if (retval != ERROR_OK)
1464 return retval;
1465 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1466 if (retval != ERROR_OK)
1467 return retval;
1468
1469 /* mass erase flash memory */
1470 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1471 if (retval != ERROR_OK)
1472 return retval;
1473 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1474 FLASH_MER | FLASH_STRT);
1475 if (retval != ERROR_OK)
1476 return retval;
1477
1478 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1479 if (retval != ERROR_OK)
1480 return retval;
1481
1482 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1483 if (retval != ERROR_OK)
1484 return retval;
1485
1486 return ERROR_OK;
1487 }
1488
1489 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1490 {
1491 int i;
1492
1493 if (CMD_ARGC < 1)
1494 return ERROR_COMMAND_SYNTAX_ERROR;
1495
1496 struct flash_bank *bank;
1497 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1498 if (ERROR_OK != retval)
1499 return retval;
1500
1501 retval = stm32x_mass_erase(bank);
1502 if (retval == ERROR_OK) {
1503 /* set all sectors as erased */
1504 for (i = 0; i < bank->num_sectors; i++)
1505 bank->sectors[i].is_erased = 1;
1506
1507 command_print(CMD_CTX, "stm32x mass erase complete");
1508 } else
1509 command_print(CMD_CTX, "stm32x mass erase failed");
1510
1511 return retval;
1512 }
1513
1514 static const struct command_registration stm32x_exec_command_handlers[] = {
1515 {
1516 .name = "lock",
1517 .handler = stm32x_handle_lock_command,
1518 .mode = COMMAND_EXEC,
1519 .usage = "bank_id",
1520 .help = "Lock entire flash device.",
1521 },
1522 {
1523 .name = "unlock",
1524 .handler = stm32x_handle_unlock_command,
1525 .mode = COMMAND_EXEC,
1526 .usage = "bank_id",
1527 .help = "Unlock entire protected flash device.",
1528 },
1529 {
1530 .name = "mass_erase",
1531 .handler = stm32x_handle_mass_erase_command,
1532 .mode = COMMAND_EXEC,
1533 .usage = "bank_id",
1534 .help = "Erase entire flash device.",
1535 },
1536 {
1537 .name = "options_read",
1538 .handler = stm32x_handle_options_read_command,
1539 .mode = COMMAND_EXEC,
1540 .usage = "bank_id",
1541 .help = "Read and display device option bytes.",
1542 },
1543 {
1544 .name = "options_write",
1545 .handler = stm32x_handle_options_write_command,
1546 .mode = COMMAND_EXEC,
1547 .usage = "bank_id ('SWWDG'|'HWWDG') "
1548 "('RSTSTNDBY'|'NORSTSTNDBY') "
1549 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1550 .help = "Replace bits in device option bytes.",
1551 },
1552 {
1553 .name = "options_load",
1554 .handler = stm32x_handle_options_load_command,
1555 .mode = COMMAND_EXEC,
1556 .usage = "bank_id",
1557 .help = "Force re-load of device option bytes.",
1558 },
1559 COMMAND_REGISTRATION_DONE
1560 };
1561
1562 static const struct command_registration stm32x_command_handlers[] = {
1563 {
1564 .name = "stm32f1x",
1565 .mode = COMMAND_ANY,
1566 .help = "stm32f1x flash command group",
1567 .usage = "",
1568 .chain = stm32x_exec_command_handlers,
1569 },
1570 COMMAND_REGISTRATION_DONE
1571 };
1572
1573 struct flash_driver stm32f1x_flash = {
1574 .name = "stm32f1x",
1575 .commands = stm32x_command_handlers,
1576 .flash_bank_command = stm32x_flash_bank_command,
1577 .erase = stm32x_erase,
1578 .protect = stm32x_protect,
1579 .write = stm32x_write,
1580 .read = default_flash_read,
1581 .probe = stm32x_probe,
1582 .auto_probe = stm32x_auto_probe,
1583 .erase_check = default_flash_blank_check,
1584 .protect_check = stm32x_protect_check,
1585 .info = get_stm32x_info,
1586 .free_driver_priv = default_flash_free_driver_priv,
1587 };
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