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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 /* timeout values */
105
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
108
109 struct stm32x_options {
110 uint8_t rdp;
111 uint8_t user;
112 uint16_t data;
113 uint32_t protection;
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 bool probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
125 uint8_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = false;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
153
154 return ERROR_OK;
155 }
156
157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
158 {
159 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
160 return reg + stm32x_info->register_base;
161 }
162
163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
164 {
165 struct target *target = bank->target;
166 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
167 }
168
169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
170 {
171 struct target *target = bank->target;
172 uint32_t status;
173 int retval = ERROR_OK;
174
175 /* wait for busy to clear */
176 for (;;) {
177 retval = stm32x_get_flash_status(bank, &status);
178 if (retval != ERROR_OK)
179 return retval;
180 LOG_DEBUG("status: 0x%" PRIx32 "", status);
181 if ((status & FLASH_BSY) == 0)
182 break;
183 if (timeout-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
185 return ERROR_FAIL;
186 }
187 alive_sleep(1);
188 }
189
190 if (status & FLASH_WRPRTERR) {
191 LOG_ERROR("stm32x device protected");
192 retval = ERROR_FAIL;
193 }
194
195 if (status & FLASH_PGERR) {
196 LOG_ERROR("stm32x device programming failed");
197 retval = ERROR_FAIL;
198 }
199
200 /* Clear but report errors */
201 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
202 /* If this operation fails, we ignore it and report the original
203 * retval
204 */
205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
206 FLASH_WRPRTERR | FLASH_PGERR);
207 }
208 return retval;
209 }
210
211 static int stm32x_check_operation_supported(struct flash_bank *bank)
212 {
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
214
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
218 LOG_ERROR("Option Byte Operation's must use bank0");
219 return ERROR_FLASH_OPERATION_FAILED;
220 }
221
222 return ERROR_OK;
223 }
224
225 static int stm32x_read_options(struct flash_bank *bank)
226 {
227 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
228 struct target *target = bank->target;
229 uint32_t option_bytes;
230 int retval;
231
232 /* read user and read protection option bytes, user data option bytes */
233 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
238 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
239 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
240
241 /* read write protection option bytes */
242 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
243 if (retval != ERROR_OK)
244 return retval;
245
246 return ERROR_OK;
247 }
248
249 static int stm32x_erase_options(struct flash_bank *bank)
250 {
251 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
252 struct target *target = bank->target;
253
254 /* read current options */
255 stm32x_read_options(bank);
256
257 /* unlock flash registers */
258 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
259 if (retval != ERROR_OK)
260 return retval;
261
262 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
263 if (retval != ERROR_OK)
264 return retval;
265
266 /* unlock option flash registers */
267 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
268 if (retval != ERROR_OK)
269 return retval;
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* erase option bytes */
275 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
276 if (retval != ERROR_OK)
277 return retval;
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
280 return retval;
281
282 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
283 if (retval != ERROR_OK)
284 return retval;
285
286 /* clear read protection option byte
287 * this will also force a device unlock if set */
288 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
289
290 return ERROR_OK;
291 }
292
293 static int stm32x_write_options(struct flash_bank *bank)
294 {
295 struct stm32x_flash_bank *stm32x_info = NULL;
296 struct target *target = bank->target;
297
298 stm32x_info = bank->driver_priv;
299
300 /* unlock flash registers */
301 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
302 if (retval != ERROR_OK)
303 return retval;
304 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
305 if (retval != ERROR_OK)
306 return retval;
307
308 /* unlock option flash registers */
309 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
310 if (retval != ERROR_OK)
311 return retval;
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
313 if (retval != ERROR_OK)
314 return retval;
315
316 /* program option bytes */
317 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
318 if (retval != ERROR_OK)
319 return retval;
320
321 uint8_t opt_bytes[16];
322
323 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
324 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
325 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
326 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
327 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
328 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
329 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
330 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
331
332 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
333 if (retval != ERROR_OK) {
334 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
335 LOG_ERROR("working area required to erase options bytes");
336 return retval;
337 }
338
339 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
340 if (retval != ERROR_OK)
341 return retval;
342
343 return ERROR_OK;
344 }
345
346 static int stm32x_protect_check(struct flash_bank *bank)
347 {
348 struct target *target = bank->target;
349 uint32_t protection;
350
351 int retval = stm32x_check_operation_supported(bank);
352 if (ERROR_OK != retval)
353 return retval;
354
355 /* medium density - each bit refers to a 4 sector protection block
356 * high density - each bit refers to a 2 sector protection block
357 * bit 31 refers to all remaining sectors in a bank */
358 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
359 if (retval != ERROR_OK)
360 return retval;
361
362 for (int i = 0; i < bank->num_prot_blocks; i++)
363 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
364
365 return ERROR_OK;
366 }
367
368 static int stm32x_erase(struct flash_bank *bank, int first, int last)
369 {
370 struct target *target = bank->target;
371
372 if (bank->target->state != TARGET_HALTED) {
373 LOG_ERROR("Target not halted");
374 return ERROR_TARGET_NOT_HALTED;
375 }
376
377 if ((first == 0) && (last == (bank->num_sectors - 1)))
378 return stm32x_mass_erase(bank);
379
380 /* unlock flash registers */
381 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
382 if (retval != ERROR_OK)
383 return retval;
384 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
385 if (retval != ERROR_OK)
386 return retval;
387
388 for (int i = first; i <= last; i++) {
389 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
390 if (retval != ERROR_OK)
391 return retval;
392 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
393 bank->base + bank->sectors[i].offset);
394 if (retval != ERROR_OK)
395 return retval;
396 retval = target_write_u32(target,
397 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
398 if (retval != ERROR_OK)
399 return retval;
400
401 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
402 if (retval != ERROR_OK)
403 return retval;
404
405 bank->sectors[i].is_erased = 1;
406 }
407
408 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
409 if (retval != ERROR_OK)
410 return retval;
411
412 return ERROR_OK;
413 }
414
415 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
416 {
417 struct target *target = bank->target;
418 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
419
420 if (target->state != TARGET_HALTED) {
421 LOG_ERROR("Target not halted");
422 return ERROR_TARGET_NOT_HALTED;
423 }
424
425 int retval = stm32x_check_operation_supported(bank);
426 if (retval != ERROR_OK)
427 return retval;
428
429 retval = stm32x_erase_options(bank);
430 if (retval != ERROR_OK) {
431 LOG_ERROR("stm32x failed to erase options");
432 return retval;
433 }
434
435 for (int i = first; i <= last; i++) {
436 if (set)
437 stm32x_info->option_bytes.protection &= ~(1 << i);
438 else
439 stm32x_info->option_bytes.protection |= (1 << i);
440 }
441
442 return stm32x_write_options(bank);
443 }
444
445 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
446 uint32_t address, uint32_t count)
447 {
448 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
449 struct target *target = bank->target;
450 uint32_t buffer_size = 16384;
451 struct working_area *write_algorithm;
452 struct working_area *source;
453 struct reg_param reg_params[5];
454 struct armv7m_algorithm armv7m_info;
455 int retval = ERROR_OK;
456
457 static const uint8_t stm32x_flash_write_code[] = {
458 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
459 };
460
461 /* flash write code */
462 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
463 &write_algorithm) != ERROR_OK) {
464 LOG_WARNING("no working area available, can't do block memory writes");
465 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
466 }
467
468 retval = target_write_buffer(target, write_algorithm->address,
469 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
470 if (retval != ERROR_OK) {
471 target_free_working_area(target, write_algorithm);
472 return retval;
473 }
474
475 /* memory buffer */
476 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
477 buffer_size /= 2;
478 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
479 if (buffer_size <= 256) {
480 /* we already allocated the writing code, but failed to get a
481 * buffer, free the algorithm */
482 target_free_working_area(target, write_algorithm);
483
484 LOG_WARNING("no large enough working area available, can't do block memory writes");
485 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
486 }
487 }
488
489 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
490 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
491 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
492 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
493 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
494
495 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
496 buf_set_u32(reg_params[1].value, 0, 32, count);
497 buf_set_u32(reg_params[2].value, 0, 32, source->address);
498 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
499 buf_set_u32(reg_params[4].value, 0, 32, address);
500
501 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
502 armv7m_info.core_mode = ARM_MODE_THREAD;
503
504 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
505 0, NULL,
506 5, reg_params,
507 source->address, source->size,
508 write_algorithm->address, 0,
509 &armv7m_info);
510
511 if (retval == ERROR_FLASH_OPERATION_FAILED) {
512 LOG_ERROR("flash write failed at address 0x%"PRIx32,
513 buf_get_u32(reg_params[4].value, 0, 32));
514
515 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
516 LOG_ERROR("flash memory not erased before writing");
517 /* Clear but report errors */
518 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
519 }
520
521 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
522 LOG_ERROR("flash memory write protected");
523 /* Clear but report errors */
524 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
525 }
526 }
527
528 target_free_working_area(target, source);
529 target_free_working_area(target, write_algorithm);
530
531 destroy_reg_param(&reg_params[0]);
532 destroy_reg_param(&reg_params[1]);
533 destroy_reg_param(&reg_params[2]);
534 destroy_reg_param(&reg_params[3]);
535 destroy_reg_param(&reg_params[4]);
536
537 return retval;
538 }
539
540 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
541 uint32_t offset, uint32_t count)
542 {
543 struct target *target = bank->target;
544 uint8_t *new_buffer = NULL;
545
546 if (bank->target->state != TARGET_HALTED) {
547 LOG_ERROR("Target not halted");
548 return ERROR_TARGET_NOT_HALTED;
549 }
550
551 if (offset & 0x1) {
552 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
553 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
554 }
555
556 /* If there's an odd number of bytes, the data has to be padded. Duplicate
557 * the buffer and use the normal code path with a single block write since
558 * it's probably cheaper than to special case the last odd write using
559 * discrete accesses. */
560 if (count & 1) {
561 new_buffer = malloc(count + 1);
562 if (new_buffer == NULL) {
563 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
564 return ERROR_FAIL;
565 }
566 LOG_INFO("odd number of bytes to write, padding with 0xff");
567 buffer = memcpy(new_buffer, buffer, count);
568 new_buffer[count++] = 0xff;
569 }
570
571 uint32_t words_remaining = count / 2;
572 int retval, retval2;
573
574 /* unlock flash registers */
575 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
576 if (retval != ERROR_OK)
577 goto cleanup;
578 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
579 if (retval != ERROR_OK)
580 goto cleanup;
581
582 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
583 if (retval != ERROR_OK)
584 goto cleanup;
585
586 /* try using a block write */
587 retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
588
589 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
590 /* if block write failed (no sufficient working area),
591 * we use normal (slow) single halfword accesses */
592 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
593
594 while (words_remaining > 0) {
595 uint16_t value;
596 memcpy(&value, buffer, sizeof(uint16_t));
597
598 retval = target_write_u16(target, bank->base + offset, value);
599 if (retval != ERROR_OK)
600 goto reset_pg_and_lock;
601
602 retval = stm32x_wait_status_busy(bank, 5);
603 if (retval != ERROR_OK)
604 goto reset_pg_and_lock;
605
606 words_remaining--;
607 buffer += 2;
608 offset += 2;
609 }
610 }
611
612 reset_pg_and_lock:
613 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
614 if (retval == ERROR_OK)
615 retval = retval2;
616
617 cleanup:
618 if (new_buffer)
619 free(new_buffer);
620
621 return retval;
622 }
623
624 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
625 {
626 /* This check the device CPUID core register to detect
627 * the M0 from the M3 devices. */
628
629 struct target *target = bank->target;
630 uint32_t cpuid, device_id_register = 0;
631
632 /* Get the CPUID from the ARM Core
633 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
634 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
635 if (retval != ERROR_OK)
636 return retval;
637
638 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
639 /* 0xC20 is M0 devices */
640 device_id_register = 0x40015800;
641 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
642 /* 0xC23 is M3 devices */
643 device_id_register = 0xE0042000;
644 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
645 /* 0xC24 is M4 devices */
646 device_id_register = 0xE0042000;
647 } else {
648 LOG_ERROR("Cannot identify target as a stm32x");
649 return ERROR_FAIL;
650 }
651
652 /* read stm32 device id register */
653 retval = target_read_u32(target, device_id_register, device_id);
654 if (retval != ERROR_OK)
655 return retval;
656
657 return retval;
658 }
659
660 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
661 {
662 struct target *target = bank->target;
663 uint32_t cpuid, flash_size_reg;
664
665 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
666 if (retval != ERROR_OK)
667 return retval;
668
669 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
670 /* 0xC20 is M0 devices */
671 flash_size_reg = 0x1FFFF7CC;
672 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
673 /* 0xC23 is M3 devices */
674 flash_size_reg = 0x1FFFF7E0;
675 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
676 /* 0xC24 is M4 devices */
677 flash_size_reg = 0x1FFFF7CC;
678 } else {
679 LOG_ERROR("Cannot identify target as a stm32x");
680 return ERROR_FAIL;
681 }
682
683 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
684 if (retval != ERROR_OK)
685 return retval;
686
687 return retval;
688 }
689
690 static int stm32x_probe(struct flash_bank *bank)
691 {
692 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
693 uint16_t flash_size_in_kb;
694 uint16_t max_flash_size_in_kb;
695 uint32_t device_id;
696 int page_size;
697 uint32_t base_address = 0x08000000;
698
699 stm32x_info->probed = false;
700 stm32x_info->register_base = FLASH_REG_BASE_B0;
701 stm32x_info->user_data_offset = 10;
702 stm32x_info->option_offset = 0;
703
704 /* default factory read protection level 0 */
705 stm32x_info->default_rdp = 0xA5;
706
707 /* read stm32 device id register */
708 int retval = stm32x_get_device_id(bank, &device_id);
709 if (retval != ERROR_OK)
710 return retval;
711
712 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
713
714 /* set page size, protection granularity and max flash size depending on family */
715 switch (device_id & 0xfff) {
716 case 0x410: /* medium density */
717 page_size = 1024;
718 stm32x_info->ppage_size = 4;
719 max_flash_size_in_kb = 128;
720 break;
721 case 0x412: /* low density */
722 page_size = 1024;
723 stm32x_info->ppage_size = 4;
724 max_flash_size_in_kb = 32;
725 break;
726 case 0x414: /* high density */
727 page_size = 2048;
728 stm32x_info->ppage_size = 2;
729 max_flash_size_in_kb = 512;
730 break;
731 case 0x418: /* connectivity line density */
732 page_size = 2048;
733 stm32x_info->ppage_size = 2;
734 max_flash_size_in_kb = 256;
735 break;
736 case 0x420: /* value line density */
737 page_size = 1024;
738 stm32x_info->ppage_size = 4;
739 max_flash_size_in_kb = 128;
740 break;
741 case 0x422: /* stm32f302/3xb/c */
742 page_size = 2048;
743 stm32x_info->ppage_size = 2;
744 max_flash_size_in_kb = 256;
745 stm32x_info->user_data_offset = 16;
746 stm32x_info->option_offset = 6;
747 stm32x_info->default_rdp = 0xAA;
748 stm32x_info->can_load_options = true;
749 break;
750 case 0x446: /* stm32f303xD/E */
751 page_size = 2048;
752 stm32x_info->ppage_size = 2;
753 max_flash_size_in_kb = 512;
754 stm32x_info->user_data_offset = 16;
755 stm32x_info->option_offset = 6;
756 stm32x_info->default_rdp = 0xAA;
757 stm32x_info->can_load_options = true;
758 break;
759 case 0x428: /* value line High density */
760 page_size = 2048;
761 stm32x_info->ppage_size = 4;
762 max_flash_size_in_kb = 128;
763 break;
764 case 0x430: /* xl line density (dual flash banks) */
765 page_size = 2048;
766 stm32x_info->ppage_size = 2;
767 max_flash_size_in_kb = 1024;
768 stm32x_info->has_dual_banks = true;
769 break;
770 case 0x432: /* stm32f37x */
771 page_size = 2048;
772 stm32x_info->ppage_size = 2;
773 max_flash_size_in_kb = 256;
774 stm32x_info->user_data_offset = 16;
775 stm32x_info->option_offset = 6;
776 stm32x_info->default_rdp = 0xAA;
777 stm32x_info->can_load_options = true;
778 break;
779 case 0x438: /* stm32f33x */
780 case 0x439: /* stm32f302x6/8 */
781 page_size = 2048;
782 stm32x_info->ppage_size = 2;
783 max_flash_size_in_kb = 64;
784 stm32x_info->user_data_offset = 16;
785 stm32x_info->option_offset = 6;
786 stm32x_info->default_rdp = 0xAA;
787 stm32x_info->can_load_options = true;
788 break;
789 case 0x440: /* stm32f05x */
790 case 0x444: /* stm32f03x */
791 case 0x445: /* stm32f04x */
792 page_size = 1024;
793 stm32x_info->ppage_size = 4;
794 max_flash_size_in_kb = 64;
795 stm32x_info->user_data_offset = 16;
796 stm32x_info->option_offset = 6;
797 stm32x_info->default_rdp = 0xAA;
798 stm32x_info->can_load_options = true;
799 break;
800 case 0x448: /* stm32f07x */
801 case 0x442: /* stm32f09x */
802 page_size = 2048;
803 stm32x_info->ppage_size = 4;
804 max_flash_size_in_kb = 256;
805 stm32x_info->user_data_offset = 16;
806 stm32x_info->option_offset = 6;
807 stm32x_info->default_rdp = 0xAA;
808 stm32x_info->can_load_options = true;
809 break;
810 default:
811 LOG_WARNING("Cannot identify target as a STM32 family.");
812 return ERROR_FAIL;
813 }
814
815 /* get flash size from target. */
816 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
817
818 /* failed reading flash size or flash size invalid (early silicon),
819 * default to max target family */
820 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
821 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
822 max_flash_size_in_kb);
823 flash_size_in_kb = max_flash_size_in_kb;
824 }
825
826 if (stm32x_info->has_dual_banks) {
827 /* split reported size into matching bank */
828 if (bank->base != 0x08080000) {
829 /* bank 0 will be fixed 512k */
830 flash_size_in_kb = 512;
831 } else {
832 flash_size_in_kb -= 512;
833 /* bank1 also uses a register offset */
834 stm32x_info->register_base = FLASH_REG_BASE_B1;
835 base_address = 0x08080000;
836 }
837 }
838
839 /* if the user sets the size manually then ignore the probed value
840 * this allows us to work around devices that have a invalid flash size register value */
841 if (stm32x_info->user_bank_size) {
842 LOG_INFO("ignoring flash probed value, using configured bank size");
843 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
844 }
845
846 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
847
848 /* did we assign flash size? */
849 assert(flash_size_in_kb != 0xffff);
850
851 /* calculate numbers of pages */
852 int num_pages = flash_size_in_kb * 1024 / page_size;
853
854 /* check that calculation result makes sense */
855 assert(num_pages > 0);
856
857 if (bank->sectors) {
858 free(bank->sectors);
859 bank->sectors = NULL;
860 }
861
862 if (bank->prot_blocks) {
863 free(bank->prot_blocks);
864 bank->prot_blocks = NULL;
865 }
866
867 bank->base = base_address;
868 bank->size = (num_pages * page_size);
869
870 bank->num_sectors = num_pages;
871 bank->sectors = alloc_block_array(0, page_size, num_pages);
872 if (!bank->sectors)
873 return ERROR_FAIL;
874
875 /* calculate number of write protection blocks */
876 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
877 if (num_prot_blocks > 32)
878 num_prot_blocks = 32;
879
880 bank->num_prot_blocks = num_prot_blocks;
881 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
882 if (!bank->prot_blocks)
883 return ERROR_FAIL;
884
885 if (num_prot_blocks == 32)
886 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
887
888 stm32x_info->probed = true;
889
890 return ERROR_OK;
891 }
892
893 static int stm32x_auto_probe(struct flash_bank *bank)
894 {
895 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
896 if (stm32x_info->probed)
897 return ERROR_OK;
898 return stm32x_probe(bank);
899 }
900
901 #if 0
902 COMMAND_HANDLER(stm32x_handle_part_id_command)
903 {
904 return ERROR_OK;
905 }
906 #endif
907
908 static const char *get_stm32f0_revision(uint16_t rev_id)
909 {
910 const char *rev_str = NULL;
911
912 switch (rev_id) {
913 case 0x1000:
914 rev_str = "1.0";
915 break;
916 case 0x2000:
917 rev_str = "2.0";
918 break;
919 }
920 return rev_str;
921 }
922
923 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
924 {
925 uint32_t dbgmcu_idcode;
926
927 /* read stm32 device id register */
928 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
929 if (retval != ERROR_OK)
930 return retval;
931
932 uint16_t device_id = dbgmcu_idcode & 0xfff;
933 uint16_t rev_id = dbgmcu_idcode >> 16;
934 const char *device_str;
935 const char *rev_str = NULL;
936
937 switch (device_id) {
938 case 0x410:
939 device_str = "STM32F10x (Medium Density)";
940
941 switch (rev_id) {
942 case 0x0000:
943 rev_str = "A";
944 break;
945
946 case 0x2000:
947 rev_str = "B";
948 break;
949
950 case 0x2001:
951 rev_str = "Z";
952 break;
953
954 case 0x2003:
955 rev_str = "Y";
956 break;
957 }
958 break;
959
960 case 0x412:
961 device_str = "STM32F10x (Low Density)";
962
963 switch (rev_id) {
964 case 0x1000:
965 rev_str = "A";
966 break;
967 }
968 break;
969
970 case 0x414:
971 device_str = "STM32F10x (High Density)";
972
973 switch (rev_id) {
974 case 0x1000:
975 rev_str = "A";
976 break;
977
978 case 0x1001:
979 rev_str = "Z";
980 break;
981
982 case 0x1003:
983 rev_str = "Y";
984 break;
985 }
986 break;
987
988 case 0x418:
989 device_str = "STM32F10x (Connectivity)";
990
991 switch (rev_id) {
992 case 0x1000:
993 rev_str = "A";
994 break;
995
996 case 0x1001:
997 rev_str = "Z";
998 break;
999 }
1000 break;
1001
1002 case 0x420:
1003 device_str = "STM32F100 (Low/Medium Density)";
1004
1005 switch (rev_id) {
1006 case 0x1000:
1007 rev_str = "A";
1008 break;
1009
1010 case 0x1001:
1011 rev_str = "Z";
1012 break;
1013 }
1014 break;
1015
1016 case 0x422:
1017 device_str = "STM32F302xB/C";
1018
1019 switch (rev_id) {
1020 case 0x1000:
1021 rev_str = "A";
1022 break;
1023
1024 case 0x1001:
1025 rev_str = "Z";
1026 break;
1027
1028 case 0x1003:
1029 rev_str = "Y";
1030 break;
1031
1032 case 0x2000:
1033 rev_str = "B";
1034 break;
1035 }
1036 break;
1037
1038 case 0x428:
1039 device_str = "STM32F100 (High Density)";
1040
1041 switch (rev_id) {
1042 case 0x1000:
1043 rev_str = "A";
1044 break;
1045
1046 case 0x1001:
1047 rev_str = "Z";
1048 break;
1049 }
1050 break;
1051
1052 case 0x430:
1053 device_str = "STM32F10x (XL Density)";
1054
1055 switch (rev_id) {
1056 case 0x1000:
1057 rev_str = "A";
1058 break;
1059 }
1060 break;
1061
1062 case 0x432:
1063 device_str = "STM32F37x";
1064
1065 switch (rev_id) {
1066 case 0x1000:
1067 rev_str = "A";
1068 break;
1069
1070 case 0x2000:
1071 rev_str = "B";
1072 break;
1073 }
1074 break;
1075
1076 case 0x438:
1077 device_str = "STM32F33x";
1078
1079 switch (rev_id) {
1080 case 0x1000:
1081 rev_str = "A";
1082 break;
1083 }
1084 break;
1085
1086 case 0x439:
1087 device_str = "STM32F302x6/8";
1088
1089 switch (rev_id) {
1090 case 0x1000:
1091 rev_str = "A";
1092 break;
1093
1094 case 0x1001:
1095 rev_str = "Z";
1096 break;
1097 }
1098 break;
1099
1100 case 0x444:
1101 device_str = "STM32F03x";
1102 rev_str = get_stm32f0_revision(rev_id);
1103 break;
1104
1105 case 0x440:
1106 device_str = "STM32F05x";
1107 rev_str = get_stm32f0_revision(rev_id);
1108 break;
1109
1110 case 0x445:
1111 device_str = "STM32F04x";
1112 rev_str = get_stm32f0_revision(rev_id);
1113 break;
1114
1115 case 0x446:
1116 device_str = "STM32F303xD/E";
1117 switch (rev_id) {
1118 case 0x1000:
1119 rev_str = "A";
1120 break;
1121 }
1122 break;
1123
1124 case 0x448:
1125 device_str = "STM32F07x";
1126 rev_str = get_stm32f0_revision(rev_id);
1127 break;
1128
1129 case 0x442:
1130 device_str = "STM32F09x";
1131 rev_str = get_stm32f0_revision(rev_id);
1132 break;
1133
1134 default:
1135 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1136 return ERROR_FAIL;
1137 }
1138
1139 if (rev_str != NULL)
1140 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1141 else
1142 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1143
1144 return ERROR_OK;
1145 }
1146
1147 COMMAND_HANDLER(stm32x_handle_lock_command)
1148 {
1149 struct target *target = NULL;
1150 struct stm32x_flash_bank *stm32x_info = NULL;
1151
1152 if (CMD_ARGC < 1)
1153 return ERROR_COMMAND_SYNTAX_ERROR;
1154
1155 struct flash_bank *bank;
1156 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1157 if (ERROR_OK != retval)
1158 return retval;
1159
1160 stm32x_info = bank->driver_priv;
1161
1162 target = bank->target;
1163
1164 if (target->state != TARGET_HALTED) {
1165 LOG_ERROR("Target not halted");
1166 return ERROR_TARGET_NOT_HALTED;
1167 }
1168
1169 retval = stm32x_check_operation_supported(bank);
1170 if (ERROR_OK != retval)
1171 return retval;
1172
1173 if (stm32x_erase_options(bank) != ERROR_OK) {
1174 command_print(CMD, "stm32x failed to erase options");
1175 return ERROR_OK;
1176 }
1177
1178 /* set readout protection */
1179 stm32x_info->option_bytes.rdp = 0;
1180
1181 if (stm32x_write_options(bank) != ERROR_OK) {
1182 command_print(CMD, "stm32x failed to lock device");
1183 return ERROR_OK;
1184 }
1185
1186 command_print(CMD, "stm32x locked");
1187
1188 return ERROR_OK;
1189 }
1190
1191 COMMAND_HANDLER(stm32x_handle_unlock_command)
1192 {
1193 struct target *target = NULL;
1194
1195 if (CMD_ARGC < 1)
1196 return ERROR_COMMAND_SYNTAX_ERROR;
1197
1198 struct flash_bank *bank;
1199 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1200 if (ERROR_OK != retval)
1201 return retval;
1202
1203 target = bank->target;
1204
1205 if (target->state != TARGET_HALTED) {
1206 LOG_ERROR("Target not halted");
1207 return ERROR_TARGET_NOT_HALTED;
1208 }
1209
1210 retval = stm32x_check_operation_supported(bank);
1211 if (ERROR_OK != retval)
1212 return retval;
1213
1214 if (stm32x_erase_options(bank) != ERROR_OK) {
1215 command_print(CMD, "stm32x failed to erase options");
1216 return ERROR_OK;
1217 }
1218
1219 if (stm32x_write_options(bank) != ERROR_OK) {
1220 command_print(CMD, "stm32x failed to unlock device");
1221 return ERROR_OK;
1222 }
1223
1224 command_print(CMD, "stm32x unlocked.\n"
1225 "INFO: a reset or power cycle is required "
1226 "for the new settings to take effect.");
1227
1228 return ERROR_OK;
1229 }
1230
1231 COMMAND_HANDLER(stm32x_handle_options_read_command)
1232 {
1233 uint32_t optionbyte, protection;
1234 struct target *target = NULL;
1235 struct stm32x_flash_bank *stm32x_info = NULL;
1236
1237 if (CMD_ARGC < 1)
1238 return ERROR_COMMAND_SYNTAX_ERROR;
1239
1240 struct flash_bank *bank;
1241 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1242 if (ERROR_OK != retval)
1243 return retval;
1244
1245 stm32x_info = bank->driver_priv;
1246
1247 target = bank->target;
1248
1249 if (target->state != TARGET_HALTED) {
1250 LOG_ERROR("Target not halted");
1251 return ERROR_TARGET_NOT_HALTED;
1252 }
1253
1254 retval = stm32x_check_operation_supported(bank);
1255 if (ERROR_OK != retval)
1256 return retval;
1257
1258 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1259 if (retval != ERROR_OK)
1260 return retval;
1261
1262 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1263
1264 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1265 if (retval != ERROR_OK)
1266 return retval;
1267
1268 if (optionbyte & (1 << OPT_ERROR))
1269 command_print(CMD, "option byte complement error");
1270
1271 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1272 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1273
1274 command_print(CMD, "read protection: %s",
1275 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1276
1277 /* user option bytes are offset depending on variant */
1278 optionbyte >>= stm32x_info->option_offset;
1279
1280 command_print(CMD, "watchdog: %sware",
1281 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1282
1283 command_print(CMD, "stop mode: %sreset generated upon entry",
1284 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1285
1286 command_print(CMD, "standby mode: %sreset generated upon entry",
1287 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1288
1289 if (stm32x_info->has_dual_banks)
1290 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1291
1292 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1293
1294 return ERROR_OK;
1295 }
1296
1297 COMMAND_HANDLER(stm32x_handle_options_write_command)
1298 {
1299 struct target *target = NULL;
1300 struct stm32x_flash_bank *stm32x_info = NULL;
1301 uint8_t optionbyte;
1302 uint16_t useropt;
1303
1304 if (CMD_ARGC < 2)
1305 return ERROR_COMMAND_SYNTAX_ERROR;
1306
1307 struct flash_bank *bank;
1308 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1309 if (ERROR_OK != retval)
1310 return retval;
1311
1312 stm32x_info = bank->driver_priv;
1313
1314 target = bank->target;
1315
1316 if (target->state != TARGET_HALTED) {
1317 LOG_ERROR("Target not halted");
1318 return ERROR_TARGET_NOT_HALTED;
1319 }
1320
1321 retval = stm32x_check_operation_supported(bank);
1322 if (ERROR_OK != retval)
1323 return retval;
1324
1325 retval = stm32x_read_options(bank);
1326 if (ERROR_OK != retval)
1327 return retval;
1328
1329 /* start with current options */
1330 optionbyte = stm32x_info->option_bytes.user;
1331 useropt = stm32x_info->option_bytes.data;
1332
1333 /* skip over flash bank */
1334 CMD_ARGC--;
1335 CMD_ARGV++;
1336
1337 while (CMD_ARGC) {
1338 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1339 optionbyte |= (1 << 0);
1340 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1341 optionbyte &= ~(1 << 0);
1342 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1343 optionbyte |= (1 << 1);
1344 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1345 optionbyte &= ~(1 << 1);
1346 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1347 optionbyte |= (1 << 2);
1348 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1349 optionbyte &= ~(1 << 2);
1350 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1351 if (CMD_ARGC < 2)
1352 return ERROR_COMMAND_SYNTAX_ERROR;
1353 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1354 CMD_ARGC--;
1355 CMD_ARGV++;
1356 }
1357 else if (stm32x_info->has_dual_banks) {
1358 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1359 optionbyte |= (1 << 3);
1360 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1361 optionbyte &= ~(1 << 3);
1362 else
1363 return ERROR_COMMAND_SYNTAX_ERROR;
1364 } else
1365 return ERROR_COMMAND_SYNTAX_ERROR;
1366 CMD_ARGC--;
1367 CMD_ARGV++;
1368 }
1369
1370 if (stm32x_erase_options(bank) != ERROR_OK) {
1371 command_print(CMD, "stm32x failed to erase options");
1372 return ERROR_OK;
1373 }
1374
1375 stm32x_info->option_bytes.user = optionbyte;
1376 stm32x_info->option_bytes.data = useropt;
1377
1378 if (stm32x_write_options(bank) != ERROR_OK) {
1379 command_print(CMD, "stm32x failed to write options");
1380 return ERROR_OK;
1381 }
1382
1383 command_print(CMD, "stm32x write options complete.\n"
1384 "INFO: %spower cycle is required "
1385 "for the new settings to take effect.",
1386 stm32x_info->can_load_options
1387 ? "'stm32f1x options_load' command or " : "");
1388
1389 return ERROR_OK;
1390 }
1391
1392 COMMAND_HANDLER(stm32x_handle_options_load_command)
1393 {
1394 if (CMD_ARGC < 1)
1395 return ERROR_COMMAND_SYNTAX_ERROR;
1396
1397 struct flash_bank *bank;
1398 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1399 if (ERROR_OK != retval)
1400 return retval;
1401
1402 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1403
1404 if (!stm32x_info->can_load_options) {
1405 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1406 "required instead.");
1407 return ERROR_FAIL;
1408 }
1409
1410 struct target *target = bank->target;
1411
1412 if (target->state != TARGET_HALTED) {
1413 LOG_ERROR("Target not halted");
1414 return ERROR_TARGET_NOT_HALTED;
1415 }
1416
1417 retval = stm32x_check_operation_supported(bank);
1418 if (ERROR_OK != retval)
1419 return retval;
1420
1421 /* unlock option flash registers */
1422 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1423 if (retval != ERROR_OK)
1424 return retval;
1425 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1426 if (retval != ERROR_OK)
1427 return retval;
1428
1429 /* force re-load of option bytes - generates software reset */
1430 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1431 if (retval != ERROR_OK)
1432 return retval;
1433
1434 return ERROR_OK;
1435 }
1436
1437 static int stm32x_mass_erase(struct flash_bank *bank)
1438 {
1439 struct target *target = bank->target;
1440
1441 if (target->state != TARGET_HALTED) {
1442 LOG_ERROR("Target not halted");
1443 return ERROR_TARGET_NOT_HALTED;
1444 }
1445
1446 /* unlock option flash registers */
1447 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1448 if (retval != ERROR_OK)
1449 return retval;
1450 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1451 if (retval != ERROR_OK)
1452 return retval;
1453
1454 /* mass erase flash memory */
1455 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1456 if (retval != ERROR_OK)
1457 return retval;
1458 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1459 FLASH_MER | FLASH_STRT);
1460 if (retval != ERROR_OK)
1461 return retval;
1462
1463 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1464 if (retval != ERROR_OK)
1465 return retval;
1466
1467 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1468 if (retval != ERROR_OK)
1469 return retval;
1470
1471 return ERROR_OK;
1472 }
1473
1474 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1475 {
1476 if (CMD_ARGC < 1)
1477 return ERROR_COMMAND_SYNTAX_ERROR;
1478
1479 struct flash_bank *bank;
1480 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1481 if (ERROR_OK != retval)
1482 return retval;
1483
1484 retval = stm32x_mass_erase(bank);
1485 if (retval == ERROR_OK) {
1486 /* set all sectors as erased */
1487 for (int i = 0; i < bank->num_sectors; i++)
1488 bank->sectors[i].is_erased = 1;
1489
1490 command_print(CMD, "stm32x mass erase complete");
1491 } else
1492 command_print(CMD, "stm32x mass erase failed");
1493
1494 return retval;
1495 }
1496
1497 static const struct command_registration stm32x_exec_command_handlers[] = {
1498 {
1499 .name = "lock",
1500 .handler = stm32x_handle_lock_command,
1501 .mode = COMMAND_EXEC,
1502 .usage = "bank_id",
1503 .help = "Lock entire flash device.",
1504 },
1505 {
1506 .name = "unlock",
1507 .handler = stm32x_handle_unlock_command,
1508 .mode = COMMAND_EXEC,
1509 .usage = "bank_id",
1510 .help = "Unlock entire protected flash device.",
1511 },
1512 {
1513 .name = "mass_erase",
1514 .handler = stm32x_handle_mass_erase_command,
1515 .mode = COMMAND_EXEC,
1516 .usage = "bank_id",
1517 .help = "Erase entire flash device.",
1518 },
1519 {
1520 .name = "options_read",
1521 .handler = stm32x_handle_options_read_command,
1522 .mode = COMMAND_EXEC,
1523 .usage = "bank_id",
1524 .help = "Read and display device option bytes.",
1525 },
1526 {
1527 .name = "options_write",
1528 .handler = stm32x_handle_options_write_command,
1529 .mode = COMMAND_EXEC,
1530 .usage = "bank_id ('SWWDG'|'HWWDG') "
1531 "('RSTSTNDBY'|'NORSTSTNDBY') "
1532 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1533 .help = "Replace bits in device option bytes.",
1534 },
1535 {
1536 .name = "options_load",
1537 .handler = stm32x_handle_options_load_command,
1538 .mode = COMMAND_EXEC,
1539 .usage = "bank_id",
1540 .help = "Force re-load of device option bytes.",
1541 },
1542 COMMAND_REGISTRATION_DONE
1543 };
1544
1545 static const struct command_registration stm32x_command_handlers[] = {
1546 {
1547 .name = "stm32f1x",
1548 .mode = COMMAND_ANY,
1549 .help = "stm32f1x flash command group",
1550 .usage = "",
1551 .chain = stm32x_exec_command_handlers,
1552 },
1553 COMMAND_REGISTRATION_DONE
1554 };
1555
1556 const struct flash_driver stm32f1x_flash = {
1557 .name = "stm32f1x",
1558 .commands = stm32x_command_handlers,
1559 .flash_bank_command = stm32x_flash_bank_command,
1560 .erase = stm32x_erase,
1561 .protect = stm32x_protect,
1562 .write = stm32x_write,
1563 .read = default_flash_read,
1564 .probe = stm32x_probe,
1565 .auto_probe = stm32x_auto_probe,
1566 .erase_check = default_flash_blank_check,
1567 .protect_check = stm32x_protect_check,
1568 .info = get_stm32x_info,
1569 .free_driver_priv = default_flash_free_driver_priv,
1570 };
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