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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 /* timeout values */
105
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
108
109 struct stm32x_options {
110 uint8_t rdp;
111 uint8_t user;
112 uint16_t data;
113 uint32_t protection;
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 int probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
125 uint8_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = 0;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
153
154 return ERROR_OK;
155 }
156
157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
158 {
159 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
160 return reg + stm32x_info->register_base;
161 }
162
163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
164 {
165 struct target *target = bank->target;
166 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
167 }
168
169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
170 {
171 struct target *target = bank->target;
172 uint32_t status;
173 int retval = ERROR_OK;
174
175 /* wait for busy to clear */
176 for (;;) {
177 retval = stm32x_get_flash_status(bank, &status);
178 if (retval != ERROR_OK)
179 return retval;
180 LOG_DEBUG("status: 0x%" PRIx32 "", status);
181 if ((status & FLASH_BSY) == 0)
182 break;
183 if (timeout-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
185 return ERROR_FAIL;
186 }
187 alive_sleep(1);
188 }
189
190 if (status & FLASH_WRPRTERR) {
191 LOG_ERROR("stm32x device protected");
192 retval = ERROR_FAIL;
193 }
194
195 if (status & FLASH_PGERR) {
196 LOG_ERROR("stm32x device programming failed");
197 retval = ERROR_FAIL;
198 }
199
200 /* Clear but report errors */
201 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
202 /* If this operation fails, we ignore it and report the original
203 * retval
204 */
205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
206 FLASH_WRPRTERR | FLASH_PGERR);
207 }
208 return retval;
209 }
210
211 static int stm32x_check_operation_supported(struct flash_bank *bank)
212 {
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
214
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
218 LOG_ERROR("Option Byte Operation's must use bank0");
219 return ERROR_FLASH_OPERATION_FAILED;
220 }
221
222 return ERROR_OK;
223 }
224
225 static int stm32x_read_options(struct flash_bank *bank)
226 {
227 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
228 struct target *target = bank->target;
229 uint32_t option_bytes;
230 int retval;
231
232 /* read user and read protection option bytes, user data option bytes */
233 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
238 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
239 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
240
241 /* read write protection option bytes */
242 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
243 if (retval != ERROR_OK)
244 return retval;
245
246 return ERROR_OK;
247 }
248
249 static int stm32x_erase_options(struct flash_bank *bank)
250 {
251 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
252 struct target *target = bank->target;
253
254 /* read current options */
255 stm32x_read_options(bank);
256
257 /* unlock flash registers */
258 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
259 if (retval != ERROR_OK)
260 return retval;
261
262 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
263 if (retval != ERROR_OK)
264 return retval;
265
266 /* unlock option flash registers */
267 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
268 if (retval != ERROR_OK)
269 return retval;
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* erase option bytes */
275 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
276 if (retval != ERROR_OK)
277 return retval;
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
280 return retval;
281
282 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
283 if (retval != ERROR_OK)
284 return retval;
285
286 /* clear read protection option byte
287 * this will also force a device unlock if set */
288 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
289
290 return ERROR_OK;
291 }
292
293 static int stm32x_write_options(struct flash_bank *bank)
294 {
295 struct stm32x_flash_bank *stm32x_info = NULL;
296 struct target *target = bank->target;
297
298 stm32x_info = bank->driver_priv;
299
300 /* unlock flash registers */
301 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
302 if (retval != ERROR_OK)
303 return retval;
304 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
305 if (retval != ERROR_OK)
306 return retval;
307
308 /* unlock option flash registers */
309 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
310 if (retval != ERROR_OK)
311 return retval;
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
313 if (retval != ERROR_OK)
314 return retval;
315
316 /* program option bytes */
317 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
318 if (retval != ERROR_OK)
319 return retval;
320
321 uint8_t opt_bytes[16];
322
323 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
324 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
325 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
326 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
327 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
328 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
329 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
330 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
331
332 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
333 if (retval != ERROR_OK) {
334 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
335 LOG_ERROR("working area required to erase options bytes");
336 return retval;
337 }
338
339 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
340 if (retval != ERROR_OK)
341 return retval;
342
343 return ERROR_OK;
344 }
345
346 static int stm32x_protect_check(struct flash_bank *bank)
347 {
348 struct target *target = bank->target;
349 uint32_t protection;
350
351 int retval = stm32x_check_operation_supported(bank);
352 if (ERROR_OK != retval)
353 return retval;
354
355 /* medium density - each bit refers to a 4 sector protection block
356 * high density - each bit refers to a 2 sector protection block
357 * bit 31 refers to all remaining sectors in a bank */
358 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
359 if (retval != ERROR_OK)
360 return retval;
361
362 for (int i = 0; i < bank->num_prot_blocks; i++)
363 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
364
365 return ERROR_OK;
366 }
367
368 static int stm32x_erase(struct flash_bank *bank, int first, int last)
369 {
370 struct target *target = bank->target;
371 int i;
372
373 if (bank->target->state != TARGET_HALTED) {
374 LOG_ERROR("Target not halted");
375 return ERROR_TARGET_NOT_HALTED;
376 }
377
378 if ((first == 0) && (last == (bank->num_sectors - 1)))
379 return stm32x_mass_erase(bank);
380
381 /* unlock flash registers */
382 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
383 if (retval != ERROR_OK)
384 return retval;
385 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
386 if (retval != ERROR_OK)
387 return retval;
388
389 for (i = first; i <= last; i++) {
390 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
391 if (retval != ERROR_OK)
392 return retval;
393 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
394 bank->base + bank->sectors[i].offset);
395 if (retval != ERROR_OK)
396 return retval;
397 retval = target_write_u32(target,
398 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
399 if (retval != ERROR_OK)
400 return retval;
401
402 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
403 if (retval != ERROR_OK)
404 return retval;
405
406 bank->sectors[i].is_erased = 1;
407 }
408
409 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
410 if (retval != ERROR_OK)
411 return retval;
412
413 return ERROR_OK;
414 }
415
416 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
417 {
418 struct target *target = bank->target;
419 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
420
421 if (target->state != TARGET_HALTED) {
422 LOG_ERROR("Target not halted");
423 return ERROR_TARGET_NOT_HALTED;
424 }
425
426 int retval = stm32x_check_operation_supported(bank);
427 if (retval != ERROR_OK)
428 return retval;
429
430 retval = stm32x_erase_options(bank);
431 if (retval != ERROR_OK) {
432 LOG_ERROR("stm32x failed to erase options");
433 return retval;
434 }
435
436 for (int i = first; i <= last; i++) {
437 if (set)
438 stm32x_info->option_bytes.protection &= ~(1 << i);
439 else
440 stm32x_info->option_bytes.protection |= (1 << i);
441 }
442
443 return stm32x_write_options(bank);
444 }
445
446 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
447 uint32_t address, uint32_t count)
448 {
449 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
450 struct target *target = bank->target;
451 uint32_t buffer_size = 16384;
452 struct working_area *write_algorithm;
453 struct working_area *source;
454 struct reg_param reg_params[5];
455 struct armv7m_algorithm armv7m_info;
456 int retval = ERROR_OK;
457
458 static const uint8_t stm32x_flash_write_code[] = {
459 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
460 };
461
462 /* flash write code */
463 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
464 &write_algorithm) != ERROR_OK) {
465 LOG_WARNING("no working area available, can't do block memory writes");
466 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
467 }
468
469 retval = target_write_buffer(target, write_algorithm->address,
470 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
471 if (retval != ERROR_OK) {
472 target_free_working_area(target, write_algorithm);
473 return retval;
474 }
475
476 /* memory buffer */
477 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
478 buffer_size /= 2;
479 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
480 if (buffer_size <= 256) {
481 /* we already allocated the writing code, but failed to get a
482 * buffer, free the algorithm */
483 target_free_working_area(target, write_algorithm);
484
485 LOG_WARNING("no large enough working area available, can't do block memory writes");
486 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
487 }
488 }
489
490 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
491 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
492 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
493 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
494 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
495
496 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
497 buf_set_u32(reg_params[1].value, 0, 32, count);
498 buf_set_u32(reg_params[2].value, 0, 32, source->address);
499 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
500 buf_set_u32(reg_params[4].value, 0, 32, address);
501
502 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
503 armv7m_info.core_mode = ARM_MODE_THREAD;
504
505 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
506 0, NULL,
507 5, reg_params,
508 source->address, source->size,
509 write_algorithm->address, 0,
510 &armv7m_info);
511
512 if (retval == ERROR_FLASH_OPERATION_FAILED) {
513 LOG_ERROR("flash write failed at address 0x%"PRIx32,
514 buf_get_u32(reg_params[4].value, 0, 32));
515
516 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
517 LOG_ERROR("flash memory not erased before writing");
518 /* Clear but report errors */
519 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
520 }
521
522 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
523 LOG_ERROR("flash memory write protected");
524 /* Clear but report errors */
525 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
526 }
527 }
528
529 target_free_working_area(target, source);
530 target_free_working_area(target, write_algorithm);
531
532 destroy_reg_param(&reg_params[0]);
533 destroy_reg_param(&reg_params[1]);
534 destroy_reg_param(&reg_params[2]);
535 destroy_reg_param(&reg_params[3]);
536 destroy_reg_param(&reg_params[4]);
537
538 return retval;
539 }
540
541 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
542 uint32_t offset, uint32_t count)
543 {
544 struct target *target = bank->target;
545 uint8_t *new_buffer = NULL;
546
547 if (bank->target->state != TARGET_HALTED) {
548 LOG_ERROR("Target not halted");
549 return ERROR_TARGET_NOT_HALTED;
550 }
551
552 if (offset & 0x1) {
553 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
554 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
555 }
556
557 /* If there's an odd number of bytes, the data has to be padded. Duplicate
558 * the buffer and use the normal code path with a single block write since
559 * it's probably cheaper than to special case the last odd write using
560 * discrete accesses. */
561 if (count & 1) {
562 new_buffer = malloc(count + 1);
563 if (new_buffer == NULL) {
564 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
565 return ERROR_FAIL;
566 }
567 LOG_INFO("odd number of bytes to write, padding with 0xff");
568 buffer = memcpy(new_buffer, buffer, count);
569 new_buffer[count++] = 0xff;
570 }
571
572 uint32_t words_remaining = count / 2;
573 int retval, retval2;
574
575 /* unlock flash registers */
576 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
577 if (retval != ERROR_OK)
578 goto cleanup;
579 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
580 if (retval != ERROR_OK)
581 goto cleanup;
582
583 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
584 if (retval != ERROR_OK)
585 goto cleanup;
586
587 /* try using a block write */
588 retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
589
590 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
591 /* if block write failed (no sufficient working area),
592 * we use normal (slow) single halfword accesses */
593 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
594
595 while (words_remaining > 0) {
596 uint16_t value;
597 memcpy(&value, buffer, sizeof(uint16_t));
598
599 retval = target_write_u16(target, bank->base + offset, value);
600 if (retval != ERROR_OK)
601 goto reset_pg_and_lock;
602
603 retval = stm32x_wait_status_busy(bank, 5);
604 if (retval != ERROR_OK)
605 goto reset_pg_and_lock;
606
607 words_remaining--;
608 buffer += 2;
609 offset += 2;
610 }
611 }
612
613 reset_pg_and_lock:
614 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
615 if (retval == ERROR_OK)
616 retval = retval2;
617
618 cleanup:
619 if (new_buffer)
620 free(new_buffer);
621
622 return retval;
623 }
624
625 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
626 {
627 /* This check the device CPUID core register to detect
628 * the M0 from the M3 devices. */
629
630 struct target *target = bank->target;
631 uint32_t cpuid, device_id_register = 0;
632
633 /* Get the CPUID from the ARM Core
634 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
635 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
636 if (retval != ERROR_OK)
637 return retval;
638
639 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
640 /* 0xC20 is M0 devices */
641 device_id_register = 0x40015800;
642 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
643 /* 0xC23 is M3 devices */
644 device_id_register = 0xE0042000;
645 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
646 /* 0xC24 is M4 devices */
647 device_id_register = 0xE0042000;
648 } else {
649 LOG_ERROR("Cannot identify target as a stm32x");
650 return ERROR_FAIL;
651 }
652
653 /* read stm32 device id register */
654 retval = target_read_u32(target, device_id_register, device_id);
655 if (retval != ERROR_OK)
656 return retval;
657
658 return retval;
659 }
660
661 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
662 {
663 struct target *target = bank->target;
664 uint32_t cpuid, flash_size_reg;
665
666 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
667 if (retval != ERROR_OK)
668 return retval;
669
670 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
671 /* 0xC20 is M0 devices */
672 flash_size_reg = 0x1FFFF7CC;
673 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
674 /* 0xC23 is M3 devices */
675 flash_size_reg = 0x1FFFF7E0;
676 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
677 /* 0xC24 is M4 devices */
678 flash_size_reg = 0x1FFFF7CC;
679 } else {
680 LOG_ERROR("Cannot identify target as a stm32x");
681 return ERROR_FAIL;
682 }
683
684 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
685 if (retval != ERROR_OK)
686 return retval;
687
688 return retval;
689 }
690
691 static int stm32x_probe(struct flash_bank *bank)
692 {
693 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
694 uint16_t flash_size_in_kb;
695 uint16_t max_flash_size_in_kb;
696 uint32_t device_id;
697 int page_size;
698 uint32_t base_address = 0x08000000;
699
700 stm32x_info->probed = 0;
701 stm32x_info->register_base = FLASH_REG_BASE_B0;
702 stm32x_info->user_data_offset = 10;
703 stm32x_info->option_offset = 0;
704
705 /* default factory read protection level 0 */
706 stm32x_info->default_rdp = 0xA5;
707
708 /* read stm32 device id register */
709 int retval = stm32x_get_device_id(bank, &device_id);
710 if (retval != ERROR_OK)
711 return retval;
712
713 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
714
715 /* set page size, protection granularity and max flash size depending on family */
716 switch (device_id & 0xfff) {
717 case 0x410: /* medium density */
718 page_size = 1024;
719 stm32x_info->ppage_size = 4;
720 max_flash_size_in_kb = 128;
721 break;
722 case 0x412: /* low density */
723 page_size = 1024;
724 stm32x_info->ppage_size = 4;
725 max_flash_size_in_kb = 32;
726 break;
727 case 0x414: /* high density */
728 page_size = 2048;
729 stm32x_info->ppage_size = 2;
730 max_flash_size_in_kb = 512;
731 break;
732 case 0x418: /* connectivity line density */
733 page_size = 2048;
734 stm32x_info->ppage_size = 2;
735 max_flash_size_in_kb = 256;
736 break;
737 case 0x420: /* value line density */
738 page_size = 1024;
739 stm32x_info->ppage_size = 4;
740 max_flash_size_in_kb = 128;
741 break;
742 case 0x422: /* stm32f302/3xb/c */
743 page_size = 2048;
744 stm32x_info->ppage_size = 2;
745 max_flash_size_in_kb = 256;
746 stm32x_info->user_data_offset = 16;
747 stm32x_info->option_offset = 6;
748 stm32x_info->default_rdp = 0xAA;
749 stm32x_info->can_load_options = true;
750 break;
751 case 0x446: /* stm32f303xD/E */
752 page_size = 2048;
753 stm32x_info->ppage_size = 2;
754 max_flash_size_in_kb = 512;
755 stm32x_info->user_data_offset = 16;
756 stm32x_info->option_offset = 6;
757 stm32x_info->default_rdp = 0xAA;
758 stm32x_info->can_load_options = true;
759 break;
760 case 0x428: /* value line High density */
761 page_size = 2048;
762 stm32x_info->ppage_size = 4;
763 max_flash_size_in_kb = 128;
764 break;
765 case 0x430: /* xl line density (dual flash banks) */
766 page_size = 2048;
767 stm32x_info->ppage_size = 2;
768 max_flash_size_in_kb = 1024;
769 stm32x_info->has_dual_banks = true;
770 break;
771 case 0x432: /* stm32f37x */
772 page_size = 2048;
773 stm32x_info->ppage_size = 2;
774 max_flash_size_in_kb = 256;
775 stm32x_info->user_data_offset = 16;
776 stm32x_info->option_offset = 6;
777 stm32x_info->default_rdp = 0xAA;
778 stm32x_info->can_load_options = true;
779 break;
780 case 0x438: /* stm32f33x */
781 case 0x439: /* stm32f302x6/8 */
782 page_size = 2048;
783 stm32x_info->ppage_size = 2;
784 max_flash_size_in_kb = 64;
785 stm32x_info->user_data_offset = 16;
786 stm32x_info->option_offset = 6;
787 stm32x_info->default_rdp = 0xAA;
788 stm32x_info->can_load_options = true;
789 break;
790 case 0x440: /* stm32f05x */
791 case 0x444: /* stm32f03x */
792 case 0x445: /* stm32f04x */
793 page_size = 1024;
794 stm32x_info->ppage_size = 4;
795 max_flash_size_in_kb = 64;
796 stm32x_info->user_data_offset = 16;
797 stm32x_info->option_offset = 6;
798 stm32x_info->default_rdp = 0xAA;
799 stm32x_info->can_load_options = true;
800 break;
801 case 0x448: /* stm32f07x */
802 case 0x442: /* stm32f09x */
803 page_size = 2048;
804 stm32x_info->ppage_size = 4;
805 max_flash_size_in_kb = 256;
806 stm32x_info->user_data_offset = 16;
807 stm32x_info->option_offset = 6;
808 stm32x_info->default_rdp = 0xAA;
809 stm32x_info->can_load_options = true;
810 break;
811 default:
812 LOG_WARNING("Cannot identify target as a STM32 family.");
813 return ERROR_FAIL;
814 }
815
816 /* get flash size from target. */
817 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
818
819 /* failed reading flash size or flash size invalid (early silicon),
820 * default to max target family */
821 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
822 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
823 max_flash_size_in_kb);
824 flash_size_in_kb = max_flash_size_in_kb;
825 }
826
827 if (stm32x_info->has_dual_banks) {
828 /* split reported size into matching bank */
829 if (bank->base != 0x08080000) {
830 /* bank 0 will be fixed 512k */
831 flash_size_in_kb = 512;
832 } else {
833 flash_size_in_kb -= 512;
834 /* bank1 also uses a register offset */
835 stm32x_info->register_base = FLASH_REG_BASE_B1;
836 base_address = 0x08080000;
837 }
838 }
839
840 /* if the user sets the size manually then ignore the probed value
841 * this allows us to work around devices that have a invalid flash size register value */
842 if (stm32x_info->user_bank_size) {
843 LOG_INFO("ignoring flash probed value, using configured bank size");
844 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
845 }
846
847 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
848
849 /* did we assign flash size? */
850 assert(flash_size_in_kb != 0xffff);
851
852 /* calculate numbers of pages */
853 int num_pages = flash_size_in_kb * 1024 / page_size;
854
855 /* check that calculation result makes sense */
856 assert(num_pages > 0);
857
858 if (bank->sectors) {
859 free(bank->sectors);
860 bank->sectors = NULL;
861 }
862
863 if (bank->prot_blocks) {
864 free(bank->prot_blocks);
865 bank->prot_blocks = NULL;
866 }
867
868 bank->base = base_address;
869 bank->size = (num_pages * page_size);
870
871 bank->num_sectors = num_pages;
872 bank->sectors = alloc_block_array(0, page_size, num_pages);
873 if (!bank->sectors)
874 return ERROR_FAIL;
875
876 /* calculate number of write protection blocks */
877 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
878 if (num_prot_blocks > 32)
879 num_prot_blocks = 32;
880
881 bank->num_prot_blocks = num_prot_blocks;
882 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
883 if (!bank->prot_blocks)
884 return ERROR_FAIL;
885
886 if (num_prot_blocks == 32)
887 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
888
889 stm32x_info->probed = 1;
890
891 return ERROR_OK;
892 }
893
894 static int stm32x_auto_probe(struct flash_bank *bank)
895 {
896 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
897 if (stm32x_info->probed)
898 return ERROR_OK;
899 return stm32x_probe(bank);
900 }
901
902 #if 0
903 COMMAND_HANDLER(stm32x_handle_part_id_command)
904 {
905 return ERROR_OK;
906 }
907 #endif
908
909 static const char *get_stm32f0_revision(uint16_t rev_id)
910 {
911 const char *rev_str = NULL;
912
913 switch (rev_id) {
914 case 0x1000:
915 rev_str = "1.0";
916 break;
917 case 0x2000:
918 rev_str = "2.0";
919 break;
920 }
921 return rev_str;
922 }
923
924 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
925 {
926 uint32_t dbgmcu_idcode;
927
928 /* read stm32 device id register */
929 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
930 if (retval != ERROR_OK)
931 return retval;
932
933 uint16_t device_id = dbgmcu_idcode & 0xfff;
934 uint16_t rev_id = dbgmcu_idcode >> 16;
935 const char *device_str;
936 const char *rev_str = NULL;
937
938 switch (device_id) {
939 case 0x410:
940 device_str = "STM32F10x (Medium Density)";
941
942 switch (rev_id) {
943 case 0x0000:
944 rev_str = "A";
945 break;
946
947 case 0x2000:
948 rev_str = "B";
949 break;
950
951 case 0x2001:
952 rev_str = "Z";
953 break;
954
955 case 0x2003:
956 rev_str = "Y";
957 break;
958 }
959 break;
960
961 case 0x412:
962 device_str = "STM32F10x (Low Density)";
963
964 switch (rev_id) {
965 case 0x1000:
966 rev_str = "A";
967 break;
968 }
969 break;
970
971 case 0x414:
972 device_str = "STM32F10x (High Density)";
973
974 switch (rev_id) {
975 case 0x1000:
976 rev_str = "A";
977 break;
978
979 case 0x1001:
980 rev_str = "Z";
981 break;
982
983 case 0x1003:
984 rev_str = "Y";
985 break;
986 }
987 break;
988
989 case 0x418:
990 device_str = "STM32F10x (Connectivity)";
991
992 switch (rev_id) {
993 case 0x1000:
994 rev_str = "A";
995 break;
996
997 case 0x1001:
998 rev_str = "Z";
999 break;
1000 }
1001 break;
1002
1003 case 0x420:
1004 device_str = "STM32F100 (Low/Medium Density)";
1005
1006 switch (rev_id) {
1007 case 0x1000:
1008 rev_str = "A";
1009 break;
1010
1011 case 0x1001:
1012 rev_str = "Z";
1013 break;
1014 }
1015 break;
1016
1017 case 0x422:
1018 device_str = "STM32F302xB/C";
1019
1020 switch (rev_id) {
1021 case 0x1000:
1022 rev_str = "A";
1023 break;
1024
1025 case 0x1001:
1026 rev_str = "Z";
1027 break;
1028
1029 case 0x1003:
1030 rev_str = "Y";
1031 break;
1032
1033 case 0x2000:
1034 rev_str = "B";
1035 break;
1036 }
1037 break;
1038
1039 case 0x428:
1040 device_str = "STM32F100 (High Density)";
1041
1042 switch (rev_id) {
1043 case 0x1000:
1044 rev_str = "A";
1045 break;
1046
1047 case 0x1001:
1048 rev_str = "Z";
1049 break;
1050 }
1051 break;
1052
1053 case 0x430:
1054 device_str = "STM32F10x (XL Density)";
1055
1056 switch (rev_id) {
1057 case 0x1000:
1058 rev_str = "A";
1059 break;
1060 }
1061 break;
1062
1063 case 0x432:
1064 device_str = "STM32F37x";
1065
1066 switch (rev_id) {
1067 case 0x1000:
1068 rev_str = "A";
1069 break;
1070
1071 case 0x2000:
1072 rev_str = "B";
1073 break;
1074 }
1075 break;
1076
1077 case 0x438:
1078 device_str = "STM32F33x";
1079
1080 switch (rev_id) {
1081 case 0x1000:
1082 rev_str = "A";
1083 break;
1084 }
1085 break;
1086
1087 case 0x439:
1088 device_str = "STM32F302x6/8";
1089
1090 switch (rev_id) {
1091 case 0x1000:
1092 rev_str = "A";
1093 break;
1094
1095 case 0x1001:
1096 rev_str = "Z";
1097 break;
1098 }
1099 break;
1100
1101 case 0x444:
1102 device_str = "STM32F03x";
1103 rev_str = get_stm32f0_revision(rev_id);
1104 break;
1105
1106 case 0x440:
1107 device_str = "STM32F05x";
1108 rev_str = get_stm32f0_revision(rev_id);
1109 break;
1110
1111 case 0x445:
1112 device_str = "STM32F04x";
1113 rev_str = get_stm32f0_revision(rev_id);
1114 break;
1115
1116 case 0x446:
1117 device_str = "STM32F303xD/E";
1118 switch (rev_id) {
1119 case 0x1000:
1120 rev_str = "A";
1121 break;
1122 }
1123 break;
1124
1125 case 0x448:
1126 device_str = "STM32F07x";
1127 rev_str = get_stm32f0_revision(rev_id);
1128 break;
1129
1130 case 0x442:
1131 device_str = "STM32F09x";
1132 rev_str = get_stm32f0_revision(rev_id);
1133 break;
1134
1135 default:
1136 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1137 return ERROR_FAIL;
1138 }
1139
1140 if (rev_str != NULL)
1141 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1142 else
1143 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1144
1145 return ERROR_OK;
1146 }
1147
1148 COMMAND_HANDLER(stm32x_handle_lock_command)
1149 {
1150 struct target *target = NULL;
1151 struct stm32x_flash_bank *stm32x_info = NULL;
1152
1153 if (CMD_ARGC < 1)
1154 return ERROR_COMMAND_SYNTAX_ERROR;
1155
1156 struct flash_bank *bank;
1157 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1158 if (ERROR_OK != retval)
1159 return retval;
1160
1161 stm32x_info = bank->driver_priv;
1162
1163 target = bank->target;
1164
1165 if (target->state != TARGET_HALTED) {
1166 LOG_ERROR("Target not halted");
1167 return ERROR_TARGET_NOT_HALTED;
1168 }
1169
1170 retval = stm32x_check_operation_supported(bank);
1171 if (ERROR_OK != retval)
1172 return retval;
1173
1174 if (stm32x_erase_options(bank) != ERROR_OK) {
1175 command_print(CMD, "stm32x failed to erase options");
1176 return ERROR_OK;
1177 }
1178
1179 /* set readout protection */
1180 stm32x_info->option_bytes.rdp = 0;
1181
1182 if (stm32x_write_options(bank) != ERROR_OK) {
1183 command_print(CMD, "stm32x failed to lock device");
1184 return ERROR_OK;
1185 }
1186
1187 command_print(CMD, "stm32x locked");
1188
1189 return ERROR_OK;
1190 }
1191
1192 COMMAND_HANDLER(stm32x_handle_unlock_command)
1193 {
1194 struct target *target = NULL;
1195
1196 if (CMD_ARGC < 1)
1197 return ERROR_COMMAND_SYNTAX_ERROR;
1198
1199 struct flash_bank *bank;
1200 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1201 if (ERROR_OK != retval)
1202 return retval;
1203
1204 target = bank->target;
1205
1206 if (target->state != TARGET_HALTED) {
1207 LOG_ERROR("Target not halted");
1208 return ERROR_TARGET_NOT_HALTED;
1209 }
1210
1211 retval = stm32x_check_operation_supported(bank);
1212 if (ERROR_OK != retval)
1213 return retval;
1214
1215 if (stm32x_erase_options(bank) != ERROR_OK) {
1216 command_print(CMD, "stm32x failed to erase options");
1217 return ERROR_OK;
1218 }
1219
1220 if (stm32x_write_options(bank) != ERROR_OK) {
1221 command_print(CMD, "stm32x failed to unlock device");
1222 return ERROR_OK;
1223 }
1224
1225 command_print(CMD, "stm32x unlocked.\n"
1226 "INFO: a reset or power cycle is required "
1227 "for the new settings to take effect.");
1228
1229 return ERROR_OK;
1230 }
1231
1232 COMMAND_HANDLER(stm32x_handle_options_read_command)
1233 {
1234 uint32_t optionbyte, protection;
1235 struct target *target = NULL;
1236 struct stm32x_flash_bank *stm32x_info = NULL;
1237
1238 if (CMD_ARGC < 1)
1239 return ERROR_COMMAND_SYNTAX_ERROR;
1240
1241 struct flash_bank *bank;
1242 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1243 if (ERROR_OK != retval)
1244 return retval;
1245
1246 stm32x_info = bank->driver_priv;
1247
1248 target = bank->target;
1249
1250 if (target->state != TARGET_HALTED) {
1251 LOG_ERROR("Target not halted");
1252 return ERROR_TARGET_NOT_HALTED;
1253 }
1254
1255 retval = stm32x_check_operation_supported(bank);
1256 if (ERROR_OK != retval)
1257 return retval;
1258
1259 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1260 if (retval != ERROR_OK)
1261 return retval;
1262
1263 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1264
1265 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1266 if (retval != ERROR_OK)
1267 return retval;
1268
1269 if (optionbyte & (1 << OPT_ERROR))
1270 command_print(CMD, "option byte complement error");
1271
1272 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1273 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1274
1275 command_print(CMD, "read protection: %s",
1276 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1277
1278 /* user option bytes are offset depending on variant */
1279 optionbyte >>= stm32x_info->option_offset;
1280
1281 command_print(CMD, "watchdog: %sware",
1282 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1283
1284 command_print(CMD, "stop mode: %sreset generated upon entry",
1285 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1286
1287 command_print(CMD, "standby mode: %sreset generated upon entry",
1288 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1289
1290 if (stm32x_info->has_dual_banks)
1291 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1292
1293 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1294
1295 return ERROR_OK;
1296 }
1297
1298 COMMAND_HANDLER(stm32x_handle_options_write_command)
1299 {
1300 struct target *target = NULL;
1301 struct stm32x_flash_bank *stm32x_info = NULL;
1302 uint8_t optionbyte;
1303 uint16_t useropt;
1304
1305 if (CMD_ARGC < 2)
1306 return ERROR_COMMAND_SYNTAX_ERROR;
1307
1308 struct flash_bank *bank;
1309 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1310 if (ERROR_OK != retval)
1311 return retval;
1312
1313 stm32x_info = bank->driver_priv;
1314
1315 target = bank->target;
1316
1317 if (target->state != TARGET_HALTED) {
1318 LOG_ERROR("Target not halted");
1319 return ERROR_TARGET_NOT_HALTED;
1320 }
1321
1322 retval = stm32x_check_operation_supported(bank);
1323 if (ERROR_OK != retval)
1324 return retval;
1325
1326 retval = stm32x_read_options(bank);
1327 if (ERROR_OK != retval)
1328 return retval;
1329
1330 /* start with current options */
1331 optionbyte = stm32x_info->option_bytes.user;
1332 useropt = stm32x_info->option_bytes.data;
1333
1334 /* skip over flash bank */
1335 CMD_ARGC--;
1336 CMD_ARGV++;
1337
1338 while (CMD_ARGC) {
1339 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1340 optionbyte |= (1 << 0);
1341 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1342 optionbyte &= ~(1 << 0);
1343 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1344 optionbyte |= (1 << 1);
1345 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1346 optionbyte &= ~(1 << 1);
1347 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1348 optionbyte |= (1 << 2);
1349 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1350 optionbyte &= ~(1 << 2);
1351 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1352 if (CMD_ARGC < 2)
1353 return ERROR_COMMAND_SYNTAX_ERROR;
1354 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1355 CMD_ARGC--;
1356 CMD_ARGV++;
1357 }
1358 else if (stm32x_info->has_dual_banks) {
1359 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1360 optionbyte |= (1 << 3);
1361 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1362 optionbyte &= ~(1 << 3);
1363 else
1364 return ERROR_COMMAND_SYNTAX_ERROR;
1365 } else
1366 return ERROR_COMMAND_SYNTAX_ERROR;
1367 CMD_ARGC--;
1368 CMD_ARGV++;
1369 }
1370
1371 if (stm32x_erase_options(bank) != ERROR_OK) {
1372 command_print(CMD, "stm32x failed to erase options");
1373 return ERROR_OK;
1374 }
1375
1376 stm32x_info->option_bytes.user = optionbyte;
1377 stm32x_info->option_bytes.data = useropt;
1378
1379 if (stm32x_write_options(bank) != ERROR_OK) {
1380 command_print(CMD, "stm32x failed to write options");
1381 return ERROR_OK;
1382 }
1383
1384 command_print(CMD, "stm32x write options complete.\n"
1385 "INFO: %spower cycle is required "
1386 "for the new settings to take effect.",
1387 stm32x_info->can_load_options
1388 ? "'stm32f1x options_load' command or " : "");
1389
1390 return ERROR_OK;
1391 }
1392
1393 COMMAND_HANDLER(stm32x_handle_options_load_command)
1394 {
1395 if (CMD_ARGC < 1)
1396 return ERROR_COMMAND_SYNTAX_ERROR;
1397
1398 struct flash_bank *bank;
1399 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1400 if (ERROR_OK != retval)
1401 return retval;
1402
1403 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1404
1405 if (!stm32x_info->can_load_options) {
1406 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1407 "required instead.");
1408 return ERROR_FAIL;
1409 }
1410
1411 struct target *target = bank->target;
1412
1413 if (target->state != TARGET_HALTED) {
1414 LOG_ERROR("Target not halted");
1415 return ERROR_TARGET_NOT_HALTED;
1416 }
1417
1418 retval = stm32x_check_operation_supported(bank);
1419 if (ERROR_OK != retval)
1420 return retval;
1421
1422 /* unlock option flash registers */
1423 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1424 if (retval != ERROR_OK)
1425 return retval;
1426 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1427 if (retval != ERROR_OK)
1428 return retval;
1429
1430 /* force re-load of option bytes - generates software reset */
1431 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1432 if (retval != ERROR_OK)
1433 return retval;
1434
1435 return ERROR_OK;
1436 }
1437
1438 static int stm32x_mass_erase(struct flash_bank *bank)
1439 {
1440 struct target *target = bank->target;
1441
1442 if (target->state != TARGET_HALTED) {
1443 LOG_ERROR("Target not halted");
1444 return ERROR_TARGET_NOT_HALTED;
1445 }
1446
1447 /* unlock option flash registers */
1448 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1449 if (retval != ERROR_OK)
1450 return retval;
1451 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1452 if (retval != ERROR_OK)
1453 return retval;
1454
1455 /* mass erase flash memory */
1456 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1457 if (retval != ERROR_OK)
1458 return retval;
1459 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1460 FLASH_MER | FLASH_STRT);
1461 if (retval != ERROR_OK)
1462 return retval;
1463
1464 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1465 if (retval != ERROR_OK)
1466 return retval;
1467
1468 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1469 if (retval != ERROR_OK)
1470 return retval;
1471
1472 return ERROR_OK;
1473 }
1474
1475 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1476 {
1477 int i;
1478
1479 if (CMD_ARGC < 1)
1480 return ERROR_COMMAND_SYNTAX_ERROR;
1481
1482 struct flash_bank *bank;
1483 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1484 if (ERROR_OK != retval)
1485 return retval;
1486
1487 retval = stm32x_mass_erase(bank);
1488 if (retval == ERROR_OK) {
1489 /* set all sectors as erased */
1490 for (i = 0; i < bank->num_sectors; i++)
1491 bank->sectors[i].is_erased = 1;
1492
1493 command_print(CMD, "stm32x mass erase complete");
1494 } else
1495 command_print(CMD, "stm32x mass erase failed");
1496
1497 return retval;
1498 }
1499
1500 static const struct command_registration stm32x_exec_command_handlers[] = {
1501 {
1502 .name = "lock",
1503 .handler = stm32x_handle_lock_command,
1504 .mode = COMMAND_EXEC,
1505 .usage = "bank_id",
1506 .help = "Lock entire flash device.",
1507 },
1508 {
1509 .name = "unlock",
1510 .handler = stm32x_handle_unlock_command,
1511 .mode = COMMAND_EXEC,
1512 .usage = "bank_id",
1513 .help = "Unlock entire protected flash device.",
1514 },
1515 {
1516 .name = "mass_erase",
1517 .handler = stm32x_handle_mass_erase_command,
1518 .mode = COMMAND_EXEC,
1519 .usage = "bank_id",
1520 .help = "Erase entire flash device.",
1521 },
1522 {
1523 .name = "options_read",
1524 .handler = stm32x_handle_options_read_command,
1525 .mode = COMMAND_EXEC,
1526 .usage = "bank_id",
1527 .help = "Read and display device option bytes.",
1528 },
1529 {
1530 .name = "options_write",
1531 .handler = stm32x_handle_options_write_command,
1532 .mode = COMMAND_EXEC,
1533 .usage = "bank_id ('SWWDG'|'HWWDG') "
1534 "('RSTSTNDBY'|'NORSTSTNDBY') "
1535 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1536 .help = "Replace bits in device option bytes.",
1537 },
1538 {
1539 .name = "options_load",
1540 .handler = stm32x_handle_options_load_command,
1541 .mode = COMMAND_EXEC,
1542 .usage = "bank_id",
1543 .help = "Force re-load of device option bytes.",
1544 },
1545 COMMAND_REGISTRATION_DONE
1546 };
1547
1548 static const struct command_registration stm32x_command_handlers[] = {
1549 {
1550 .name = "stm32f1x",
1551 .mode = COMMAND_ANY,
1552 .help = "stm32f1x flash command group",
1553 .usage = "",
1554 .chain = stm32x_exec_command_handlers,
1555 },
1556 COMMAND_REGISTRATION_DONE
1557 };
1558
1559 const struct flash_driver stm32f1x_flash = {
1560 .name = "stm32f1x",
1561 .commands = stm32x_command_handlers,
1562 .flash_bank_command = stm32x_flash_bank_command,
1563 .erase = stm32x_erase,
1564 .protect = stm32x_protect,
1565 .write = stm32x_write,
1566 .read = default_flash_read,
1567 .probe = stm32x_probe,
1568 .auto_probe = stm32x_auto_probe,
1569 .erase_check = default_flash_blank_check,
1570 .protect_check = stm32x_protect_check,
1571 .info = get_stm32x_info,
1572 .free_driver_priv = default_flash_free_driver_priv,
1573 };
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