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[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81
82 /* FLASH_SR register bits */
83
84 #define FLASH_BSY (1 << 0)
85 #define FLASH_PGERR (1 << 2)
86 #define FLASH_WRPRTERR (1 << 4)
87 #define FLASH_EOP (1 << 5)
88
89 /* STM32_FLASH_OBR bit definitions (reading) */
90
91 #define OPT_ERROR 0
92 #define OPT_READOUT 1
93 #define OPT_RDWDGSW 2
94 #define OPT_RDRSTSTOP 3
95 #define OPT_RDRSTSTDBY 4
96 #define OPT_BFB2 5 /* dual flash bank only */
97
98 /* register unlock keys */
99
100 #define KEY1 0x45670123
101 #define KEY2 0xCDEF89AB
102
103 /* timeout values */
104
105 #define FLASH_WRITE_TIMEOUT 10
106 #define FLASH_ERASE_TIMEOUT 100
107
108 struct stm32x_options {
109 uint16_t RDP;
110 uint16_t user_options;
111 uint16_t user_data;
112 uint16_t protection[4];
113 };
114
115 struct stm32x_flash_bank {
116 struct stm32x_options option_bytes;
117 int ppage_size;
118 int probed;
119
120 bool has_dual_banks;
121 /* used to access dual flash bank stm32xl */
122 uint32_t register_base;
123 uint16_t default_rdp;
124 int user_data_offset;
125 int option_offset;
126 uint32_t user_bank_size;
127 };
128
129 static int stm32x_mass_erase(struct flash_bank *bank);
130 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
131 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
132 uint32_t offset, uint32_t count);
133
134 /* flash bank stm32x <base> <size> 0 0 <target#>
135 */
136 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
137 {
138 struct stm32x_flash_bank *stm32x_info;
139
140 if (CMD_ARGC < 6)
141 return ERROR_COMMAND_SYNTAX_ERROR;
142
143 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
144
145 bank->driver_priv = stm32x_info;
146 stm32x_info->probed = 0;
147 stm32x_info->has_dual_banks = false;
148 stm32x_info->register_base = FLASH_REG_BASE_B0;
149 stm32x_info->user_bank_size = bank->size;
150
151 return ERROR_OK;
152 }
153
154 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
155 {
156 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
157 return reg + stm32x_info->register_base;
158 }
159
160 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
161 {
162 struct target *target = bank->target;
163 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
164 }
165
166 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
167 {
168 struct target *target = bank->target;
169 uint32_t status;
170 int retval = ERROR_OK;
171
172 /* wait for busy to clear */
173 for (;;) {
174 retval = stm32x_get_flash_status(bank, &status);
175 if (retval != ERROR_OK)
176 return retval;
177 LOG_DEBUG("status: 0x%" PRIx32 "", status);
178 if ((status & FLASH_BSY) == 0)
179 break;
180 if (timeout-- <= 0) {
181 LOG_ERROR("timed out waiting for flash");
182 return ERROR_FAIL;
183 }
184 alive_sleep(1);
185 }
186
187 if (status & FLASH_WRPRTERR) {
188 LOG_ERROR("stm32x device protected");
189 retval = ERROR_FAIL;
190 }
191
192 if (status & FLASH_PGERR) {
193 LOG_ERROR("stm32x device programming failed");
194 retval = ERROR_FAIL;
195 }
196
197 /* Clear but report errors */
198 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
199 /* If this operation fails, we ignore it and report the original
200 * retval
201 */
202 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
203 FLASH_WRPRTERR | FLASH_PGERR);
204 }
205 return retval;
206 }
207
208 static int stm32x_check_operation_supported(struct flash_bank *bank)
209 {
210 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
211
212 /* if we have a dual flash bank device then
213 * we need to perform option byte stuff on bank0 only */
214 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
215 LOG_ERROR("Option Byte Operation's must use bank0");
216 return ERROR_FLASH_OPERATION_FAILED;
217 }
218
219 return ERROR_OK;
220 }
221
222 static int stm32x_read_options(struct flash_bank *bank)
223 {
224 uint32_t optiondata;
225 struct stm32x_flash_bank *stm32x_info = NULL;
226 struct target *target = bank->target;
227
228 stm32x_info = bank->driver_priv;
229
230 /* read current option bytes */
231 int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
232 if (retval != ERROR_OK)
233 return retval;
234
235 stm32x_info->option_bytes.user_options = (optiondata >> stm32x_info->option_offset >> 2) & 0xffff;
236 stm32x_info->option_bytes.user_data = (optiondata >> stm32x_info->user_data_offset) & 0xffff;
237 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
238
239 if (optiondata & (1 << OPT_READOUT))
240 LOG_INFO("Device Security Bit Set");
241
242 /* each bit refers to a 4bank protection */
243 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
244 if (retval != ERROR_OK)
245 return retval;
246
247 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
248 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
249 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
250 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
251
252 return ERROR_OK;
253 }
254
255 static int stm32x_erase_options(struct flash_bank *bank)
256 {
257 struct stm32x_flash_bank *stm32x_info = NULL;
258 struct target *target = bank->target;
259
260 stm32x_info = bank->driver_priv;
261
262 /* read current options */
263 stm32x_read_options(bank);
264
265 /* unlock flash registers */
266 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
267 if (retval != ERROR_OK)
268 return retval;
269
270 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* unlock option flash registers */
275 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
276 if (retval != ERROR_OK)
277 return retval;
278 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
279 if (retval != ERROR_OK)
280 return retval;
281
282 /* erase option bytes */
283 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
284 if (retval != ERROR_OK)
285 return retval;
286 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
287 if (retval != ERROR_OK)
288 return retval;
289
290 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
291 if (retval != ERROR_OK)
292 return retval;
293
294 /* clear readout protection and complementary option bytes
295 * this will also force a device unlock if set */
296 stm32x_info->option_bytes.RDP = stm32x_info->default_rdp;
297
298 return ERROR_OK;
299 }
300
301 static int stm32x_write_options(struct flash_bank *bank)
302 {
303 struct stm32x_flash_bank *stm32x_info = NULL;
304 struct target *target = bank->target;
305
306 stm32x_info = bank->driver_priv;
307
308 /* unlock flash registers */
309 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
310 if (retval != ERROR_OK)
311 return retval;
312 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
313 if (retval != ERROR_OK)
314 return retval;
315
316 /* unlock option flash registers */
317 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
318 if (retval != ERROR_OK)
319 return retval;
320 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
321 if (retval != ERROR_OK)
322 return retval;
323
324 /* program option bytes */
325 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
326 if (retval != ERROR_OK)
327 return retval;
328
329 uint8_t opt_bytes[16];
330
331 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.RDP);
332 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user_options);
333 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.user_data & 0xff);
334 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.user_data >> 8) & 0xff);
335 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection[0]);
336 target_buffer_set_u16(target, opt_bytes + 10, stm32x_info->option_bytes.protection[1]);
337 target_buffer_set_u16(target, opt_bytes + 12, stm32x_info->option_bytes.protection[2]);
338 target_buffer_set_u16(target, opt_bytes + 14, stm32x_info->option_bytes.protection[3]);
339
340 uint32_t offset = STM32_OB_RDP - bank->base;
341 retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
342 if (retval != ERROR_OK) {
343 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
344 LOG_ERROR("working area required to erase options bytes");
345 return retval;
346 }
347
348 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
349 if (retval != ERROR_OK)
350 return retval;
351
352 return ERROR_OK;
353 }
354
355 static int stm32x_protect_check(struct flash_bank *bank)
356 {
357 struct target *target = bank->target;
358 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
359
360 uint32_t protection;
361 int i, s;
362 int num_bits;
363 int set;
364
365 int retval = stm32x_check_operation_supported(bank);
366 if (ERROR_OK != retval)
367 return retval;
368
369 /* medium density - each bit refers to a 4bank protection
370 * high density - each bit refers to a 2bank protection */
371 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
372 if (retval != ERROR_OK)
373 return retval;
374
375 /* medium density - each protection bit is for 4 * 1K pages
376 * high density - each protection bit is for 2 * 2K pages */
377 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
378
379 if (stm32x_info->ppage_size == 2) {
380 /* high density flash/connectivity line protection */
381
382 set = 1;
383
384 if (protection & (1 << 31))
385 set = 0;
386
387 /* bit 31 controls sector 62 - 255 protection for high density
388 * bit 31 controls sector 62 - 127 protection for connectivity line */
389 for (s = 62; s < bank->num_sectors; s++)
390 bank->sectors[s].is_protected = set;
391
392 if (bank->num_sectors > 61)
393 num_bits = 31;
394
395 for (i = 0; i < num_bits; i++) {
396 set = 1;
397
398 if (protection & (1 << i))
399 set = 0;
400
401 for (s = 0; s < stm32x_info->ppage_size; s++)
402 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
403 }
404 } else {
405 /* low/medium density flash protection */
406 for (i = 0; i < num_bits; i++) {
407 set = 1;
408
409 if (protection & (1 << i))
410 set = 0;
411
412 for (s = 0; s < stm32x_info->ppage_size; s++)
413 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
414 }
415 }
416
417 return ERROR_OK;
418 }
419
420 static int stm32x_erase(struct flash_bank *bank, int first, int last)
421 {
422 struct target *target = bank->target;
423 int i;
424
425 if (bank->target->state != TARGET_HALTED) {
426 LOG_ERROR("Target not halted");
427 return ERROR_TARGET_NOT_HALTED;
428 }
429
430 if ((first == 0) && (last == (bank->num_sectors - 1)))
431 return stm32x_mass_erase(bank);
432
433 /* unlock flash registers */
434 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
435 if (retval != ERROR_OK)
436 return retval;
437 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
438 if (retval != ERROR_OK)
439 return retval;
440
441 for (i = first; i <= last; i++) {
442 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
443 if (retval != ERROR_OK)
444 return retval;
445 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
446 bank->base + bank->sectors[i].offset);
447 if (retval != ERROR_OK)
448 return retval;
449 retval = target_write_u32(target,
450 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
451 if (retval != ERROR_OK)
452 return retval;
453
454 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
455 if (retval != ERROR_OK)
456 return retval;
457
458 bank->sectors[i].is_erased = 1;
459 }
460
461 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
462 if (retval != ERROR_OK)
463 return retval;
464
465 return ERROR_OK;
466 }
467
468 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
469 {
470 struct stm32x_flash_bank *stm32x_info = NULL;
471 struct target *target = bank->target;
472 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
473 int i, reg, bit;
474 int status;
475 uint32_t protection;
476
477 stm32x_info = bank->driver_priv;
478
479 if (target->state != TARGET_HALTED) {
480 LOG_ERROR("Target not halted");
481 return ERROR_TARGET_NOT_HALTED;
482 }
483
484 int retval = stm32x_check_operation_supported(bank);
485 if (ERROR_OK != retval)
486 return retval;
487
488 if ((first % stm32x_info->ppage_size) != 0) {
489 LOG_WARNING("aligned start protect sector to a %d sector boundary",
490 stm32x_info->ppage_size);
491 first = first - (first % stm32x_info->ppage_size);
492 }
493 if (((last + 1) % stm32x_info->ppage_size) != 0) {
494 LOG_WARNING("aligned end protect sector to a %d sector boundary",
495 stm32x_info->ppage_size);
496 last++;
497 last = last - (last % stm32x_info->ppage_size);
498 last--;
499 }
500
501 /* medium density - each bit refers to a 4bank protection
502 * high density - each bit refers to a 2bank protection */
503 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
504 if (retval != ERROR_OK)
505 return retval;
506
507 prot_reg[0] = (uint16_t)protection;
508 prot_reg[1] = (uint16_t)(protection >> 8);
509 prot_reg[2] = (uint16_t)(protection >> 16);
510 prot_reg[3] = (uint16_t)(protection >> 24);
511
512 if (stm32x_info->ppage_size == 2) {
513 /* high density flash */
514
515 /* bit 7 controls sector 62 - 255 protection */
516 if (last > 61) {
517 if (set)
518 prot_reg[3] &= ~(1 << 7);
519 else
520 prot_reg[3] |= (1 << 7);
521 }
522
523 if (first > 61)
524 first = 62;
525 if (last > 61)
526 last = 61;
527
528 for (i = first; i <= last; i++) {
529 reg = (i / stm32x_info->ppage_size) / 8;
530 bit = (i / stm32x_info->ppage_size) - (reg * 8);
531
532 if (set)
533 prot_reg[reg] &= ~(1 << bit);
534 else
535 prot_reg[reg] |= (1 << bit);
536 }
537 } else {
538 /* medium density flash */
539 for (i = first; i <= last; i++) {
540 reg = (i / stm32x_info->ppage_size) / 8;
541 bit = (i / stm32x_info->ppage_size) - (reg * 8);
542
543 if (set)
544 prot_reg[reg] &= ~(1 << bit);
545 else
546 prot_reg[reg] |= (1 << bit);
547 }
548 }
549
550 status = stm32x_erase_options(bank);
551 if (status != ERROR_OK)
552 return status;
553
554 stm32x_info->option_bytes.protection[0] = prot_reg[0];
555 stm32x_info->option_bytes.protection[1] = prot_reg[1];
556 stm32x_info->option_bytes.protection[2] = prot_reg[2];
557 stm32x_info->option_bytes.protection[3] = prot_reg[3];
558
559 return stm32x_write_options(bank);
560 }
561
562 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
563 uint32_t offset, uint32_t count)
564 {
565 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
566 struct target *target = bank->target;
567 uint32_t buffer_size = 16384;
568 struct working_area *write_algorithm;
569 struct working_area *source;
570 uint32_t address = bank->base + offset;
571 struct reg_param reg_params[5];
572 struct armv7m_algorithm armv7m_info;
573 int retval = ERROR_OK;
574
575 /* see contrib/loaders/flash/stm32f1x.S for src */
576
577 static const uint8_t stm32x_flash_write_code[] = {
578 /* #define STM32_FLASH_SR_OFFSET 0x0C */
579 /* wait_fifo: */
580 0x16, 0x68, /* ldr r6, [r2, #0] */
581 0x00, 0x2e, /* cmp r6, #0 */
582 0x18, 0xd0, /* beq exit */
583 0x55, 0x68, /* ldr r5, [r2, #4] */
584 0xb5, 0x42, /* cmp r5, r6 */
585 0xf9, 0xd0, /* beq wait_fifo */
586 0x2e, 0x88, /* ldrh r6, [r5, #0] */
587 0x26, 0x80, /* strh r6, [r4, #0] */
588 0x02, 0x35, /* adds r5, #2 */
589 0x02, 0x34, /* adds r4, #2 */
590 /* busy: */
591 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
592 0x01, 0x27, /* movs r7, #1 */
593 0x3e, 0x42, /* tst r6, r7 */
594 0xfb, 0xd1, /* bne busy */
595 0x14, 0x27, /* movs r7, #0x14 */
596 0x3e, 0x42, /* tst r6, r7 */
597 0x08, 0xd1, /* bne error */
598 0x9d, 0x42, /* cmp r5, r3 */
599 0x01, 0xd3, /* bcc no_wrap */
600 0x15, 0x46, /* mov r5, r2 */
601 0x08, 0x35, /* adds r5, #8 */
602 /* no_wrap: */
603 0x55, 0x60, /* str r5, [r2, #4] */
604 0x01, 0x39, /* subs r1, r1, #1 */
605 0x00, 0x29, /* cmp r1, #0 */
606 0x02, 0xd0, /* beq exit */
607 0xe5, 0xe7, /* b wait_fifo */
608 /* error: */
609 0x00, 0x20, /* movs r0, #0 */
610 0x50, 0x60, /* str r0, [r2, #4] */
611 /* exit: */
612 0x30, 0x46, /* mov r0, r6 */
613 0x00, 0xbe, /* bkpt #0 */
614 };
615
616 /* flash write code */
617 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
618 &write_algorithm) != ERROR_OK) {
619 LOG_WARNING("no working area available, can't do block memory writes");
620 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
621 }
622
623 retval = target_write_buffer(target, write_algorithm->address,
624 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
625 if (retval != ERROR_OK)
626 return retval;
627
628 /* memory buffer */
629 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
630 buffer_size /= 2;
631 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
632 if (buffer_size <= 256) {
633 /* we already allocated the writing code, but failed to get a
634 * buffer, free the algorithm */
635 target_free_working_area(target, write_algorithm);
636
637 LOG_WARNING("no large enough working area available, can't do block memory writes");
638 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
639 }
640 }
641
642 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
643 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
644 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
645 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
646 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
647
648 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
649 buf_set_u32(reg_params[1].value, 0, 32, count);
650 buf_set_u32(reg_params[2].value, 0, 32, source->address);
651 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
652 buf_set_u32(reg_params[4].value, 0, 32, address);
653
654 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
655 armv7m_info.core_mode = ARM_MODE_THREAD;
656
657 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
658 0, NULL,
659 5, reg_params,
660 source->address, source->size,
661 write_algorithm->address, 0,
662 &armv7m_info);
663
664 if (retval == ERROR_FLASH_OPERATION_FAILED) {
665 LOG_ERROR("flash write failed at address 0x%"PRIx32,
666 buf_get_u32(reg_params[4].value, 0, 32));
667
668 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
669 LOG_ERROR("flash memory not erased before writing");
670 /* Clear but report errors */
671 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
672 }
673
674 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
675 LOG_ERROR("flash memory write protected");
676 /* Clear but report errors */
677 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
678 }
679 }
680
681 target_free_working_area(target, source);
682 target_free_working_area(target, write_algorithm);
683
684 destroy_reg_param(&reg_params[0]);
685 destroy_reg_param(&reg_params[1]);
686 destroy_reg_param(&reg_params[2]);
687 destroy_reg_param(&reg_params[3]);
688 destroy_reg_param(&reg_params[4]);
689
690 return retval;
691 }
692
693 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
694 uint32_t offset, uint32_t count)
695 {
696 struct target *target = bank->target;
697 uint8_t *new_buffer = NULL;
698
699 if (bank->target->state != TARGET_HALTED) {
700 LOG_ERROR("Target not halted");
701 return ERROR_TARGET_NOT_HALTED;
702 }
703
704 if (offset & 0x1) {
705 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
706 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
707 }
708
709 /* If there's an odd number of bytes, the data has to be padded. Duplicate
710 * the buffer and use the normal code path with a single block write since
711 * it's probably cheaper than to special case the last odd write using
712 * discrete accesses. */
713 if (count & 1) {
714 new_buffer = malloc(count + 1);
715 if (new_buffer == NULL) {
716 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
717 return ERROR_FAIL;
718 }
719 LOG_INFO("odd number of bytes to write, padding with 0xff");
720 buffer = memcpy(new_buffer, buffer, count);
721 new_buffer[count++] = 0xff;
722 }
723
724 uint32_t words_remaining = count / 2;
725 int retval, retval2;
726
727 /* unlock flash registers */
728 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
729 if (retval != ERROR_OK)
730 goto cleanup;
731 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
732 if (retval != ERROR_OK)
733 goto cleanup;
734
735 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
736 if (retval != ERROR_OK)
737 goto cleanup;
738
739 /* try using a block write */
740 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
741
742 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
743 /* if block write failed (no sufficient working area),
744 * we use normal (slow) single halfword accesses */
745 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
746
747 while (words_remaining > 0) {
748 uint16_t value;
749 memcpy(&value, buffer, sizeof(uint16_t));
750
751 retval = target_write_u16(target, bank->base + offset, value);
752 if (retval != ERROR_OK)
753 goto reset_pg_and_lock;
754
755 retval = stm32x_wait_status_busy(bank, 5);
756 if (retval != ERROR_OK)
757 goto reset_pg_and_lock;
758
759 words_remaining--;
760 buffer += 2;
761 offset += 2;
762 }
763 }
764
765 reset_pg_and_lock:
766 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
767 if (retval == ERROR_OK)
768 retval = retval2;
769
770 cleanup:
771 if (new_buffer)
772 free(new_buffer);
773
774 return retval;
775 }
776
777 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
778 {
779 /* This check the device CPUID core register to detect
780 * the M0 from the M3 devices. */
781
782 struct target *target = bank->target;
783 uint32_t cpuid, device_id_register = 0;
784
785 /* Get the CPUID from the ARM Core
786 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
787 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
788 if (retval != ERROR_OK)
789 return retval;
790
791 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
792 /* 0xC20 is M0 devices */
793 device_id_register = 0x40015800;
794 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
795 /* 0xC23 is M3 devices */
796 device_id_register = 0xE0042000;
797 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
798 /* 0xC24 is M4 devices */
799 device_id_register = 0xE0042000;
800 } else {
801 LOG_ERROR("Cannot identify target as a stm32x");
802 return ERROR_FAIL;
803 }
804
805 /* read stm32 device id register */
806 retval = target_read_u32(target, device_id_register, device_id);
807 if (retval != ERROR_OK)
808 return retval;
809
810 return retval;
811 }
812
813 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
814 {
815 struct target *target = bank->target;
816 uint32_t cpuid, flash_size_reg;
817
818 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
819 if (retval != ERROR_OK)
820 return retval;
821
822 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
823 /* 0xC20 is M0 devices */
824 flash_size_reg = 0x1FFFF7CC;
825 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
826 /* 0xC23 is M3 devices */
827 flash_size_reg = 0x1FFFF7E0;
828 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
829 /* 0xC24 is M4 devices */
830 flash_size_reg = 0x1FFFF7CC;
831 } else {
832 LOG_ERROR("Cannot identify target as a stm32x");
833 return ERROR_FAIL;
834 }
835
836 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
837 if (retval != ERROR_OK)
838 return retval;
839
840 return retval;
841 }
842
843 static int stm32x_probe(struct flash_bank *bank)
844 {
845 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
846 int i;
847 uint16_t flash_size_in_kb;
848 uint16_t max_flash_size_in_kb;
849 uint32_t device_id;
850 int page_size;
851 uint32_t base_address = 0x08000000;
852
853 stm32x_info->probed = 0;
854 stm32x_info->register_base = FLASH_REG_BASE_B0;
855 stm32x_info->user_data_offset = 10;
856 stm32x_info->option_offset = 0;
857
858 /* default factory protection level */
859 stm32x_info->default_rdp = 0x5AA5;
860
861 /* read stm32 device id register */
862 int retval = stm32x_get_device_id(bank, &device_id);
863 if (retval != ERROR_OK)
864 return retval;
865
866 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
867
868 /* set page size, protection granularity and max flash size depending on family */
869 switch (device_id & 0xfff) {
870 case 0x410: /* medium density */
871 page_size = 1024;
872 stm32x_info->ppage_size = 4;
873 max_flash_size_in_kb = 128;
874 break;
875 case 0x412: /* low density */
876 page_size = 1024;
877 stm32x_info->ppage_size = 4;
878 max_flash_size_in_kb = 32;
879 break;
880 case 0x414: /* high density */
881 page_size = 2048;
882 stm32x_info->ppage_size = 2;
883 max_flash_size_in_kb = 512;
884 break;
885 case 0x418: /* connectivity line density */
886 page_size = 2048;
887 stm32x_info->ppage_size = 2;
888 max_flash_size_in_kb = 256;
889 break;
890 case 0x420: /* value line density */
891 page_size = 1024;
892 stm32x_info->ppage_size = 4;
893 max_flash_size_in_kb = 128;
894 break;
895 case 0x422: /* stm32f302/3xb/c */
896 page_size = 2048;
897 stm32x_info->ppage_size = 2;
898 max_flash_size_in_kb = 256;
899 stm32x_info->user_data_offset = 16;
900 stm32x_info->option_offset = 6;
901 stm32x_info->default_rdp = 0x55AA;
902 break;
903 case 0x446: /* stm32f303xD/E */
904 page_size = 2048;
905 stm32x_info->ppage_size = 2;
906 max_flash_size_in_kb = 512;
907 stm32x_info->user_data_offset = 16;
908 stm32x_info->option_offset = 6;
909 stm32x_info->default_rdp = 0x55AA;
910 break;
911 case 0x428: /* value line High density */
912 page_size = 2048;
913 stm32x_info->ppage_size = 4;
914 max_flash_size_in_kb = 128;
915 break;
916 case 0x430: /* xl line density (dual flash banks) */
917 page_size = 2048;
918 stm32x_info->ppage_size = 2;
919 max_flash_size_in_kb = 1024;
920 stm32x_info->has_dual_banks = true;
921 break;
922 case 0x432: /* stm32f37x */
923 page_size = 2048;
924 stm32x_info->ppage_size = 2;
925 max_flash_size_in_kb = 256;
926 stm32x_info->user_data_offset = 16;
927 stm32x_info->option_offset = 6;
928 stm32x_info->default_rdp = 0x55AA;
929 break;
930 case 0x438: /* stm32f33x */
931 case 0x439: /* stm32f302x6/8 */
932 page_size = 2048;
933 stm32x_info->ppage_size = 2;
934 max_flash_size_in_kb = 64;
935 stm32x_info->user_data_offset = 16;
936 stm32x_info->option_offset = 6;
937 stm32x_info->default_rdp = 0x55AA;
938 break;
939 case 0x440: /* stm32f05x */
940 case 0x444: /* stm32f03x */
941 case 0x445: /* stm32f04x */
942 page_size = 1024;
943 stm32x_info->ppage_size = 4;
944 max_flash_size_in_kb = 64;
945 stm32x_info->user_data_offset = 16;
946 stm32x_info->option_offset = 6;
947 stm32x_info->default_rdp = 0x55AA;
948 break;
949 case 0x448: /* stm32f07x */
950 case 0x442: /* stm32f09x */
951 page_size = 2048;
952 stm32x_info->ppage_size = 4;
953 max_flash_size_in_kb = 256;
954 stm32x_info->user_data_offset = 16;
955 stm32x_info->option_offset = 6;
956 stm32x_info->default_rdp = 0x55AA;
957 break;
958 default:
959 LOG_WARNING("Cannot identify target as a STM32 family.");
960 return ERROR_FAIL;
961 }
962
963 /* get flash size from target. */
964 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
965
966 /* failed reading flash size or flash size invalid (early silicon),
967 * default to max target family */
968 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
969 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
970 max_flash_size_in_kb);
971 flash_size_in_kb = max_flash_size_in_kb;
972 }
973
974 if (stm32x_info->has_dual_banks) {
975 /* split reported size into matching bank */
976 if (bank->base != 0x08080000) {
977 /* bank 0 will be fixed 512k */
978 flash_size_in_kb = 512;
979 } else {
980 flash_size_in_kb -= 512;
981 /* bank1 also uses a register offset */
982 stm32x_info->register_base = FLASH_REG_BASE_B1;
983 base_address = 0x08080000;
984 }
985 }
986
987 /* if the user sets the size manually then ignore the probed value
988 * this allows us to work around devices that have a invalid flash size register value */
989 if (stm32x_info->user_bank_size) {
990 LOG_INFO("ignoring flash probed value, using configured bank size");
991 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
992 }
993
994 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
995
996 /* did we assign flash size? */
997 assert(flash_size_in_kb != 0xffff);
998
999 /* calculate numbers of pages */
1000 int num_pages = flash_size_in_kb * 1024 / page_size;
1001
1002 /* check that calculation result makes sense */
1003 assert(num_pages > 0);
1004
1005 if (bank->sectors) {
1006 free(bank->sectors);
1007 bank->sectors = NULL;
1008 }
1009
1010 bank->base = base_address;
1011 bank->size = (num_pages * page_size);
1012 bank->num_sectors = num_pages;
1013 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1014
1015 for (i = 0; i < num_pages; i++) {
1016 bank->sectors[i].offset = i * page_size;
1017 bank->sectors[i].size = page_size;
1018 bank->sectors[i].is_erased = -1;
1019 bank->sectors[i].is_protected = 1;
1020 }
1021
1022 stm32x_info->probed = 1;
1023
1024 return ERROR_OK;
1025 }
1026
1027 static int stm32x_auto_probe(struct flash_bank *bank)
1028 {
1029 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1030 if (stm32x_info->probed)
1031 return ERROR_OK;
1032 return stm32x_probe(bank);
1033 }
1034
1035 #if 0
1036 COMMAND_HANDLER(stm32x_handle_part_id_command)
1037 {
1038 return ERROR_OK;
1039 }
1040 #endif
1041
1042 static const char *get_stm32f0_revision(uint16_t rev_id)
1043 {
1044 const char *rev_str = NULL;
1045
1046 switch (rev_id) {
1047 case 0x1000:
1048 rev_str = "1.0";
1049 break;
1050 case 0x2000:
1051 rev_str = "2.0";
1052 break;
1053 }
1054 return rev_str;
1055 }
1056
1057 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1058 {
1059 uint32_t dbgmcu_idcode;
1060
1061 /* read stm32 device id register */
1062 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1063 if (retval != ERROR_OK)
1064 return retval;
1065
1066 uint16_t device_id = dbgmcu_idcode & 0xfff;
1067 uint16_t rev_id = dbgmcu_idcode >> 16;
1068 const char *device_str;
1069 const char *rev_str = NULL;
1070
1071 switch (device_id) {
1072 case 0x410:
1073 device_str = "STM32F10x (Medium Density)";
1074
1075 switch (rev_id) {
1076 case 0x0000:
1077 rev_str = "A";
1078 break;
1079
1080 case 0x2000:
1081 rev_str = "B";
1082 break;
1083
1084 case 0x2001:
1085 rev_str = "Z";
1086 break;
1087
1088 case 0x2003:
1089 rev_str = "Y";
1090 break;
1091 }
1092 break;
1093
1094 case 0x412:
1095 device_str = "STM32F10x (Low Density)";
1096
1097 switch (rev_id) {
1098 case 0x1000:
1099 rev_str = "A";
1100 break;
1101 }
1102 break;
1103
1104 case 0x414:
1105 device_str = "STM32F10x (High Density)";
1106
1107 switch (rev_id) {
1108 case 0x1000:
1109 rev_str = "A";
1110 break;
1111
1112 case 0x1001:
1113 rev_str = "Z";
1114 break;
1115
1116 case 0x1003:
1117 rev_str = "Y";
1118 break;
1119 }
1120 break;
1121
1122 case 0x418:
1123 device_str = "STM32F10x (Connectivity)";
1124
1125 switch (rev_id) {
1126 case 0x1000:
1127 rev_str = "A";
1128 break;
1129
1130 case 0x1001:
1131 rev_str = "Z";
1132 break;
1133 }
1134 break;
1135
1136 case 0x420:
1137 device_str = "STM32F100 (Low/Medium Density)";
1138
1139 switch (rev_id) {
1140 case 0x1000:
1141 rev_str = "A";
1142 break;
1143
1144 case 0x1001:
1145 rev_str = "Z";
1146 break;
1147 }
1148 break;
1149
1150 case 0x422:
1151 device_str = "STM32F302xB/C";
1152
1153 switch (rev_id) {
1154 case 0x1000:
1155 rev_str = "A";
1156 break;
1157
1158 case 0x1001:
1159 rev_str = "Z";
1160 break;
1161
1162 case 0x1003:
1163 rev_str = "Y";
1164 break;
1165
1166 case 0x2000:
1167 rev_str = "B";
1168 break;
1169 }
1170 break;
1171
1172 case 0x428:
1173 device_str = "STM32F100 (High Density)";
1174
1175 switch (rev_id) {
1176 case 0x1000:
1177 rev_str = "A";
1178 break;
1179
1180 case 0x1001:
1181 rev_str = "Z";
1182 break;
1183 }
1184 break;
1185
1186 case 0x430:
1187 device_str = "STM32F10x (XL Density)";
1188
1189 switch (rev_id) {
1190 case 0x1000:
1191 rev_str = "A";
1192 break;
1193 }
1194 break;
1195
1196 case 0x432:
1197 device_str = "STM32F37x";
1198
1199 switch (rev_id) {
1200 case 0x1000:
1201 rev_str = "A";
1202 break;
1203
1204 case 0x2000:
1205 rev_str = "B";
1206 break;
1207 }
1208 break;
1209
1210 case 0x438:
1211 device_str = "STM32F33x";
1212
1213 switch (rev_id) {
1214 case 0x1000:
1215 rev_str = "A";
1216 break;
1217 }
1218 break;
1219
1220 case 0x439:
1221 device_str = "STM32F302x6/8";
1222
1223 switch (rev_id) {
1224 case 0x1000:
1225 rev_str = "A";
1226 break;
1227
1228 case 0x1001:
1229 rev_str = "Z";
1230 break;
1231 }
1232 break;
1233
1234 case 0x444:
1235 device_str = "STM32F03x";
1236 rev_str = get_stm32f0_revision(rev_id);
1237 break;
1238
1239 case 0x440:
1240 device_str = "STM32F05x";
1241 rev_str = get_stm32f0_revision(rev_id);
1242 break;
1243
1244 case 0x445:
1245 device_str = "STM32F04x";
1246 rev_str = get_stm32f0_revision(rev_id);
1247 break;
1248
1249 case 0x446:
1250 device_str = "STM32F303xD/E";
1251 switch (rev_id) {
1252 case 0x1000:
1253 rev_str = "A";
1254 break;
1255 }
1256 break;
1257
1258 case 0x448:
1259 device_str = "STM32F07x";
1260 rev_str = get_stm32f0_revision(rev_id);
1261 break;
1262
1263 case 0x442:
1264 device_str = "STM32F09x";
1265 rev_str = get_stm32f0_revision(rev_id);
1266 break;
1267
1268 default:
1269 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1270 return ERROR_FAIL;
1271 }
1272
1273 if (rev_str != NULL)
1274 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1275 else
1276 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1277
1278 return ERROR_OK;
1279 }
1280
1281 COMMAND_HANDLER(stm32x_handle_lock_command)
1282 {
1283 struct target *target = NULL;
1284 struct stm32x_flash_bank *stm32x_info = NULL;
1285
1286 if (CMD_ARGC < 1)
1287 return ERROR_COMMAND_SYNTAX_ERROR;
1288
1289 struct flash_bank *bank;
1290 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1291 if (ERROR_OK != retval)
1292 return retval;
1293
1294 stm32x_info = bank->driver_priv;
1295
1296 target = bank->target;
1297
1298 if (target->state != TARGET_HALTED) {
1299 LOG_ERROR("Target not halted");
1300 return ERROR_TARGET_NOT_HALTED;
1301 }
1302
1303 retval = stm32x_check_operation_supported(bank);
1304 if (ERROR_OK != retval)
1305 return retval;
1306
1307 if (stm32x_erase_options(bank) != ERROR_OK) {
1308 command_print(CMD_CTX, "stm32x failed to erase options");
1309 return ERROR_OK;
1310 }
1311
1312 /* set readout protection */
1313 stm32x_info->option_bytes.RDP = 0;
1314
1315 if (stm32x_write_options(bank) != ERROR_OK) {
1316 command_print(CMD_CTX, "stm32x failed to lock device");
1317 return ERROR_OK;
1318 }
1319
1320 command_print(CMD_CTX, "stm32x locked");
1321
1322 return ERROR_OK;
1323 }
1324
1325 COMMAND_HANDLER(stm32x_handle_unlock_command)
1326 {
1327 struct target *target = NULL;
1328
1329 if (CMD_ARGC < 1)
1330 return ERROR_COMMAND_SYNTAX_ERROR;
1331
1332 struct flash_bank *bank;
1333 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1334 if (ERROR_OK != retval)
1335 return retval;
1336
1337 target = bank->target;
1338
1339 if (target->state != TARGET_HALTED) {
1340 LOG_ERROR("Target not halted");
1341 return ERROR_TARGET_NOT_HALTED;
1342 }
1343
1344 retval = stm32x_check_operation_supported(bank);
1345 if (ERROR_OK != retval)
1346 return retval;
1347
1348 if (stm32x_erase_options(bank) != ERROR_OK) {
1349 command_print(CMD_CTX, "stm32x failed to unlock device");
1350 return ERROR_OK;
1351 }
1352
1353 if (stm32x_write_options(bank) != ERROR_OK) {
1354 command_print(CMD_CTX, "stm32x failed to lock device");
1355 return ERROR_OK;
1356 }
1357
1358 command_print(CMD_CTX, "stm32x unlocked.\n"
1359 "INFO: a reset or power cycle is required "
1360 "for the new settings to take effect.");
1361
1362 return ERROR_OK;
1363 }
1364
1365 COMMAND_HANDLER(stm32x_handle_options_read_command)
1366 {
1367 uint32_t optionbyte;
1368 struct target *target = NULL;
1369 struct stm32x_flash_bank *stm32x_info = NULL;
1370
1371 if (CMD_ARGC < 1)
1372 return ERROR_COMMAND_SYNTAX_ERROR;
1373
1374 struct flash_bank *bank;
1375 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1376 if (ERROR_OK != retval)
1377 return retval;
1378
1379 stm32x_info = bank->driver_priv;
1380
1381 target = bank->target;
1382
1383 if (target->state != TARGET_HALTED) {
1384 LOG_ERROR("Target not halted");
1385 return ERROR_TARGET_NOT_HALTED;
1386 }
1387
1388 retval = stm32x_check_operation_supported(bank);
1389 if (ERROR_OK != retval)
1390 return retval;
1391
1392 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1393 if (retval != ERROR_OK)
1394 return retval;
1395 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1396
1397 int user_data = optionbyte;
1398
1399 if (optionbyte >> OPT_ERROR & 1)
1400 command_print(CMD_CTX, "Option Byte Complement Error");
1401
1402 if (optionbyte >> OPT_READOUT & 1)
1403 command_print(CMD_CTX, "Readout Protection On");
1404 else
1405 command_print(CMD_CTX, "Readout Protection Off");
1406
1407 /* user option bytes are offset depending on variant */
1408 optionbyte >>= stm32x_info->option_offset;
1409
1410 if (optionbyte >> OPT_RDWDGSW & 1)
1411 command_print(CMD_CTX, "Software Watchdog");
1412 else
1413 command_print(CMD_CTX, "Hardware Watchdog");
1414
1415 if (optionbyte >> OPT_RDRSTSTOP & 1)
1416 command_print(CMD_CTX, "Stop: No reset generated");
1417 else
1418 command_print(CMD_CTX, "Stop: Reset generated");
1419
1420 if (optionbyte >> OPT_RDRSTSTDBY & 1)
1421 command_print(CMD_CTX, "Standby: No reset generated");
1422 else
1423 command_print(CMD_CTX, "Standby: Reset generated");
1424
1425 if (stm32x_info->has_dual_banks) {
1426 if (optionbyte >> OPT_BFB2 & 1)
1427 command_print(CMD_CTX, "Boot: Bank 0");
1428 else
1429 command_print(CMD_CTX, "Boot: Bank 1");
1430 }
1431
1432 command_print(CMD_CTX, "User Option0: 0x%02" PRIx8,
1433 (uint8_t)((user_data >> stm32x_info->user_data_offset) & 0xff));
1434 command_print(CMD_CTX, "User Option1: 0x%02" PRIx8,
1435 (uint8_t)((user_data >> (stm32x_info->user_data_offset + 8)) & 0xff));
1436
1437 return ERROR_OK;
1438 }
1439
1440 COMMAND_HANDLER(stm32x_handle_options_write_command)
1441 {
1442 struct target *target = NULL;
1443 struct stm32x_flash_bank *stm32x_info = NULL;
1444 uint16_t optionbyte;
1445
1446 if (CMD_ARGC < 2)
1447 return ERROR_COMMAND_SYNTAX_ERROR;
1448
1449 struct flash_bank *bank;
1450 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1451 if (ERROR_OK != retval)
1452 return retval;
1453
1454 stm32x_info = bank->driver_priv;
1455
1456 target = bank->target;
1457
1458 if (target->state != TARGET_HALTED) {
1459 LOG_ERROR("Target not halted");
1460 return ERROR_TARGET_NOT_HALTED;
1461 }
1462
1463 retval = stm32x_check_operation_supported(bank);
1464 if (ERROR_OK != retval)
1465 return retval;
1466
1467 retval = stm32x_read_options(bank);
1468 if (ERROR_OK != retval)
1469 return retval;
1470
1471 /* start with current options */
1472 optionbyte = stm32x_info->option_bytes.user_options;
1473
1474 /* skip over flash bank */
1475 CMD_ARGC--;
1476 CMD_ARGV++;
1477
1478 while (CMD_ARGC) {
1479 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1480 optionbyte |= (1 << 0);
1481 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1482 optionbyte &= ~(1 << 0);
1483 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1484 optionbyte |= (1 << 1);
1485 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1486 optionbyte &= ~(1 << 1);
1487 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1488 optionbyte |= (1 << 2);
1489 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1490 optionbyte &= ~(1 << 2);
1491 else if (stm32x_info->has_dual_banks) {
1492 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1493 optionbyte |= (1 << 3);
1494 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1495 optionbyte &= ~(1 << 3);
1496 else
1497 return ERROR_COMMAND_SYNTAX_ERROR;
1498 } else
1499 return ERROR_COMMAND_SYNTAX_ERROR;
1500 CMD_ARGC--;
1501 CMD_ARGV++;
1502 }
1503
1504 if (stm32x_erase_options(bank) != ERROR_OK) {
1505 command_print(CMD_CTX, "stm32x failed to erase options");
1506 return ERROR_OK;
1507 }
1508
1509 stm32x_info->option_bytes.user_options = optionbyte;
1510
1511 if (stm32x_write_options(bank) != ERROR_OK) {
1512 command_print(CMD_CTX, "stm32x failed to write options");
1513 return ERROR_OK;
1514 }
1515
1516 command_print(CMD_CTX, "stm32x write options complete.\n"
1517 "INFO: a reset or power cycle is required "
1518 "for the new settings to take effect.");
1519
1520 return ERROR_OK;
1521 }
1522
1523 static int stm32x_mass_erase(struct flash_bank *bank)
1524 {
1525 struct target *target = bank->target;
1526
1527 if (target->state != TARGET_HALTED) {
1528 LOG_ERROR("Target not halted");
1529 return ERROR_TARGET_NOT_HALTED;
1530 }
1531
1532 /* unlock option flash registers */
1533 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1534 if (retval != ERROR_OK)
1535 return retval;
1536 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1537 if (retval != ERROR_OK)
1538 return retval;
1539
1540 /* mass erase flash memory */
1541 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1542 if (retval != ERROR_OK)
1543 return retval;
1544 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1545 FLASH_MER | FLASH_STRT);
1546 if (retval != ERROR_OK)
1547 return retval;
1548
1549 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1550 if (retval != ERROR_OK)
1551 return retval;
1552
1553 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1554 if (retval != ERROR_OK)
1555 return retval;
1556
1557 return ERROR_OK;
1558 }
1559
1560 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1561 {
1562 int i;
1563
1564 if (CMD_ARGC < 1)
1565 return ERROR_COMMAND_SYNTAX_ERROR;
1566
1567 struct flash_bank *bank;
1568 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1569 if (ERROR_OK != retval)
1570 return retval;
1571
1572 retval = stm32x_mass_erase(bank);
1573 if (retval == ERROR_OK) {
1574 /* set all sectors as erased */
1575 for (i = 0; i < bank->num_sectors; i++)
1576 bank->sectors[i].is_erased = 1;
1577
1578 command_print(CMD_CTX, "stm32x mass erase complete");
1579 } else
1580 command_print(CMD_CTX, "stm32x mass erase failed");
1581
1582 return retval;
1583 }
1584
1585 static const struct command_registration stm32x_exec_command_handlers[] = {
1586 {
1587 .name = "lock",
1588 .handler = stm32x_handle_lock_command,
1589 .mode = COMMAND_EXEC,
1590 .usage = "bank_id",
1591 .help = "Lock entire flash device.",
1592 },
1593 {
1594 .name = "unlock",
1595 .handler = stm32x_handle_unlock_command,
1596 .mode = COMMAND_EXEC,
1597 .usage = "bank_id",
1598 .help = "Unlock entire protected flash device.",
1599 },
1600 {
1601 .name = "mass_erase",
1602 .handler = stm32x_handle_mass_erase_command,
1603 .mode = COMMAND_EXEC,
1604 .usage = "bank_id",
1605 .help = "Erase entire flash device.",
1606 },
1607 {
1608 .name = "options_read",
1609 .handler = stm32x_handle_options_read_command,
1610 .mode = COMMAND_EXEC,
1611 .usage = "bank_id",
1612 .help = "Read and display device option byte.",
1613 },
1614 {
1615 .name = "options_write",
1616 .handler = stm32x_handle_options_write_command,
1617 .mode = COMMAND_EXEC,
1618 .usage = "bank_id ('SWWDG'|'HWWDG') "
1619 "('RSTSTNDBY'|'NORSTSTNDBY') "
1620 "('RSTSTOP'|'NORSTSTOP')",
1621 .help = "Replace bits in device option byte.",
1622 },
1623 COMMAND_REGISTRATION_DONE
1624 };
1625
1626 static const struct command_registration stm32x_command_handlers[] = {
1627 {
1628 .name = "stm32f1x",
1629 .mode = COMMAND_ANY,
1630 .help = "stm32f1x flash command group",
1631 .usage = "",
1632 .chain = stm32x_exec_command_handlers,
1633 },
1634 COMMAND_REGISTRATION_DONE
1635 };
1636
1637 struct flash_driver stm32f1x_flash = {
1638 .name = "stm32f1x",
1639 .commands = stm32x_command_handlers,
1640 .flash_bank_command = stm32x_flash_bank_command,
1641 .erase = stm32x_erase,
1642 .protect = stm32x_protect,
1643 .write = stm32x_write,
1644 .read = default_flash_read,
1645 .probe = stm32x_probe,
1646 .auto_probe = stm32x_auto_probe,
1647 .erase_check = default_flash_blank_check,
1648 .protect_check = stm32x_protect_check,
1649 .info = get_stm32x_info,
1650 .free_driver_priv = default_flash_free_driver_priv,
1651 };
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