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[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 /* timeout values */
105
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
108
109 struct stm32x_options {
110 uint8_t rdp;
111 uint8_t user;
112 uint16_t data;
113 uint32_t protection;
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 bool probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
125 uint8_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = false;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
153
154 return ERROR_OK;
155 }
156
157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
158 {
159 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
160 return reg + stm32x_info->register_base;
161 }
162
163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
164 {
165 struct target *target = bank->target;
166 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
167 }
168
169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
170 {
171 struct target *target = bank->target;
172 uint32_t status;
173 int retval = ERROR_OK;
174
175 /* wait for busy to clear */
176 for (;;) {
177 retval = stm32x_get_flash_status(bank, &status);
178 if (retval != ERROR_OK)
179 return retval;
180 LOG_DEBUG("status: 0x%" PRIx32 "", status);
181 if ((status & FLASH_BSY) == 0)
182 break;
183 if (timeout-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
185 return ERROR_FAIL;
186 }
187 alive_sleep(1);
188 }
189
190 if (status & FLASH_WRPRTERR) {
191 LOG_ERROR("stm32x device protected");
192 retval = ERROR_FAIL;
193 }
194
195 if (status & FLASH_PGERR) {
196 LOG_ERROR("stm32x device programming failed");
197 retval = ERROR_FAIL;
198 }
199
200 /* Clear but report errors */
201 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
202 /* If this operation fails, we ignore it and report the original
203 * retval
204 */
205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
206 FLASH_WRPRTERR | FLASH_PGERR);
207 }
208 return retval;
209 }
210
211 static int stm32x_check_operation_supported(struct flash_bank *bank)
212 {
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
214
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
218 LOG_ERROR("Option Byte Operation's must use bank0");
219 return ERROR_FLASH_OPERATION_FAILED;
220 }
221
222 return ERROR_OK;
223 }
224
225 static int stm32x_read_options(struct flash_bank *bank)
226 {
227 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
228 struct target *target = bank->target;
229 uint32_t option_bytes;
230 int retval;
231
232 /* read user and read protection option bytes, user data option bytes */
233 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
238 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
239 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
240
241 /* read write protection option bytes */
242 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
243 if (retval != ERROR_OK)
244 return retval;
245
246 return ERROR_OK;
247 }
248
249 static int stm32x_erase_options(struct flash_bank *bank)
250 {
251 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
252 struct target *target = bank->target;
253
254 /* read current options */
255 stm32x_read_options(bank);
256
257 /* unlock flash registers */
258 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
259 if (retval != ERROR_OK)
260 return retval;
261
262 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
263 if (retval != ERROR_OK)
264 return retval;
265
266 /* unlock option flash registers */
267 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
268 if (retval != ERROR_OK)
269 return retval;
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* erase option bytes */
275 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
276 if (retval != ERROR_OK)
277 return retval;
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
280 return retval;
281
282 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
283 if (retval != ERROR_OK)
284 return retval;
285
286 /* clear read protection option byte
287 * this will also force a device unlock if set */
288 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
289
290 return ERROR_OK;
291 }
292
293 static int stm32x_write_options(struct flash_bank *bank)
294 {
295 struct stm32x_flash_bank *stm32x_info = NULL;
296 struct target *target = bank->target;
297
298 stm32x_info = bank->driver_priv;
299
300 /* unlock flash registers */
301 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
302 if (retval != ERROR_OK)
303 return retval;
304 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
305 if (retval != ERROR_OK)
306 return retval;
307
308 /* unlock option flash registers */
309 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
310 if (retval != ERROR_OK)
311 return retval;
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
313 if (retval != ERROR_OK)
314 return retval;
315
316 /* program option bytes */
317 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
318 if (retval != ERROR_OK)
319 return retval;
320
321 uint8_t opt_bytes[16];
322
323 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
324 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
325 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
326 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
327 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
328 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
329 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
330 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
331
332 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
333 if (retval != ERROR_OK) {
334 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
335 LOG_ERROR("working area required to erase options bytes");
336 return retval;
337 }
338
339 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
340 if (retval != ERROR_OK)
341 return retval;
342
343 return ERROR_OK;
344 }
345
346 static int stm32x_protect_check(struct flash_bank *bank)
347 {
348 struct target *target = bank->target;
349 uint32_t protection;
350
351 int retval = stm32x_check_operation_supported(bank);
352 if (ERROR_OK != retval)
353 return retval;
354
355 /* medium density - each bit refers to a 4 sector protection block
356 * high density - each bit refers to a 2 sector protection block
357 * bit 31 refers to all remaining sectors in a bank */
358 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
359 if (retval != ERROR_OK)
360 return retval;
361
362 for (int i = 0; i < bank->num_prot_blocks; i++)
363 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
364
365 return ERROR_OK;
366 }
367
368 static int stm32x_erase(struct flash_bank *bank, int first, int last)
369 {
370 struct target *target = bank->target;
371
372 if (bank->target->state != TARGET_HALTED) {
373 LOG_ERROR("Target not halted");
374 return ERROR_TARGET_NOT_HALTED;
375 }
376
377 if ((first == 0) && (last == (bank->num_sectors - 1)))
378 return stm32x_mass_erase(bank);
379
380 /* unlock flash registers */
381 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
382 if (retval != ERROR_OK)
383 return retval;
384 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
385 if (retval != ERROR_OK)
386 return retval;
387
388 for (int i = first; i <= last; i++) {
389 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
390 if (retval != ERROR_OK)
391 return retval;
392 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
393 bank->base + bank->sectors[i].offset);
394 if (retval != ERROR_OK)
395 return retval;
396 retval = target_write_u32(target,
397 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
398 if (retval != ERROR_OK)
399 return retval;
400
401 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
402 if (retval != ERROR_OK)
403 return retval;
404
405 bank->sectors[i].is_erased = 1;
406 }
407
408 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
409 if (retval != ERROR_OK)
410 return retval;
411
412 return ERROR_OK;
413 }
414
415 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
416 {
417 struct target *target = bank->target;
418 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
419
420 if (target->state != TARGET_HALTED) {
421 LOG_ERROR("Target not halted");
422 return ERROR_TARGET_NOT_HALTED;
423 }
424
425 int retval = stm32x_check_operation_supported(bank);
426 if (retval != ERROR_OK)
427 return retval;
428
429 retval = stm32x_erase_options(bank);
430 if (retval != ERROR_OK) {
431 LOG_ERROR("stm32x failed to erase options");
432 return retval;
433 }
434
435 for (int i = first; i <= last; i++) {
436 if (set)
437 stm32x_info->option_bytes.protection &= ~(1 << i);
438 else
439 stm32x_info->option_bytes.protection |= (1 << i);
440 }
441
442 return stm32x_write_options(bank);
443 }
444
445 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
446 uint32_t address, uint32_t count)
447 {
448 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
449 struct target *target = bank->target;
450 uint32_t buffer_size = 16384;
451 struct working_area *write_algorithm;
452 struct working_area *source;
453 struct reg_param reg_params[5];
454 struct armv7m_algorithm armv7m_info;
455 int retval = ERROR_OK;
456
457 static const uint8_t stm32x_flash_write_code[] = {
458 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
459 };
460
461 /* flash write code */
462 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
463 &write_algorithm) != ERROR_OK) {
464 LOG_WARNING("no working area available, can't do block memory writes");
465 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
466 }
467
468 retval = target_write_buffer(target, write_algorithm->address,
469 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
470 if (retval != ERROR_OK) {
471 target_free_working_area(target, write_algorithm);
472 return retval;
473 }
474
475 /* memory buffer */
476 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
477 buffer_size /= 2;
478 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
479 if (buffer_size <= 256) {
480 /* we already allocated the writing code, but failed to get a
481 * buffer, free the algorithm */
482 target_free_working_area(target, write_algorithm);
483
484 LOG_WARNING("no large enough working area available, can't do block memory writes");
485 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
486 }
487 }
488
489 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
490 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
491 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
492 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
493 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
494
495 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
496 buf_set_u32(reg_params[1].value, 0, 32, count);
497 buf_set_u32(reg_params[2].value, 0, 32, source->address);
498 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
499 buf_set_u32(reg_params[4].value, 0, 32, address);
500
501 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
502 armv7m_info.core_mode = ARM_MODE_THREAD;
503
504 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
505 0, NULL,
506 5, reg_params,
507 source->address, source->size,
508 write_algorithm->address, 0,
509 &armv7m_info);
510
511 if (retval == ERROR_FLASH_OPERATION_FAILED) {
512 LOG_ERROR("flash write failed at address 0x%"PRIx32,
513 buf_get_u32(reg_params[4].value, 0, 32));
514
515 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
516 LOG_ERROR("flash memory not erased before writing");
517 /* Clear but report errors */
518 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
519 }
520
521 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
522 LOG_ERROR("flash memory write protected");
523 /* Clear but report errors */
524 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
525 }
526 }
527
528 target_free_working_area(target, source);
529 target_free_working_area(target, write_algorithm);
530
531 destroy_reg_param(&reg_params[0]);
532 destroy_reg_param(&reg_params[1]);
533 destroy_reg_param(&reg_params[2]);
534 destroy_reg_param(&reg_params[3]);
535 destroy_reg_param(&reg_params[4]);
536
537 return retval;
538 }
539
540 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
541 uint32_t offset, uint32_t count)
542 {
543 struct target *target = bank->target;
544 uint8_t *new_buffer = NULL;
545
546 if (bank->target->state != TARGET_HALTED) {
547 LOG_ERROR("Target not halted");
548 return ERROR_TARGET_NOT_HALTED;
549 }
550
551 if (offset & 0x1) {
552 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
553 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
554 }
555
556 /* If there's an odd number of bytes, the data has to be padded. Duplicate
557 * the buffer and use the normal code path with a single block write since
558 * it's probably cheaper than to special case the last odd write using
559 * discrete accesses. */
560 if (count & 1) {
561 new_buffer = malloc(count + 1);
562 if (new_buffer == NULL) {
563 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
564 return ERROR_FAIL;
565 }
566 LOG_INFO("odd number of bytes to write, padding with 0xff");
567 buffer = memcpy(new_buffer, buffer, count);
568 new_buffer[count++] = 0xff;
569 }
570
571 uint32_t words_remaining = count / 2;
572 int retval, retval2;
573
574 /* unlock flash registers */
575 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
576 if (retval != ERROR_OK)
577 goto cleanup;
578 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
579 if (retval != ERROR_OK)
580 goto cleanup;
581
582 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
583 if (retval != ERROR_OK)
584 goto cleanup;
585
586 /* try using a block write */
587 retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
588
589 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
590 /* if block write failed (no sufficient working area),
591 * we use normal (slow) single halfword accesses */
592 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
593
594 while (words_remaining > 0) {
595 uint16_t value;
596 memcpy(&value, buffer, sizeof(uint16_t));
597
598 retval = target_write_u16(target, bank->base + offset, value);
599 if (retval != ERROR_OK)
600 goto reset_pg_and_lock;
601
602 retval = stm32x_wait_status_busy(bank, 5);
603 if (retval != ERROR_OK)
604 goto reset_pg_and_lock;
605
606 words_remaining--;
607 buffer += 2;
608 offset += 2;
609 }
610 }
611
612 reset_pg_and_lock:
613 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
614 if (retval == ERROR_OK)
615 retval = retval2;
616
617 cleanup:
618 if (new_buffer)
619 free(new_buffer);
620
621 return retval;
622 }
623
624 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
625 {
626 /* This check the device CPUID core register to detect
627 * the M0 from the M3 devices. */
628
629 struct target *target = bank->target;
630 uint32_t cpuid, device_id_register = 0;
631
632 /* Get the CPUID from the ARM Core
633 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
634 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
635 if (retval != ERROR_OK)
636 return retval;
637
638 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
639 /* 0xC20 is M0 devices */
640 device_id_register = 0x40015800;
641 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
642 /* 0xC23 is M3 devices */
643 device_id_register = 0xE0042000;
644 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
645 /* 0xC24 is M4 devices */
646 device_id_register = 0xE0042000;
647 } else {
648 LOG_ERROR("Cannot identify target as a stm32x");
649 return ERROR_FAIL;
650 }
651
652 /* read stm32 device id register */
653 retval = target_read_u32(target, device_id_register, device_id);
654 if (retval != ERROR_OK)
655 return retval;
656
657 return retval;
658 }
659
660 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
661 {
662 struct target *target = bank->target;
663 uint32_t cpuid, flash_size_reg;
664
665 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
666 if (retval != ERROR_OK)
667 return retval;
668
669 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
670 /* 0xC20 is M0 devices */
671 flash_size_reg = 0x1FFFF7CC;
672 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
673 /* 0xC23 is M3 devices */
674 flash_size_reg = 0x1FFFF7E0;
675 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
676 /* 0xC24 is M4 devices */
677 flash_size_reg = 0x1FFFF7CC;
678 } else {
679 LOG_ERROR("Cannot identify target as a stm32x");
680 return ERROR_FAIL;
681 }
682
683 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
684 if (retval != ERROR_OK)
685 return retval;
686
687 return retval;
688 }
689
690 static int stm32x_probe(struct flash_bank *bank)
691 {
692 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
693 uint16_t flash_size_in_kb;
694 uint16_t max_flash_size_in_kb;
695 uint32_t device_id;
696 int page_size;
697 uint32_t base_address = 0x08000000;
698
699 stm32x_info->probed = false;
700 stm32x_info->register_base = FLASH_REG_BASE_B0;
701 stm32x_info->user_data_offset = 10;
702 stm32x_info->option_offset = 0;
703
704 /* default factory read protection level 0 */
705 stm32x_info->default_rdp = 0xA5;
706
707 /* read stm32 device id register */
708 int retval = stm32x_get_device_id(bank, &device_id);
709 if (retval != ERROR_OK)
710 return retval;
711
712 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
713
714 /* set page size, protection granularity and max flash size depending on family */
715 switch (device_id & 0xfff) {
716 case 0x440: /* stm32f05x */
717 page_size = 1024;
718 stm32x_info->ppage_size = 4;
719 max_flash_size_in_kb = 64;
720 stm32x_info->user_data_offset = 16;
721 stm32x_info->option_offset = 6;
722 stm32x_info->default_rdp = 0xAA;
723 stm32x_info->can_load_options = true;
724 break;
725 case 0x444: /* stm32f03x */
726 case 0x445: /* stm32f04x */
727 page_size = 1024;
728 stm32x_info->ppage_size = 4;
729 max_flash_size_in_kb = 32;
730 stm32x_info->user_data_offset = 16;
731 stm32x_info->option_offset = 6;
732 stm32x_info->default_rdp = 0xAA;
733 stm32x_info->can_load_options = true;
734 break;
735 case 0x448: /* stm32f07x */
736 page_size = 2048;
737 stm32x_info->ppage_size = 4;
738 max_flash_size_in_kb = 128;
739 stm32x_info->user_data_offset = 16;
740 stm32x_info->option_offset = 6;
741 stm32x_info->default_rdp = 0xAA;
742 stm32x_info->can_load_options = true;
743 break;
744 case 0x442: /* stm32f09x */
745 page_size = 2048;
746 stm32x_info->ppage_size = 4;
747 max_flash_size_in_kb = 256;
748 stm32x_info->user_data_offset = 16;
749 stm32x_info->option_offset = 6;
750 stm32x_info->default_rdp = 0xAA;
751 stm32x_info->can_load_options = true;
752 break;
753 case 0x410: /* stm32f1x medium-density */
754 page_size = 1024;
755 stm32x_info->ppage_size = 4;
756 max_flash_size_in_kb = 128;
757 break;
758 case 0x412: /* stm32f1x low-density */
759 page_size = 1024;
760 stm32x_info->ppage_size = 4;
761 max_flash_size_in_kb = 32;
762 break;
763 case 0x414: /* stm32f1x high-density */
764 page_size = 2048;
765 stm32x_info->ppage_size = 2;
766 max_flash_size_in_kb = 512;
767 break;
768 case 0x418: /* stm32f1x connectivity */
769 page_size = 2048;
770 stm32x_info->ppage_size = 2;
771 max_flash_size_in_kb = 256;
772 break;
773 case 0x430: /* stm32f1 XL-density (dual flash banks) */
774 page_size = 2048;
775 stm32x_info->ppage_size = 2;
776 max_flash_size_in_kb = 1024;
777 stm32x_info->has_dual_banks = true;
778 break;
779 case 0x420: /* stm32f100xx low- and medium-density value line */
780 page_size = 1024;
781 stm32x_info->ppage_size = 4;
782 max_flash_size_in_kb = 128;
783 break;
784 case 0x428: /* stm32f100xx high-density value line */
785 page_size = 2048;
786 stm32x_info->ppage_size = 4;
787 max_flash_size_in_kb = 512;
788 break;
789 case 0x422: /* stm32f302/3xb/c */
790 page_size = 2048;
791 stm32x_info->ppage_size = 2;
792 max_flash_size_in_kb = 256;
793 stm32x_info->user_data_offset = 16;
794 stm32x_info->option_offset = 6;
795 stm32x_info->default_rdp = 0xAA;
796 stm32x_info->can_load_options = true;
797 break;
798 case 0x446: /* stm32f303xD/E */
799 page_size = 2048;
800 stm32x_info->ppage_size = 2;
801 max_flash_size_in_kb = 512;
802 stm32x_info->user_data_offset = 16;
803 stm32x_info->option_offset = 6;
804 stm32x_info->default_rdp = 0xAA;
805 stm32x_info->can_load_options = true;
806 break;
807 case 0x432: /* stm32f37x */
808 page_size = 2048;
809 stm32x_info->ppage_size = 2;
810 max_flash_size_in_kb = 256;
811 stm32x_info->user_data_offset = 16;
812 stm32x_info->option_offset = 6;
813 stm32x_info->default_rdp = 0xAA;
814 stm32x_info->can_load_options = true;
815 break;
816 case 0x438: /* stm32f33x */
817 case 0x439: /* stm32f302x6/8 */
818 page_size = 2048;
819 stm32x_info->ppage_size = 2;
820 max_flash_size_in_kb = 64;
821 stm32x_info->user_data_offset = 16;
822 stm32x_info->option_offset = 6;
823 stm32x_info->default_rdp = 0xAA;
824 stm32x_info->can_load_options = true;
825 break;
826 default:
827 LOG_WARNING("Cannot identify target as a STM32 family.");
828 return ERROR_FAIL;
829 }
830
831 /* get flash size from target. */
832 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
833
834 /* failed reading flash size or flash size invalid (early silicon),
835 * default to max target family */
836 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
837 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
838 max_flash_size_in_kb);
839 flash_size_in_kb = max_flash_size_in_kb;
840 }
841
842 if (stm32x_info->has_dual_banks) {
843 /* split reported size into matching bank */
844 if (bank->base != 0x08080000) {
845 /* bank 0 will be fixed 512k */
846 flash_size_in_kb = 512;
847 } else {
848 flash_size_in_kb -= 512;
849 /* bank1 also uses a register offset */
850 stm32x_info->register_base = FLASH_REG_BASE_B1;
851 base_address = 0x08080000;
852 }
853 }
854
855 /* if the user sets the size manually then ignore the probed value
856 * this allows us to work around devices that have a invalid flash size register value */
857 if (stm32x_info->user_bank_size) {
858 LOG_INFO("ignoring flash probed value, using configured bank size");
859 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
860 }
861
862 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
863
864 /* did we assign flash size? */
865 assert(flash_size_in_kb != 0xffff);
866
867 /* calculate numbers of pages */
868 int num_pages = flash_size_in_kb * 1024 / page_size;
869
870 /* check that calculation result makes sense */
871 assert(num_pages > 0);
872
873 if (bank->sectors) {
874 free(bank->sectors);
875 bank->sectors = NULL;
876 }
877
878 if (bank->prot_blocks) {
879 free(bank->prot_blocks);
880 bank->prot_blocks = NULL;
881 }
882
883 bank->base = base_address;
884 bank->size = (num_pages * page_size);
885
886 bank->num_sectors = num_pages;
887 bank->sectors = alloc_block_array(0, page_size, num_pages);
888 if (!bank->sectors)
889 return ERROR_FAIL;
890
891 /* calculate number of write protection blocks */
892 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
893 if (num_prot_blocks > 32)
894 num_prot_blocks = 32;
895
896 bank->num_prot_blocks = num_prot_blocks;
897 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
898 if (!bank->prot_blocks)
899 return ERROR_FAIL;
900
901 if (num_prot_blocks == 32)
902 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
903
904 stm32x_info->probed = true;
905
906 return ERROR_OK;
907 }
908
909 static int stm32x_auto_probe(struct flash_bank *bank)
910 {
911 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
912 if (stm32x_info->probed)
913 return ERROR_OK;
914 return stm32x_probe(bank);
915 }
916
917 #if 0
918 COMMAND_HANDLER(stm32x_handle_part_id_command)
919 {
920 return ERROR_OK;
921 }
922 #endif
923
924 static const char *get_stm32f0_revision(uint16_t rev_id)
925 {
926 const char *rev_str = NULL;
927
928 switch (rev_id) {
929 case 0x1000:
930 rev_str = "1.0";
931 break;
932 case 0x2000:
933 rev_str = "2.0";
934 break;
935 }
936 return rev_str;
937 }
938
939 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
940 {
941 uint32_t dbgmcu_idcode;
942
943 /* read stm32 device id register */
944 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
945 if (retval != ERROR_OK)
946 return retval;
947
948 uint16_t device_id = dbgmcu_idcode & 0xfff;
949 uint16_t rev_id = dbgmcu_idcode >> 16;
950 const char *device_str;
951 const char *rev_str = NULL;
952
953 switch (device_id) {
954 case 0x410:
955 device_str = "STM32F10x (Medium Density)";
956
957 switch (rev_id) {
958 case 0x0000:
959 rev_str = "A";
960 break;
961
962 case 0x2000:
963 rev_str = "B";
964 break;
965
966 case 0x2001:
967 rev_str = "Z";
968 break;
969
970 case 0x2003:
971 rev_str = "Y";
972 break;
973 }
974 break;
975
976 case 0x412:
977 device_str = "STM32F10x (Low Density)";
978
979 switch (rev_id) {
980 case 0x1000:
981 rev_str = "A";
982 break;
983 }
984 break;
985
986 case 0x414:
987 device_str = "STM32F10x (High Density)";
988
989 switch (rev_id) {
990 case 0x1000:
991 rev_str = "A";
992 break;
993
994 case 0x1001:
995 rev_str = "Z";
996 break;
997
998 case 0x1003:
999 rev_str = "Y";
1000 break;
1001 }
1002 break;
1003
1004 case 0x418:
1005 device_str = "STM32F10x (Connectivity)";
1006
1007 switch (rev_id) {
1008 case 0x1000:
1009 rev_str = "A";
1010 break;
1011
1012 case 0x1001:
1013 rev_str = "Z";
1014 break;
1015 }
1016 break;
1017
1018 case 0x420:
1019 device_str = "STM32F100 (Low/Medium Density)";
1020
1021 switch (rev_id) {
1022 case 0x1000:
1023 rev_str = "A";
1024 break;
1025
1026 case 0x1001:
1027 rev_str = "Z";
1028 break;
1029 }
1030 break;
1031
1032 case 0x422:
1033 device_str = "STM32F302xB/C";
1034
1035 switch (rev_id) {
1036 case 0x1000:
1037 rev_str = "A";
1038 break;
1039
1040 case 0x1001:
1041 rev_str = "Z";
1042 break;
1043
1044 case 0x1003:
1045 rev_str = "Y";
1046 break;
1047
1048 case 0x2000:
1049 rev_str = "B";
1050 break;
1051 }
1052 break;
1053
1054 case 0x428:
1055 device_str = "STM32F100 (High Density)";
1056
1057 switch (rev_id) {
1058 case 0x1000:
1059 rev_str = "A";
1060 break;
1061
1062 case 0x1001:
1063 rev_str = "Z";
1064 break;
1065 }
1066 break;
1067
1068 case 0x430:
1069 device_str = "STM32F10x (XL Density)";
1070
1071 switch (rev_id) {
1072 case 0x1000:
1073 rev_str = "A";
1074 break;
1075 }
1076 break;
1077
1078 case 0x432:
1079 device_str = "STM32F37x";
1080
1081 switch (rev_id) {
1082 case 0x1000:
1083 rev_str = "A";
1084 break;
1085
1086 case 0x2000:
1087 rev_str = "B";
1088 break;
1089 }
1090 break;
1091
1092 case 0x438:
1093 device_str = "STM32F33x";
1094
1095 switch (rev_id) {
1096 case 0x1000:
1097 rev_str = "A";
1098 break;
1099 }
1100 break;
1101
1102 case 0x439:
1103 device_str = "STM32F302x6/8";
1104
1105 switch (rev_id) {
1106 case 0x1000:
1107 rev_str = "A";
1108 break;
1109
1110 case 0x1001:
1111 rev_str = "Z";
1112 break;
1113 }
1114 break;
1115
1116 case 0x444:
1117 device_str = "STM32F03x";
1118 rev_str = get_stm32f0_revision(rev_id);
1119 break;
1120
1121 case 0x440:
1122 device_str = "STM32F05x";
1123 rev_str = get_stm32f0_revision(rev_id);
1124 break;
1125
1126 case 0x445:
1127 device_str = "STM32F04x";
1128 rev_str = get_stm32f0_revision(rev_id);
1129 break;
1130
1131 case 0x446:
1132 device_str = "STM32F303xD/E";
1133 switch (rev_id) {
1134 case 0x1000:
1135 rev_str = "A";
1136 break;
1137 }
1138 break;
1139
1140 case 0x448:
1141 device_str = "STM32F07x";
1142 rev_str = get_stm32f0_revision(rev_id);
1143 break;
1144
1145 case 0x442:
1146 device_str = "STM32F09x";
1147 rev_str = get_stm32f0_revision(rev_id);
1148 break;
1149
1150 default:
1151 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1152 return ERROR_FAIL;
1153 }
1154
1155 if (rev_str != NULL)
1156 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1157 else
1158 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1159
1160 return ERROR_OK;
1161 }
1162
1163 COMMAND_HANDLER(stm32x_handle_lock_command)
1164 {
1165 struct target *target = NULL;
1166 struct stm32x_flash_bank *stm32x_info = NULL;
1167
1168 if (CMD_ARGC < 1)
1169 return ERROR_COMMAND_SYNTAX_ERROR;
1170
1171 struct flash_bank *bank;
1172 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1173 if (ERROR_OK != retval)
1174 return retval;
1175
1176 stm32x_info = bank->driver_priv;
1177
1178 target = bank->target;
1179
1180 if (target->state != TARGET_HALTED) {
1181 LOG_ERROR("Target not halted");
1182 return ERROR_TARGET_NOT_HALTED;
1183 }
1184
1185 retval = stm32x_check_operation_supported(bank);
1186 if (ERROR_OK != retval)
1187 return retval;
1188
1189 if (stm32x_erase_options(bank) != ERROR_OK) {
1190 command_print(CMD, "stm32x failed to erase options");
1191 return ERROR_OK;
1192 }
1193
1194 /* set readout protection */
1195 stm32x_info->option_bytes.rdp = 0;
1196
1197 if (stm32x_write_options(bank) != ERROR_OK) {
1198 command_print(CMD, "stm32x failed to lock device");
1199 return ERROR_OK;
1200 }
1201
1202 command_print(CMD, "stm32x locked");
1203
1204 return ERROR_OK;
1205 }
1206
1207 COMMAND_HANDLER(stm32x_handle_unlock_command)
1208 {
1209 struct target *target = NULL;
1210
1211 if (CMD_ARGC < 1)
1212 return ERROR_COMMAND_SYNTAX_ERROR;
1213
1214 struct flash_bank *bank;
1215 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1216 if (ERROR_OK != retval)
1217 return retval;
1218
1219 target = bank->target;
1220
1221 if (target->state != TARGET_HALTED) {
1222 LOG_ERROR("Target not halted");
1223 return ERROR_TARGET_NOT_HALTED;
1224 }
1225
1226 retval = stm32x_check_operation_supported(bank);
1227 if (ERROR_OK != retval)
1228 return retval;
1229
1230 if (stm32x_erase_options(bank) != ERROR_OK) {
1231 command_print(CMD, "stm32x failed to erase options");
1232 return ERROR_OK;
1233 }
1234
1235 if (stm32x_write_options(bank) != ERROR_OK) {
1236 command_print(CMD, "stm32x failed to unlock device");
1237 return ERROR_OK;
1238 }
1239
1240 command_print(CMD, "stm32x unlocked.\n"
1241 "INFO: a reset or power cycle is required "
1242 "for the new settings to take effect.");
1243
1244 return ERROR_OK;
1245 }
1246
1247 COMMAND_HANDLER(stm32x_handle_options_read_command)
1248 {
1249 uint32_t optionbyte, protection;
1250 struct target *target = NULL;
1251 struct stm32x_flash_bank *stm32x_info = NULL;
1252
1253 if (CMD_ARGC < 1)
1254 return ERROR_COMMAND_SYNTAX_ERROR;
1255
1256 struct flash_bank *bank;
1257 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1258 if (ERROR_OK != retval)
1259 return retval;
1260
1261 stm32x_info = bank->driver_priv;
1262
1263 target = bank->target;
1264
1265 if (target->state != TARGET_HALTED) {
1266 LOG_ERROR("Target not halted");
1267 return ERROR_TARGET_NOT_HALTED;
1268 }
1269
1270 retval = stm32x_check_operation_supported(bank);
1271 if (ERROR_OK != retval)
1272 return retval;
1273
1274 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1275 if (retval != ERROR_OK)
1276 return retval;
1277
1278 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1279
1280 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1281 if (retval != ERROR_OK)
1282 return retval;
1283
1284 if (optionbyte & (1 << OPT_ERROR))
1285 command_print(CMD, "option byte complement error");
1286
1287 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1288 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1289
1290 command_print(CMD, "read protection: %s",
1291 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1292
1293 /* user option bytes are offset depending on variant */
1294 optionbyte >>= stm32x_info->option_offset;
1295
1296 command_print(CMD, "watchdog: %sware",
1297 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1298
1299 command_print(CMD, "stop mode: %sreset generated upon entry",
1300 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1301
1302 command_print(CMD, "standby mode: %sreset generated upon entry",
1303 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1304
1305 if (stm32x_info->has_dual_banks)
1306 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1307
1308 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1309
1310 return ERROR_OK;
1311 }
1312
1313 COMMAND_HANDLER(stm32x_handle_options_write_command)
1314 {
1315 struct target *target = NULL;
1316 struct stm32x_flash_bank *stm32x_info = NULL;
1317 uint8_t optionbyte;
1318 uint16_t useropt;
1319
1320 if (CMD_ARGC < 2)
1321 return ERROR_COMMAND_SYNTAX_ERROR;
1322
1323 struct flash_bank *bank;
1324 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1325 if (ERROR_OK != retval)
1326 return retval;
1327
1328 stm32x_info = bank->driver_priv;
1329
1330 target = bank->target;
1331
1332 if (target->state != TARGET_HALTED) {
1333 LOG_ERROR("Target not halted");
1334 return ERROR_TARGET_NOT_HALTED;
1335 }
1336
1337 retval = stm32x_check_operation_supported(bank);
1338 if (ERROR_OK != retval)
1339 return retval;
1340
1341 retval = stm32x_read_options(bank);
1342 if (ERROR_OK != retval)
1343 return retval;
1344
1345 /* start with current options */
1346 optionbyte = stm32x_info->option_bytes.user;
1347 useropt = stm32x_info->option_bytes.data;
1348
1349 /* skip over flash bank */
1350 CMD_ARGC--;
1351 CMD_ARGV++;
1352
1353 while (CMD_ARGC) {
1354 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1355 optionbyte |= (1 << 0);
1356 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1357 optionbyte &= ~(1 << 0);
1358 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1359 optionbyte |= (1 << 1);
1360 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1361 optionbyte &= ~(1 << 1);
1362 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1363 optionbyte |= (1 << 2);
1364 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1365 optionbyte &= ~(1 << 2);
1366 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1367 if (CMD_ARGC < 2)
1368 return ERROR_COMMAND_SYNTAX_ERROR;
1369 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1370 CMD_ARGC--;
1371 CMD_ARGV++;
1372 }
1373 else if (stm32x_info->has_dual_banks) {
1374 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1375 optionbyte |= (1 << 3);
1376 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1377 optionbyte &= ~(1 << 3);
1378 else
1379 return ERROR_COMMAND_SYNTAX_ERROR;
1380 } else
1381 return ERROR_COMMAND_SYNTAX_ERROR;
1382 CMD_ARGC--;
1383 CMD_ARGV++;
1384 }
1385
1386 if (stm32x_erase_options(bank) != ERROR_OK) {
1387 command_print(CMD, "stm32x failed to erase options");
1388 return ERROR_OK;
1389 }
1390
1391 stm32x_info->option_bytes.user = optionbyte;
1392 stm32x_info->option_bytes.data = useropt;
1393
1394 if (stm32x_write_options(bank) != ERROR_OK) {
1395 command_print(CMD, "stm32x failed to write options");
1396 return ERROR_OK;
1397 }
1398
1399 command_print(CMD, "stm32x write options complete.\n"
1400 "INFO: %spower cycle is required "
1401 "for the new settings to take effect.",
1402 stm32x_info->can_load_options
1403 ? "'stm32f1x options_load' command or " : "");
1404
1405 return ERROR_OK;
1406 }
1407
1408 COMMAND_HANDLER(stm32x_handle_options_load_command)
1409 {
1410 if (CMD_ARGC < 1)
1411 return ERROR_COMMAND_SYNTAX_ERROR;
1412
1413 struct flash_bank *bank;
1414 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1415 if (ERROR_OK != retval)
1416 return retval;
1417
1418 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1419
1420 if (!stm32x_info->can_load_options) {
1421 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1422 "required instead.");
1423 return ERROR_FAIL;
1424 }
1425
1426 struct target *target = bank->target;
1427
1428 if (target->state != TARGET_HALTED) {
1429 LOG_ERROR("Target not halted");
1430 return ERROR_TARGET_NOT_HALTED;
1431 }
1432
1433 retval = stm32x_check_operation_supported(bank);
1434 if (ERROR_OK != retval)
1435 return retval;
1436
1437 /* unlock option flash registers */
1438 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1439 if (retval != ERROR_OK)
1440 return retval;
1441 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1442 if (retval != ERROR_OK)
1443 return retval;
1444
1445 /* force re-load of option bytes - generates software reset */
1446 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1447 if (retval != ERROR_OK)
1448 return retval;
1449
1450 return ERROR_OK;
1451 }
1452
1453 static int stm32x_mass_erase(struct flash_bank *bank)
1454 {
1455 struct target *target = bank->target;
1456
1457 if (target->state != TARGET_HALTED) {
1458 LOG_ERROR("Target not halted");
1459 return ERROR_TARGET_NOT_HALTED;
1460 }
1461
1462 /* unlock option flash registers */
1463 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1464 if (retval != ERROR_OK)
1465 return retval;
1466 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1467 if (retval != ERROR_OK)
1468 return retval;
1469
1470 /* mass erase flash memory */
1471 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1472 if (retval != ERROR_OK)
1473 return retval;
1474 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1475 FLASH_MER | FLASH_STRT);
1476 if (retval != ERROR_OK)
1477 return retval;
1478
1479 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1480 if (retval != ERROR_OK)
1481 return retval;
1482
1483 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1484 if (retval != ERROR_OK)
1485 return retval;
1486
1487 return ERROR_OK;
1488 }
1489
1490 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1491 {
1492 if (CMD_ARGC < 1)
1493 return ERROR_COMMAND_SYNTAX_ERROR;
1494
1495 struct flash_bank *bank;
1496 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1497 if (ERROR_OK != retval)
1498 return retval;
1499
1500 retval = stm32x_mass_erase(bank);
1501 if (retval == ERROR_OK) {
1502 /* set all sectors as erased */
1503 for (int i = 0; i < bank->num_sectors; i++)
1504 bank->sectors[i].is_erased = 1;
1505
1506 command_print(CMD, "stm32x mass erase complete");
1507 } else
1508 command_print(CMD, "stm32x mass erase failed");
1509
1510 return retval;
1511 }
1512
1513 static const struct command_registration stm32x_exec_command_handlers[] = {
1514 {
1515 .name = "lock",
1516 .handler = stm32x_handle_lock_command,
1517 .mode = COMMAND_EXEC,
1518 .usage = "bank_id",
1519 .help = "Lock entire flash device.",
1520 },
1521 {
1522 .name = "unlock",
1523 .handler = stm32x_handle_unlock_command,
1524 .mode = COMMAND_EXEC,
1525 .usage = "bank_id",
1526 .help = "Unlock entire protected flash device.",
1527 },
1528 {
1529 .name = "mass_erase",
1530 .handler = stm32x_handle_mass_erase_command,
1531 .mode = COMMAND_EXEC,
1532 .usage = "bank_id",
1533 .help = "Erase entire flash device.",
1534 },
1535 {
1536 .name = "options_read",
1537 .handler = stm32x_handle_options_read_command,
1538 .mode = COMMAND_EXEC,
1539 .usage = "bank_id",
1540 .help = "Read and display device option bytes.",
1541 },
1542 {
1543 .name = "options_write",
1544 .handler = stm32x_handle_options_write_command,
1545 .mode = COMMAND_EXEC,
1546 .usage = "bank_id ('SWWDG'|'HWWDG') "
1547 "('RSTSTNDBY'|'NORSTSTNDBY') "
1548 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1549 .help = "Replace bits in device option bytes.",
1550 },
1551 {
1552 .name = "options_load",
1553 .handler = stm32x_handle_options_load_command,
1554 .mode = COMMAND_EXEC,
1555 .usage = "bank_id",
1556 .help = "Force re-load of device option bytes.",
1557 },
1558 COMMAND_REGISTRATION_DONE
1559 };
1560
1561 static const struct command_registration stm32x_command_handlers[] = {
1562 {
1563 .name = "stm32f1x",
1564 .mode = COMMAND_ANY,
1565 .help = "stm32f1x flash command group",
1566 .usage = "",
1567 .chain = stm32x_exec_command_handlers,
1568 },
1569 COMMAND_REGISTRATION_DONE
1570 };
1571
1572 const struct flash_driver stm32f1x_flash = {
1573 .name = "stm32f1x",
1574 .commands = stm32x_command_handlers,
1575 .flash_bank_command = stm32x_flash_bank_command,
1576 .erase = stm32x_erase,
1577 .protect = stm32x_protect,
1578 .write = stm32x_write,
1579 .read = default_flash_read,
1580 .probe = stm32x_probe,
1581 .auto_probe = stm32x_auto_probe,
1582 .erase_check = default_flash_blank_check,
1583 .protect_check = stm32x_protect_check,
1584 .info = get_stm32x_info,
1585 .free_driver_priv = default_flash_free_driver_priv,
1586 };
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