Code Review / openocd.git / blob
? search:


13affcda71589ba43dbb0b68ab2aba05c14b56ea
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35
36 /* stm32x register locations */
37
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
40
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
49
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
61
62 /* option byte location */
63
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
72
73 /* FLASH_CR register bits */
74
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
83
84 /* FLASH_SR register bits */
85
86 #define FLASH_BSY (1 << 0)
87 #define FLASH_PGERR (1 << 2)
88 #define FLASH_WRPRTERR (1 << 4)
89 #define FLASH_EOP (1 << 5)
90
91 /* STM32_FLASH_OBR bit definitions (reading) */
92
93 #define OPT_ERROR 0
94 #define OPT_READOUT 1
95 #define OPT_RDWDGSW 2
96 #define OPT_RDRSTSTOP 3
97 #define OPT_RDRSTSTDBY 4
98 #define OPT_BFB2 5 /* dual flash bank only */
99
100 /* register unlock keys */
101
102 #define KEY1 0x45670123
103 #define KEY2 0xCDEF89AB
104
105 /* timeout values */
106
107 #define FLASH_WRITE_TIMEOUT 10
108 #define FLASH_ERASE_TIMEOUT 100
109
110 struct stm32x_options {
111 uint16_t RDP;
112 uint16_t user_options;
113 uint16_t user_data;
114 uint16_t protection[4];
115 };
116
117 struct stm32x_flash_bank {
118 struct stm32x_options option_bytes;
119 int ppage_size;
120 int probed;
121
122 bool has_dual_banks;
123 /* used to access dual flash bank stm32xl */
124 uint32_t register_base;
125 uint16_t default_rdp;
126 int user_data_offset;
127 };
128
129 static int stm32x_mass_erase(struct flash_bank *bank);
130 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
131 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
132 uint32_t offset, uint32_t count);
133
134 /* flash bank stm32x <base> <size> 0 0 <target#>
135 */
136 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
137 {
138 struct stm32x_flash_bank *stm32x_info;
139
140 if (CMD_ARGC < 6)
141 return ERROR_COMMAND_SYNTAX_ERROR;
142
143 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
144
145 bank->driver_priv = stm32x_info;
146 stm32x_info->probed = 0;
147 stm32x_info->has_dual_banks = false;
148 stm32x_info->register_base = FLASH_REG_BASE_B0;
149
150 return ERROR_OK;
151 }
152
153 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
154 {
155 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
156 return reg + stm32x_info->register_base;
157 }
158
159 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
160 {
161 struct target *target = bank->target;
162 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
163 }
164
165 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
166 {
167 struct target *target = bank->target;
168 uint32_t status;
169 int retval = ERROR_OK;
170
171 /* wait for busy to clear */
172 for (;;) {
173 retval = stm32x_get_flash_status(bank, &status);
174 if (retval != ERROR_OK)
175 return retval;
176 LOG_DEBUG("status: 0x%" PRIx32 "", status);
177 if ((status & FLASH_BSY) == 0)
178 break;
179 if (timeout-- <= 0) {
180 LOG_ERROR("timed out waiting for flash");
181 return ERROR_FAIL;
182 }
183 alive_sleep(1);
184 }
185
186 if (status & FLASH_WRPRTERR) {
187 LOG_ERROR("stm32x device protected");
188 retval = ERROR_FAIL;
189 }
190
191 if (status & FLASH_PGERR) {
192 LOG_ERROR("stm32x device programming failed");
193 retval = ERROR_FAIL;
194 }
195
196 /* Clear but report errors */
197 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
198 /* If this operation fails, we ignore it and report the original
199 * retval
200 */
201 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
202 FLASH_WRPRTERR | FLASH_PGERR);
203 }
204 return retval;
205 }
206
207 int stm32x_check_operation_supported(struct flash_bank *bank)
208 {
209 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
210
211 /* if we have a dual flash bank device then
212 * we need to perform option byte stuff on bank0 only */
213 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
214 LOG_ERROR("Option Byte Operation's must use bank0");
215 return ERROR_FLASH_OPERATION_FAILED;
216 }
217
218 return ERROR_OK;
219 }
220
221 static int stm32x_read_options(struct flash_bank *bank)
222 {
223 uint32_t optiondata;
224 struct stm32x_flash_bank *stm32x_info = NULL;
225 struct target *target = bank->target;
226
227 stm32x_info = bank->driver_priv;
228
229 /* read current option bytes */
230 int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
231 if (retval != ERROR_OK)
232 return retval;
233
234 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF0 | ((optiondata >> 2) & 0x0f);
235 stm32x_info->option_bytes.user_data = (optiondata >> stm32x_info->user_data_offset) & 0xffff;
236 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
237
238 if (optiondata & (1 << OPT_READOUT))
239 LOG_INFO("Device Security Bit Set");
240
241 /* each bit refers to a 4bank protection */
242 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
243 if (retval != ERROR_OK)
244 return retval;
245
246 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
247 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
248 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
249 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
250
251 return ERROR_OK;
252 }
253
254 static int stm32x_erase_options(struct flash_bank *bank)
255 {
256 struct stm32x_flash_bank *stm32x_info = NULL;
257 struct target *target = bank->target;
258
259 stm32x_info = bank->driver_priv;
260
261 /* read current options */
262 stm32x_read_options(bank);
263
264 /* unlock flash registers */
265 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
266 if (retval != ERROR_OK)
267 return retval;
268
269 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
270 if (retval != ERROR_OK)
271 return retval;
272
273 /* unlock option flash registers */
274 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
275 if (retval != ERROR_OK)
276 return retval;
277 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
278 if (retval != ERROR_OK)
279 return retval;
280
281 /* erase option bytes */
282 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
283 if (retval != ERROR_OK)
284 return retval;
285 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
286 if (retval != ERROR_OK)
287 return retval;
288
289 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
290 if (retval != ERROR_OK)
291 return retval;
292
293 /* clear readout protection and complementary option bytes
294 * this will also force a device unlock if set */
295 stm32x_info->option_bytes.RDP = stm32x_info->default_rdp;
296
297 return ERROR_OK;
298 }
299
300 static int stm32x_write_options(struct flash_bank *bank)
301 {
302 struct stm32x_flash_bank *stm32x_info = NULL;
303 struct target *target = bank->target;
304
305 stm32x_info = bank->driver_priv;
306
307 /* unlock flash registers */
308 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
309 if (retval != ERROR_OK)
310 return retval;
311 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
312 if (retval != ERROR_OK)
313 return retval;
314
315 /* unlock option flash registers */
316 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
317 if (retval != ERROR_OK)
318 return retval;
319 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
320 if (retval != ERROR_OK)
321 return retval;
322
323 /* program option bytes */
324 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
325 if (retval != ERROR_OK)
326 return retval;
327
328 uint8_t opt_bytes[16];
329
330 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.RDP);
331 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user_options);
332 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.user_data & 0xff);
333 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.user_data >> 8) & 0xff);
334 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection[0]);
335 target_buffer_set_u16(target, opt_bytes + 10, stm32x_info->option_bytes.protection[1]);
336 target_buffer_set_u16(target, opt_bytes + 12, stm32x_info->option_bytes.protection[2]);
337 target_buffer_set_u16(target, opt_bytes + 14, stm32x_info->option_bytes.protection[3]);
338
339 uint32_t offset = STM32_OB_RDP - bank->base;
340 retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
341 if (retval != ERROR_OK) {
342 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
343 LOG_ERROR("working area required to erase options bytes");
344 return retval;
345 }
346
347 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
348 if (retval != ERROR_OK)
349 return retval;
350
351 return ERROR_OK;
352 }
353
354 static int stm32x_protect_check(struct flash_bank *bank)
355 {
356 struct target *target = bank->target;
357 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
358
359 uint32_t protection;
360 int i, s;
361 int num_bits;
362 int set;
363
364 if (target->state != TARGET_HALTED) {
365 LOG_ERROR("Target not halted");
366 return ERROR_TARGET_NOT_HALTED;
367 }
368
369 int retval = stm32x_check_operation_supported(bank);
370 if (ERROR_OK != retval)
371 return retval;
372
373 /* medium density - each bit refers to a 4bank protection
374 * high density - each bit refers to a 2bank protection */
375 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
376 if (retval != ERROR_OK)
377 return retval;
378
379 /* medium density - each protection bit is for 4 * 1K pages
380 * high density - each protection bit is for 2 * 2K pages */
381 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
382
383 if (stm32x_info->ppage_size == 2) {
384 /* high density flash/connectivity line protection */
385
386 set = 1;
387
388 if (protection & (1 << 31))
389 set = 0;
390
391 /* bit 31 controls sector 62 - 255 protection for high density
392 * bit 31 controls sector 62 - 127 protection for connectivity line */
393 for (s = 62; s < bank->num_sectors; s++)
394 bank->sectors[s].is_protected = set;
395
396 if (bank->num_sectors > 61)
397 num_bits = 31;
398
399 for (i = 0; i < num_bits; i++) {
400 set = 1;
401
402 if (protection & (1 << i))
403 set = 0;
404
405 for (s = 0; s < stm32x_info->ppage_size; s++)
406 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
407 }
408 } else {
409 /* low/medium density flash protection */
410 for (i = 0; i < num_bits; i++) {
411 set = 1;
412
413 if (protection & (1 << i))
414 set = 0;
415
416 for (s = 0; s < stm32x_info->ppage_size; s++)
417 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
418 }
419 }
420
421 return ERROR_OK;
422 }
423
424 static int stm32x_erase(struct flash_bank *bank, int first, int last)
425 {
426 struct target *target = bank->target;
427 int i;
428
429 if (bank->target->state != TARGET_HALTED) {
430 LOG_ERROR("Target not halted");
431 return ERROR_TARGET_NOT_HALTED;
432 }
433
434 if ((first == 0) && (last == (bank->num_sectors - 1)))
435 return stm32x_mass_erase(bank);
436
437 /* unlock flash registers */
438 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
439 if (retval != ERROR_OK)
440 return retval;
441 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
442 if (retval != ERROR_OK)
443 return retval;
444
445 for (i = first; i <= last; i++) {
446 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
447 if (retval != ERROR_OK)
448 return retval;
449 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
450 bank->base + bank->sectors[i].offset);
451 if (retval != ERROR_OK)
452 return retval;
453 retval = target_write_u32(target,
454 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
455 if (retval != ERROR_OK)
456 return retval;
457
458 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
459 if (retval != ERROR_OK)
460 return retval;
461
462 bank->sectors[i].is_erased = 1;
463 }
464
465 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
466 if (retval != ERROR_OK)
467 return retval;
468
469 return ERROR_OK;
470 }
471
472 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
473 {
474 struct stm32x_flash_bank *stm32x_info = NULL;
475 struct target *target = bank->target;
476 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
477 int i, reg, bit;
478 int status;
479 uint32_t protection;
480
481 stm32x_info = bank->driver_priv;
482
483 if (target->state != TARGET_HALTED) {
484 LOG_ERROR("Target not halted");
485 return ERROR_TARGET_NOT_HALTED;
486 }
487
488 int retval = stm32x_check_operation_supported(bank);
489 if (ERROR_OK != retval)
490 return retval;
491
492 if ((first % stm32x_info->ppage_size) != 0) {
493 LOG_WARNING("aligned start protect sector to a %d sector boundary",
494 stm32x_info->ppage_size);
495 first = first - (first % stm32x_info->ppage_size);
496 }
497 if (((last + 1) % stm32x_info->ppage_size) != 0) {
498 LOG_WARNING("aligned end protect sector to a %d sector boundary",
499 stm32x_info->ppage_size);
500 last++;
501 last = last - (last % stm32x_info->ppage_size);
502 last--;
503 }
504
505 /* medium density - each bit refers to a 4bank protection
506 * high density - each bit refers to a 2bank protection */
507 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
508 if (retval != ERROR_OK)
509 return retval;
510
511 prot_reg[0] = (uint16_t)protection;
512 prot_reg[1] = (uint16_t)(protection >> 8);
513 prot_reg[2] = (uint16_t)(protection >> 16);
514 prot_reg[3] = (uint16_t)(protection >> 24);
515
516 if (stm32x_info->ppage_size == 2) {
517 /* high density flash */
518
519 /* bit 7 controls sector 62 - 255 protection */
520 if (last > 61) {
521 if (set)
522 prot_reg[3] &= ~(1 << 7);
523 else
524 prot_reg[3] |= (1 << 7);
525 }
526
527 if (first > 61)
528 first = 62;
529 if (last > 61)
530 last = 61;
531
532 for (i = first; i <= last; i++) {
533 reg = (i / stm32x_info->ppage_size) / 8;
534 bit = (i / stm32x_info->ppage_size) - (reg * 8);
535
536 if (set)
537 prot_reg[reg] &= ~(1 << bit);
538 else
539 prot_reg[reg] |= (1 << bit);
540 }
541 } else {
542 /* medium density flash */
543 for (i = first; i <= last; i++) {
544 reg = (i / stm32x_info->ppage_size) / 8;
545 bit = (i / stm32x_info->ppage_size) - (reg * 8);
546
547 if (set)
548 prot_reg[reg] &= ~(1 << bit);
549 else
550 prot_reg[reg] |= (1 << bit);
551 }
552 }
553
554 status = stm32x_erase_options(bank);
555 if (status != ERROR_OK)
556 return status;
557
558 stm32x_info->option_bytes.protection[0] = prot_reg[0];
559 stm32x_info->option_bytes.protection[1] = prot_reg[1];
560 stm32x_info->option_bytes.protection[2] = prot_reg[2];
561 stm32x_info->option_bytes.protection[3] = prot_reg[3];
562
563 return stm32x_write_options(bank);
564 }
565
566 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
567 uint32_t offset, uint32_t count)
568 {
569 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
570 struct target *target = bank->target;
571 uint32_t buffer_size = 16384;
572 struct working_area *write_algorithm;
573 struct working_area *source;
574 uint32_t address = bank->base + offset;
575 struct reg_param reg_params[5];
576 struct armv7m_algorithm armv7m_info;
577 int retval = ERROR_OK;
578
579 /* see contrib/loaders/flash/stm32f1x.S for src */
580
581 static const uint8_t stm32x_flash_write_code[] = {
582 /* #define STM32_FLASH_SR_OFFSET 0x0C */
583 /* wait_fifo: */
584 0x16, 0x68, /* ldr r6, [r2, #0] */
585 0x00, 0x2e, /* cmp r6, #0 */
586 0x18, 0xd0, /* beq exit */
587 0x55, 0x68, /* ldr r5, [r2, #4] */
588 0xb5, 0x42, /* cmp r5, r6 */
589 0xf9, 0xd0, /* beq wait_fifo */
590 0x2e, 0x88, /* ldrh r6, [r5, #0] */
591 0x26, 0x80, /* strh r6, [r4, #0] */
592 0x02, 0x35, /* adds r5, #2 */
593 0x02, 0x34, /* adds r4, #2 */
594 /* busy: */
595 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
596 0x01, 0x27, /* movs r7, #1 */
597 0x3e, 0x42, /* tst r6, r7 */
598 0xfb, 0xd1, /* bne busy */
599 0x14, 0x27, /* movs r7, #0x14 */
600 0x3e, 0x42, /* tst r6, r7 */
601 0x08, 0xd1, /* bne error */
602 0x9d, 0x42, /* cmp r5, r3 */
603 0x01, 0xd3, /* bcc no_wrap */
604 0x15, 0x46, /* mov r5, r2 */
605 0x08, 0x35, /* adds r5, #8 */
606 /* no_wrap: */
607 0x55, 0x60, /* str r5, [r2, #4] */
608 0x01, 0x39, /* subs r1, r1, #1 */
609 0x00, 0x29, /* cmp r1, #0 */
610 0x02, 0xd0, /* beq exit */
611 0xe5, 0xe7, /* b wait_fifo */
612 /* error: */
613 0x00, 0x20, /* movs r0, #0 */
614 0x50, 0x60, /* str r0, [r2, #4] */
615 /* exit: */
616 0x30, 0x46, /* mov r0, r6 */
617 0x00, 0xbe, /* bkpt #0 */
618 };
619
620 /* flash write code */
621 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
622 &write_algorithm) != ERROR_OK) {
623 LOG_WARNING("no working area available, can't do block memory writes");
624 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
625 };
626
627 retval = target_write_buffer(target, write_algorithm->address,
628 sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
629 if (retval != ERROR_OK)
630 return retval;
631
632 /* memory buffer */
633 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
634 buffer_size /= 2;
635 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
636 if (buffer_size <= 256) {
637 /* we already allocated the writing code, but failed to get a
638 * buffer, free the algorithm */
639 target_free_working_area(target, write_algorithm);
640
641 LOG_WARNING("no large enough working area available, can't do block memory writes");
642 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
643 }
644 };
645
646 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
647 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
648 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
649 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
650 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
651
652 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
653 buf_set_u32(reg_params[1].value, 0, 32, count);
654 buf_set_u32(reg_params[2].value, 0, 32, source->address);
655 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
656 buf_set_u32(reg_params[4].value, 0, 32, address);
657
658 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
659 armv7m_info.core_mode = ARM_MODE_THREAD;
660
661 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
662 0, NULL,
663 5, reg_params,
664 source->address, source->size,
665 write_algorithm->address, 0,
666 &armv7m_info);
667
668 if (retval == ERROR_FLASH_OPERATION_FAILED) {
669 LOG_ERROR("flash write failed at address 0x%"PRIx32,
670 buf_get_u32(reg_params[4].value, 0, 32));
671
672 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
673 LOG_ERROR("flash memory not erased before writing");
674 /* Clear but report errors */
675 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
676 }
677
678 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
679 LOG_ERROR("flash memory write protected");
680 /* Clear but report errors */
681 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
682 }
683 }
684
685 target_free_working_area(target, source);
686 target_free_working_area(target, write_algorithm);
687
688 destroy_reg_param(&reg_params[0]);
689 destroy_reg_param(&reg_params[1]);
690 destroy_reg_param(&reg_params[2]);
691 destroy_reg_param(&reg_params[3]);
692 destroy_reg_param(&reg_params[4]);
693
694 return retval;
695 }
696
697 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
698 uint32_t offset, uint32_t count)
699 {
700 struct target *target = bank->target;
701 uint8_t *new_buffer = NULL;
702
703 if (bank->target->state != TARGET_HALTED) {
704 LOG_ERROR("Target not halted");
705 return ERROR_TARGET_NOT_HALTED;
706 }
707
708 if (offset & 0x1) {
709 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
710 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
711 }
712
713 /* If there's an odd number of bytes, the data has to be padded. Duplicate
714 * the buffer and use the normal code path with a single block write since
715 * it's probably cheaper than to special case the last odd write using
716 * discrete accesses. */
717 if (count & 1) {
718 new_buffer = malloc(count + 1);
719 if (new_buffer == NULL) {
720 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
721 return ERROR_FAIL;
722 }
723 LOG_INFO("odd number of bytes to write, padding with 0xff");
724 buffer = memcpy(new_buffer, buffer, count);
725 buffer[count++] = 0xff;
726 }
727
728 uint32_t words_remaining = count / 2;
729 int retval, retval2;
730
731 /* unlock flash registers */
732 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
733 if (retval != ERROR_OK)
734 goto cleanup;
735 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
736 if (retval != ERROR_OK)
737 goto cleanup;
738
739 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
740 if (retval != ERROR_OK)
741 goto cleanup;
742
743 /* try using a block write */
744 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
745
746 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
747 /* if block write failed (no sufficient working area),
748 * we use normal (slow) single halfword accesses */
749 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
750
751 while (words_remaining > 0) {
752 uint16_t value;
753 memcpy(&value, buffer, sizeof(uint16_t));
754
755 retval = target_write_u16(target, bank->base + offset, value);
756 if (retval != ERROR_OK)
757 goto reset_pg_and_lock;
758
759 retval = stm32x_wait_status_busy(bank, 5);
760 if (retval != ERROR_OK)
761 goto reset_pg_and_lock;
762
763 words_remaining--;
764 buffer += 2;
765 offset += 2;
766 }
767 }
768
769 reset_pg_and_lock:
770 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
771 if (retval == ERROR_OK)
772 retval = retval2;
773
774 cleanup:
775 if (new_buffer)
776 free(new_buffer);
777
778 return retval;
779 }
780
781 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
782 {
783 /* This check the device CPUID core register to detect
784 * the M0 from the M3 devices. */
785
786 struct target *target = bank->target;
787 uint32_t cpuid, device_id_register = 0;
788
789 /* Get the CPUID from the ARM Core
790 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
791 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
792 if (retval != ERROR_OK)
793 return retval;
794
795 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
796 /* 0xC20 is M0 devices */
797 device_id_register = 0x40015800;
798 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
799 /* 0xC23 is M3 devices */
800 device_id_register = 0xE0042000;
801 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
802 /* 0xC24 is M4 devices */
803 device_id_register = 0xE0042000;
804 } else {
805 LOG_ERROR("Cannot identify target as a stm32x");
806 return ERROR_FAIL;
807 }
808
809 /* read stm32 device id register */
810 retval = target_read_u32(target, device_id_register, device_id);
811 if (retval != ERROR_OK)
812 return retval;
813
814 return retval;
815 }
816
817 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
818 {
819 struct target *target = bank->target;
820 uint32_t cpuid, flash_size_reg;
821
822 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
823 if (retval != ERROR_OK)
824 return retval;
825
826 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
827 /* 0xC20 is M0 devices */
828 flash_size_reg = 0x1FFFF7CC;
829 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
830 /* 0xC23 is M3 devices */
831 flash_size_reg = 0x1FFFF7E0;
832 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
833 /* 0xC24 is M4 devices */
834 flash_size_reg = 0x1FFFF7CC;
835 } else {
836 LOG_ERROR("Cannot identify target as a stm32x");
837 return ERROR_FAIL;
838 }
839
840 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
841 if (retval != ERROR_OK)
842 return retval;
843
844 return retval;
845 }
846
847 static int stm32x_probe(struct flash_bank *bank)
848 {
849 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
850 int i;
851 uint16_t flash_size_in_kb;
852 uint16_t max_flash_size_in_kb;
853 uint32_t device_id;
854 int page_size;
855 uint32_t base_address = 0x08000000;
856
857 stm32x_info->probed = 0;
858 stm32x_info->register_base = FLASH_REG_BASE_B0;
859 stm32x_info->user_data_offset = 10;
860
861 /* default factory protection level */
862 stm32x_info->default_rdp = 0x5AA5;
863
864 /* read stm32 device id register */
865 int retval = stm32x_get_device_id(bank, &device_id);
866 if (retval != ERROR_OK)
867 return retval;
868
869 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
870
871 /* set page size, protection granularity and max flash size depending on family */
872 switch (device_id & 0xfff) {
873 case 0x410: /* medium density */
874 page_size = 1024;
875 stm32x_info->ppage_size = 4;
876 max_flash_size_in_kb = 128;
877 break;
878 case 0x412: /* low density */
879 page_size = 1024;
880 stm32x_info->ppage_size = 4;
881 max_flash_size_in_kb = 32;
882 break;
883 case 0x414: /* high density */
884 page_size = 2048;
885 stm32x_info->ppage_size = 2;
886 max_flash_size_in_kb = 512;
887 break;
888 case 0x418: /* connectivity line density */
889 page_size = 2048;
890 stm32x_info->ppage_size = 2;
891 max_flash_size_in_kb = 256;
892 break;
893 case 0x420: /* value line density */
894 page_size = 1024;
895 stm32x_info->ppage_size = 4;
896 max_flash_size_in_kb = 128;
897 break;
898 case 0x422: /* stm32f30x */
899 page_size = 2048;
900 stm32x_info->ppage_size = 2;
901 max_flash_size_in_kb = 256;
902 stm32x_info->user_data_offset = 16;
903 stm32x_info->default_rdp = 0x55AA;
904 break;
905 case 0x428: /* value line High density */
906 page_size = 2048;
907 stm32x_info->ppage_size = 4;
908 max_flash_size_in_kb = 128;
909 break;
910 case 0x430: /* xl line density (dual flash banks) */
911 page_size = 2048;
912 stm32x_info->ppage_size = 2;
913 max_flash_size_in_kb = 1024;
914 stm32x_info->has_dual_banks = true;
915 break;
916 case 0x432: /* stm32f37x */
917 page_size = 2048;
918 stm32x_info->ppage_size = 2;
919 max_flash_size_in_kb = 256;
920 stm32x_info->user_data_offset = 16;
921 stm32x_info->default_rdp = 0x55AA;
922 break;
923 case 0x440: /* stm32f0x */
924 page_size = 1024;
925 stm32x_info->ppage_size = 4;
926 max_flash_size_in_kb = 64;
927 stm32x_info->user_data_offset = 16;
928 stm32x_info->default_rdp = 0x55AA;
929 break;
930 default:
931 LOG_WARNING("Cannot identify target as a STM32 family.");
932 return ERROR_FAIL;
933 }
934
935 /* get flash size from target. */
936 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
937
938 /* failed reading flash size or flash size invalid (early silicon),
939 * default to max target family */
940 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
941 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
942 max_flash_size_in_kb);
943 flash_size_in_kb = max_flash_size_in_kb;
944 }
945
946 if (stm32x_info->has_dual_banks) {
947 /* split reported size into matching bank */
948 if (bank->base != 0x08080000) {
949 /* bank 0 will be fixed 512k */
950 flash_size_in_kb = 512;
951 } else {
952 flash_size_in_kb -= 512;
953 /* bank1 also uses a register offset */
954 stm32x_info->register_base = FLASH_REG_BASE_B1;
955 base_address = 0x08080000;
956 }
957 }
958
959 /* if the user sets the size manually then ignore the probed value
960 * this allows us to work around devices that have a invalid flash size register value */
961 if (bank->size) {
962 LOG_INFO("ignoring flash probed value, using configured bank size");
963 flash_size_in_kb = bank->size / 1024;
964 }
965
966 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
967
968 /* did we assign flash size? */
969 assert(flash_size_in_kb != 0xffff);
970
971 /* calculate numbers of pages */
972 int num_pages = flash_size_in_kb * 1024 / page_size;
973
974 /* check that calculation result makes sense */
975 assert(num_pages > 0);
976
977 if (bank->sectors) {
978 free(bank->sectors);
979 bank->sectors = NULL;
980 }
981
982 bank->base = base_address;
983 bank->size = (num_pages * page_size);
984 bank->num_sectors = num_pages;
985 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
986
987 for (i = 0; i < num_pages; i++) {
988 bank->sectors[i].offset = i * page_size;
989 bank->sectors[i].size = page_size;
990 bank->sectors[i].is_erased = -1;
991 bank->sectors[i].is_protected = 1;
992 }
993
994 stm32x_info->probed = 1;
995
996 return ERROR_OK;
997 }
998
999 static int stm32x_auto_probe(struct flash_bank *bank)
1000 {
1001 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1002 if (stm32x_info->probed)
1003 return ERROR_OK;
1004 return stm32x_probe(bank);
1005 }
1006
1007 #if 0
1008 COMMAND_HANDLER(stm32x_handle_part_id_command)
1009 {
1010 return ERROR_OK;
1011 }
1012 #endif
1013
1014 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1015 {
1016 uint32_t device_id;
1017 int printed;
1018
1019 /* read stm32 device id register */
1020 int retval = stm32x_get_device_id(bank, &device_id);
1021 if (retval != ERROR_OK)
1022 return retval;
1023
1024 if ((device_id & 0xfff) == 0x410) {
1025 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1026 buf += printed;
1027 buf_size -= printed;
1028
1029 switch (device_id >> 16) {
1030 case 0x0000:
1031 snprintf(buf, buf_size, "A");
1032 break;
1033
1034 case 0x2000:
1035 snprintf(buf, buf_size, "B");
1036 break;
1037
1038 case 0x2001:
1039 snprintf(buf, buf_size, "Z");
1040 break;
1041
1042 case 0x2003:
1043 snprintf(buf, buf_size, "Y");
1044 break;
1045
1046 default:
1047 snprintf(buf, buf_size, "unknown");
1048 break;
1049 }
1050 } else if ((device_id & 0xfff) == 0x412) {
1051 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1052 buf += printed;
1053 buf_size -= printed;
1054
1055 switch (device_id >> 16) {
1056 case 0x1000:
1057 snprintf(buf, buf_size, "A");
1058 break;
1059
1060 default:
1061 snprintf(buf, buf_size, "unknown");
1062 break;
1063 }
1064 } else if ((device_id & 0xfff) == 0x414) {
1065 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1066 buf += printed;
1067 buf_size -= printed;
1068
1069 switch (device_id >> 16) {
1070 case 0x1000:
1071 snprintf(buf, buf_size, "A");
1072 break;
1073
1074 case 0x1001:
1075 snprintf(buf, buf_size, "Z");
1076 break;
1077
1078 default:
1079 snprintf(buf, buf_size, "unknown");
1080 break;
1081 }
1082 } else if ((device_id & 0xfff) == 0x418) {
1083 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1084 buf += printed;
1085 buf_size -= printed;
1086
1087 switch (device_id >> 16) {
1088 case 0x1000:
1089 snprintf(buf, buf_size, "A");
1090 break;
1091
1092 case 0x1001:
1093 snprintf(buf, buf_size, "Z");
1094 break;
1095
1096 default:
1097 snprintf(buf, buf_size, "unknown");
1098 break;
1099 }
1100 } else if ((device_id & 0xfff) == 0x420) {
1101 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1102 buf += printed;
1103 buf_size -= printed;
1104
1105 switch (device_id >> 16) {
1106 case 0x1000:
1107 snprintf(buf, buf_size, "A");
1108 break;
1109
1110 case 0x1001:
1111 snprintf(buf, buf_size, "Z");
1112 break;
1113
1114 default:
1115 snprintf(buf, buf_size, "unknown");
1116 break;
1117 }
1118 } else if ((device_id & 0xfff) == 0x422) {
1119 printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
1120 buf += printed;
1121 buf_size -= printed;
1122
1123 switch (device_id >> 16) {
1124 case 0x1000:
1125 snprintf(buf, buf_size, "A");
1126 break;
1127
1128 case 0x1001:
1129 snprintf(buf, buf_size, "Z");
1130 break;
1131
1132 case 0x2000:
1133 snprintf(buf, buf_size, "B");
1134 break;
1135
1136 default:
1137 snprintf(buf, buf_size, "unknown");
1138 break;
1139 }
1140 } else if ((device_id & 0xfff) == 0x428) {
1141 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1142 buf += printed;
1143 buf_size -= printed;
1144
1145 switch (device_id >> 16) {
1146 case 0x1000:
1147 snprintf(buf, buf_size, "A");
1148 break;
1149
1150 case 0x1001:
1151 snprintf(buf, buf_size, "Z");
1152 break;
1153
1154 default:
1155 snprintf(buf, buf_size, "unknown");
1156 break;
1157 }
1158 } else if ((device_id & 0xfff) == 0x430) {
1159 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1160 buf += printed;
1161 buf_size -= printed;
1162
1163 switch (device_id >> 16) {
1164 case 0x1000:
1165 snprintf(buf, buf_size, "A");
1166 break;
1167
1168 default:
1169 snprintf(buf, buf_size, "unknown");
1170 break;
1171 }
1172 } else if ((device_id & 0xfff) == 0x432) {
1173 printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
1174 buf += printed;
1175 buf_size -= printed;
1176
1177 switch (device_id >> 16) {
1178 case 0x1000:
1179 snprintf(buf, buf_size, "A");
1180 break;
1181
1182 case 0x2000:
1183 snprintf(buf, buf_size, "B");
1184 break;
1185
1186 default:
1187 snprintf(buf, buf_size, "unknown");
1188 break;
1189 }
1190 } else if ((device_id & 0xfff) == 0x440) {
1191 printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
1192 buf += printed;
1193 buf_size -= printed;
1194
1195 switch (device_id >> 16) {
1196 case 0x1000:
1197 snprintf(buf, buf_size, "1.0");
1198 break;
1199
1200 case 0x2000:
1201 snprintf(buf, buf_size, "2.0");
1202 break;
1203
1204 default:
1205 snprintf(buf, buf_size, "unknown");
1206 break;
1207 }
1208 } else {
1209 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1210 return ERROR_FAIL;
1211 }
1212
1213 return ERROR_OK;
1214 }
1215
1216 COMMAND_HANDLER(stm32x_handle_lock_command)
1217 {
1218 struct target *target = NULL;
1219 struct stm32x_flash_bank *stm32x_info = NULL;
1220
1221 if (CMD_ARGC < 1)
1222 return ERROR_COMMAND_SYNTAX_ERROR;
1223
1224 struct flash_bank *bank;
1225 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1226 if (ERROR_OK != retval)
1227 return retval;
1228
1229 stm32x_info = bank->driver_priv;
1230
1231 target = bank->target;
1232
1233 if (target->state != TARGET_HALTED) {
1234 LOG_ERROR("Target not halted");
1235 return ERROR_TARGET_NOT_HALTED;
1236 }
1237
1238 retval = stm32x_check_operation_supported(bank);
1239 if (ERROR_OK != retval)
1240 return retval;
1241
1242 if (stm32x_erase_options(bank) != ERROR_OK) {
1243 command_print(CMD_CTX, "stm32x failed to erase options");
1244 return ERROR_OK;
1245 }
1246
1247 /* set readout protection */
1248 stm32x_info->option_bytes.RDP = 0;
1249
1250 if (stm32x_write_options(bank) != ERROR_OK) {
1251 command_print(CMD_CTX, "stm32x failed to lock device");
1252 return ERROR_OK;
1253 }
1254
1255 command_print(CMD_CTX, "stm32x locked");
1256
1257 return ERROR_OK;
1258 }
1259
1260 COMMAND_HANDLER(stm32x_handle_unlock_command)
1261 {
1262 struct target *target = NULL;
1263
1264 if (CMD_ARGC < 1)
1265 return ERROR_COMMAND_SYNTAX_ERROR;
1266
1267 struct flash_bank *bank;
1268 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1269 if (ERROR_OK != retval)
1270 return retval;
1271
1272 target = bank->target;
1273
1274 if (target->state != TARGET_HALTED) {
1275 LOG_ERROR("Target not halted");
1276 return ERROR_TARGET_NOT_HALTED;
1277 }
1278
1279 retval = stm32x_check_operation_supported(bank);
1280 if (ERROR_OK != retval)
1281 return retval;
1282
1283 if (stm32x_erase_options(bank) != ERROR_OK) {
1284 command_print(CMD_CTX, "stm32x failed to unlock device");
1285 return ERROR_OK;
1286 }
1287
1288 if (stm32x_write_options(bank) != ERROR_OK) {
1289 command_print(CMD_CTX, "stm32x failed to lock device");
1290 return ERROR_OK;
1291 }
1292
1293 command_print(CMD_CTX, "stm32x unlocked.\n"
1294 "INFO: a reset or power cycle is required "
1295 "for the new settings to take effect.");
1296
1297 return ERROR_OK;
1298 }
1299
1300 COMMAND_HANDLER(stm32x_handle_options_read_command)
1301 {
1302 uint32_t optionbyte;
1303 struct target *target = NULL;
1304 struct stm32x_flash_bank *stm32x_info = NULL;
1305
1306 if (CMD_ARGC < 1)
1307 return ERROR_COMMAND_SYNTAX_ERROR;
1308
1309 struct flash_bank *bank;
1310 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1311 if (ERROR_OK != retval)
1312 return retval;
1313
1314 stm32x_info = bank->driver_priv;
1315
1316 target = bank->target;
1317
1318 if (target->state != TARGET_HALTED) {
1319 LOG_ERROR("Target not halted");
1320 return ERROR_TARGET_NOT_HALTED;
1321 }
1322
1323 retval = stm32x_check_operation_supported(bank);
1324 if (ERROR_OK != retval)
1325 return retval;
1326
1327 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1328 if (retval != ERROR_OK)
1329 return retval;
1330 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1331
1332 if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
1333 command_print(CMD_CTX, "Option Byte Complement Error");
1334
1335 if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
1336 command_print(CMD_CTX, "Readout Protection On");
1337 else
1338 command_print(CMD_CTX, "Readout Protection Off");
1339
1340 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
1341 command_print(CMD_CTX, "Software Watchdog");
1342 else
1343 command_print(CMD_CTX, "Hardware Watchdog");
1344
1345 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
1346 command_print(CMD_CTX, "Stop: No reset generated");
1347 else
1348 command_print(CMD_CTX, "Stop: Reset generated");
1349
1350 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
1351 command_print(CMD_CTX, "Standby: No reset generated");
1352 else
1353 command_print(CMD_CTX, "Standby: Reset generated");
1354
1355 if (stm32x_info->has_dual_banks) {
1356 if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
1357 command_print(CMD_CTX, "Boot: Bank 0");
1358 else
1359 command_print(CMD_CTX, "Boot: Bank 1");
1360 }
1361
1362 command_print(CMD_CTX, "User Option0: 0x%02" PRIx8,
1363 (optionbyte >> stm32x_info->user_data_offset) & 0xff);
1364 command_print(CMD_CTX, "User Option1: 0x%02" PRIx8,
1365 (optionbyte >> (stm32x_info->user_data_offset + 8)) & 0xff);
1366
1367 return ERROR_OK;
1368 }
1369
1370 COMMAND_HANDLER(stm32x_handle_options_write_command)
1371 {
1372 struct target *target = NULL;
1373 struct stm32x_flash_bank *stm32x_info = NULL;
1374 uint16_t optionbyte;
1375
1376 if (CMD_ARGC < 2)
1377 return ERROR_COMMAND_SYNTAX_ERROR;
1378
1379 struct flash_bank *bank;
1380 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1381 if (ERROR_OK != retval)
1382 return retval;
1383
1384 stm32x_info = bank->driver_priv;
1385
1386 target = bank->target;
1387
1388 if (target->state != TARGET_HALTED) {
1389 LOG_ERROR("Target not halted");
1390 return ERROR_TARGET_NOT_HALTED;
1391 }
1392
1393 retval = stm32x_check_operation_supported(bank);
1394 if (ERROR_OK != retval)
1395 return retval;
1396
1397 retval = stm32x_read_options(bank);
1398 if (ERROR_OK != retval)
1399 return retval;
1400
1401 /* start with current options */
1402 optionbyte = stm32x_info->option_bytes.user_options;
1403
1404 /* skip over flash bank */
1405 CMD_ARGC--;
1406 CMD_ARGV++;
1407
1408 while (CMD_ARGC) {
1409 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1410 optionbyte |= (1 << 0);
1411 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1412 optionbyte &= ~(1 << 0);
1413 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1414 optionbyte &= ~(1 << 1);
1415 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1416 optionbyte &= ~(1 << 1);
1417 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1418 optionbyte &= ~(1 << 2);
1419 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1420 optionbyte &= ~(1 << 2);
1421 else if (stm32x_info->has_dual_banks) {
1422 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1423 optionbyte |= (1 << 3);
1424 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1425 optionbyte &= ~(1 << 3);
1426 else
1427 return ERROR_COMMAND_SYNTAX_ERROR;
1428 } else
1429 return ERROR_COMMAND_SYNTAX_ERROR;
1430 CMD_ARGC--;
1431 CMD_ARGV++;
1432 }
1433
1434 if (stm32x_erase_options(bank) != ERROR_OK) {
1435 command_print(CMD_CTX, "stm32x failed to erase options");
1436 return ERROR_OK;
1437 }
1438
1439 stm32x_info->option_bytes.user_options = optionbyte;
1440
1441 if (stm32x_write_options(bank) != ERROR_OK) {
1442 command_print(CMD_CTX, "stm32x failed to write options");
1443 return ERROR_OK;
1444 }
1445
1446 command_print(CMD_CTX, "stm32x write options complete.\n"
1447 "INFO: a reset or power cycle is required "
1448 "for the new settings to take effect.");
1449
1450 return ERROR_OK;
1451 }
1452
1453 static int stm32x_mass_erase(struct flash_bank *bank)
1454 {
1455 struct target *target = bank->target;
1456
1457 if (target->state != TARGET_HALTED) {
1458 LOG_ERROR("Target not halted");
1459 return ERROR_TARGET_NOT_HALTED;
1460 }
1461
1462 /* unlock option flash registers */
1463 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1464 if (retval != ERROR_OK)
1465 return retval;
1466 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1467 if (retval != ERROR_OK)
1468 return retval;
1469
1470 /* mass erase flash memory */
1471 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1472 if (retval != ERROR_OK)
1473 return retval;
1474 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1475 FLASH_MER | FLASH_STRT);
1476 if (retval != ERROR_OK)
1477 return retval;
1478
1479 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1480 if (retval != ERROR_OK)
1481 return retval;
1482
1483 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1484 if (retval != ERROR_OK)
1485 return retval;
1486
1487 return ERROR_OK;
1488 }
1489
1490 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1491 {
1492 int i;
1493
1494 if (CMD_ARGC < 1)
1495 return ERROR_COMMAND_SYNTAX_ERROR;
1496
1497 struct flash_bank *bank;
1498 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1499 if (ERROR_OK != retval)
1500 return retval;
1501
1502 retval = stm32x_mass_erase(bank);
1503 if (retval == ERROR_OK) {
1504 /* set all sectors as erased */
1505 for (i = 0; i < bank->num_sectors; i++)
1506 bank->sectors[i].is_erased = 1;
1507
1508 command_print(CMD_CTX, "stm32x mass erase complete");
1509 } else
1510 command_print(CMD_CTX, "stm32x mass erase failed");
1511
1512 return retval;
1513 }
1514
1515 static const struct command_registration stm32x_exec_command_handlers[] = {
1516 {
1517 .name = "lock",
1518 .handler = stm32x_handle_lock_command,
1519 .mode = COMMAND_EXEC,
1520 .usage = "bank_id",
1521 .help = "Lock entire flash device.",
1522 },
1523 {
1524 .name = "unlock",
1525 .handler = stm32x_handle_unlock_command,
1526 .mode = COMMAND_EXEC,
1527 .usage = "bank_id",
1528 .help = "Unlock entire protected flash device.",
1529 },
1530 {
1531 .name = "mass_erase",
1532 .handler = stm32x_handle_mass_erase_command,
1533 .mode = COMMAND_EXEC,
1534 .usage = "bank_id",
1535 .help = "Erase entire flash device.",
1536 },
1537 {
1538 .name = "options_read",
1539 .handler = stm32x_handle_options_read_command,
1540 .mode = COMMAND_EXEC,
1541 .usage = "bank_id",
1542 .help = "Read and display device option byte.",
1543 },
1544 {
1545 .name = "options_write",
1546 .handler = stm32x_handle_options_write_command,
1547 .mode = COMMAND_EXEC,
1548 .usage = "bank_id ('SWWDG'|'HWWDG') "
1549 "('RSTSTNDBY'|'NORSTSTNDBY') "
1550 "('RSTSTOP'|'NORSTSTOP')",
1551 .help = "Replace bits in device option byte.",
1552 },
1553 COMMAND_REGISTRATION_DONE
1554 };
1555
1556 static const struct command_registration stm32x_command_handlers[] = {
1557 {
1558 .name = "stm32f1x",
1559 .mode = COMMAND_ANY,
1560 .help = "stm32f1x flash command group",
1561 .usage = "",
1562 .chain = stm32x_exec_command_handlers,
1563 },
1564 COMMAND_REGISTRATION_DONE
1565 };
1566
1567 struct flash_driver stm32f1x_flash = {
1568 .name = "stm32f1x",
1569 .commands = stm32x_command_handlers,
1570 .flash_bank_command = stm32x_flash_bank_command,
1571 .erase = stm32x_erase,
1572 .protect = stm32x_protect,
1573 .write = stm32x_write,
1574 .read = default_flash_read,
1575 .probe = stm32x_probe,
1576 .auto_probe = stm32x_auto_probe,
1577 .erase_check = default_flash_blank_check,
1578 .protect_check = stm32x_protect_check,
1579 .info = get_stm32x_info,
1580 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)