1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
24 /***************************************************************************
25 * STELLARIS is tested on LM3S811, LM3S6965
26 ***************************************************************************/
32 #include "stellaris.h"
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
37 #define DID0_VER(did0) ((did0 >> 28)&0x07)
39 static int stellaris_read_part_info(struct flash_bank
*bank
);
40 static uint32_t stellaris_get_flash_status(struct flash_bank
*bank
);
42 static int stellaris_mass_erase(struct flash_bank
*bank
);
219 static char * StellarisClassname
[5] =
228 /***************************************************************************
229 * openocd command interface *
230 ***************************************************************************/
232 /* flash_bank stellaris <base> <size> 0 0 <target#>
234 FLASH_BANK_COMMAND_HANDLER(stellaris_flash_bank_command
)
236 struct stellaris_flash_bank
*stellaris_info
;
240 LOG_WARNING("incomplete flash_bank stellaris configuration");
241 return ERROR_FLASH_BANK_INVALID
;
244 stellaris_info
= calloc(sizeof(struct stellaris_flash_bank
), 1);
246 bank
->driver_priv
= stellaris_info
;
248 stellaris_info
->target_name
= "Unknown target";
250 /* part wasn't probed for info yet */
251 stellaris_info
->did1
= 0;
253 /* TODO Specify the main crystal speed in kHz using an optional
254 * argument; ditto, the speed of an external oscillator used
255 * instead of a crystal. Avoid programming flash using IOSC.
260 static int stellaris_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
262 int printed
, device_class
;
263 struct stellaris_flash_bank
*stellaris_info
= bank
->driver_priv
;
265 stellaris_read_part_info(bank
);
267 if (stellaris_info
->did1
== 0)
269 printed
= snprintf(buf
, buf_size
, "Cannot identify target as a Stellaris\n");
272 return ERROR_FLASH_OPERATION_FAILED
;
275 if (DID0_VER(stellaris_info
->did0
) > 0)
277 device_class
= (stellaris_info
->did0
>> 16) & 0xFF;
283 printed
= snprintf(buf
,
285 "\nTI/LMI Stellaris information: Chip is "
286 "class %i (%s) %s rev %c%i\n",
288 StellarisClassname
[device_class
],
289 stellaris_info
->target_name
,
290 (int)('A' + ((stellaris_info
->did0
>> 8) & 0xFF)),
291 (int)((stellaris_info
->did0
) & 0xFF));
295 printed
= snprintf(buf
,
297 "did1: 0x%8.8" PRIx32
", arch: 0x%4.4" PRIx32
298 ", eproc: %s, ramsize: %ik, flashsize: %ik\n",
299 stellaris_info
->did1
,
300 stellaris_info
->did1
,
302 (int)((1 + ((stellaris_info
->dc0
>> 16) & 0xFFFF))/4),
303 (int)((1 + (stellaris_info
->dc0
& 0xFFFF))*2));
307 printed
= snprintf(buf
,
309 "master clock: %ikHz%s, "
310 "rcc is 0x%" PRIx32
", rcc2 is 0x%" PRIx32
"\n",
311 (int)(stellaris_info
->mck_freq
/ 1000),
312 stellaris_info
->mck_desc
,
314 stellaris_info
->rcc2
);
318 if (stellaris_info
->num_lockbits
> 0)
320 printed
= snprintf(buf
,
322 "pagesize: %" PRIi32
", pages: %d, "
323 "lockbits: %i, pages per lockbit: %i\n",
324 stellaris_info
->pagesize
,
325 (unsigned) stellaris_info
->num_pages
,
326 stellaris_info
->num_lockbits
,
327 (unsigned) stellaris_info
->pages_in_lockregion
);
334 /***************************************************************************
335 * chip identification and status *
336 ***************************************************************************/
338 static uint32_t stellaris_get_flash_status(struct flash_bank
*bank
)
340 struct target
*target
= bank
->target
;
343 target_read_u32(target
, FLASH_CONTROL_BASE
| FLASH_FMC
, &fmc
);
348 /* Set the flash timimg register to match current clocking */
349 static void stellaris_set_flash_timing(struct flash_bank
*bank
)
351 struct stellaris_flash_bank
*stellaris_info
= bank
->driver_priv
;
352 struct target
*target
= bank
->target
;
353 uint32_t usecrl
= (stellaris_info
->mck_freq
/1000000ul-1);
355 LOG_DEBUG("usecrl = %i",(int)(usecrl
));
356 target_write_u32(target
, SCB_BASE
| USECRL
, usecrl
);
359 static const unsigned rcc_xtal
[32] = {
360 [0x00] = 1000000, /* no pll */
361 [0x01] = 1843200, /* no pll */
362 [0x02] = 2000000, /* no pll */
363 [0x03] = 2457600, /* no pll */
367 [0x06] = 4000000, /* usb */
371 [0x09] = 5000000, /* usb */
373 [0x0b] = 6000000, /* (reset) usb */
377 [0x0e] = 8000000, /* usb */
380 /* parts before DustDevil use just 4 bits for xtal spec */
382 [0x10] = 10000000, /* usb */
383 [0x11] = 12000000, /* usb */
388 [0x15] = 16000000, /* usb */
392 /** Read clock configuration and set stellaris_info->usec_clocks. */
393 static void stellaris_read_clock_info(struct flash_bank
*bank
)
395 struct stellaris_flash_bank
*stellaris_info
= bank
->driver_priv
;
396 struct target
*target
= bank
->target
;
397 uint32_t rcc
, rcc2
, pllcfg
, sysdiv
, usesysdiv
, bypass
, oscsrc
;
399 unsigned long mainfreq
;
401 target_read_u32(target
, SCB_BASE
| RCC
, &rcc
);
402 LOG_DEBUG("Stellaris RCC %" PRIx32
"", rcc
);
404 target_read_u32(target
, SCB_BASE
| RCC2
, &rcc2
);
405 LOG_DEBUG("Stellaris RCC2 %" PRIx32
"", rcc
);
407 target_read_u32(target
, SCB_BASE
| PLLCFG
, &pllcfg
);
408 LOG_DEBUG("Stellaris PLLCFG %" PRIx32
"", pllcfg
);
410 stellaris_info
->rcc
= rcc
;
411 stellaris_info
->rcc
= rcc2
;
413 sysdiv
= (rcc
>> 23) & 0xF;
414 usesysdiv
= (rcc
>> 22) & 0x1;
415 bypass
= (rcc
>> 11) & 0x1;
416 oscsrc
= (rcc
>> 4) & 0x3;
417 xtal
= (rcc
>> 6) & stellaris_info
->xtal_mask
;
419 /* NOTE: post-Sandstorm parts have RCC2 which may override
420 * parts of RCC ... with more sysdiv options, option for
421 * 32768 Hz mainfreq, PLL controls. On Sandstorm it reads
422 * as zero, so the "use RCC2" flag is always clear.
424 if (rcc2
& (1 << 31)) {
425 sysdiv
= (rcc2
>> 23) & 0x3F;
426 bypass
= (rcc2
>> 11) & 0x1;
427 oscsrc
= (rcc2
>> 4) & 0x7;
429 /* FIXME Tempest parts have an additional lsb for
430 * fractional sysdiv (200 MHz / 2.5 == 80 MHz)
434 stellaris_info
->mck_desc
= "";
439 mainfreq
= rcc_xtal
[xtal
];
442 mainfreq
= stellaris_info
->iosc_freq
;
443 stellaris_info
->mck_desc
= stellaris_info
->iosc_desc
;
446 mainfreq
= stellaris_info
->iosc_freq
/ 4;
447 stellaris_info
->mck_desc
= stellaris_info
->iosc_desc
;
449 case 3: /* lowspeed */
450 /* Sandstorm doesn't have this 30K +/- 30% osc */
452 stellaris_info
->mck_desc
= " (±30%)";
454 case 8: /* hibernation osc */
455 /* not all parts support hibernation */
459 default: /* NOTREACHED */
464 /* PLL is used if it's not bypassed; its output is 200 MHz
465 * even when it runs at 400 MHz (adds divide-by-two stage).
468 mainfreq
= 200000000;
471 stellaris_info
->mck_freq
= mainfreq
/(1 + sysdiv
);
473 stellaris_info
->mck_freq
= mainfreq
;
477 static uint32_t stellaris_wait_status_busy(struct flash_bank
*bank
, uint32_t waitbits
, int timeout
)
481 /* Stellaris waits for cmdbit to clear */
482 while (((status
= stellaris_get_flash_status(bank
)) & waitbits
) && (timeout
-- > 0))
484 LOG_DEBUG("status: 0x%x", status
);
488 /* Flash errors are reflected in the FLASH_CRIS register */
493 /* Send one command to the flash controller */
494 static int stellaris_flash_command(struct flash_bank
*bank
,uint8_t cmd
,uint16_t pagen
)
497 struct target
*target
= bank
->target
;
499 fmc
= FMC_WRKEY
| cmd
;
500 target_write_u32(target
, FLASH_CONTROL_BASE
| FLASH_FMC
, fmc
);
501 LOG_DEBUG("Flash command: 0x%x", fmc
);
503 if (stellaris_wait_status_busy(bank
, cmd
, 100))
505 return ERROR_FLASH_OPERATION_FAILED
;
512 /* Read device id register, main clock frequency register and fill in driver info structure */
513 static int stellaris_read_part_info(struct flash_bank
*bank
)
515 struct stellaris_flash_bank
*stellaris_info
= bank
->driver_priv
;
516 struct target
*target
= bank
->target
;
517 uint32_t did0
, did1
, ver
, fam
, status
;
520 /* Read and parse chip identification register */
521 target_read_u32(target
, SCB_BASE
| DID0
, &did0
);
522 target_read_u32(target
, SCB_BASE
| DID1
, &did1
);
523 target_read_u32(target
, SCB_BASE
| DC0
, &stellaris_info
->dc0
);
524 target_read_u32(target
, SCB_BASE
| DC1
, &stellaris_info
->dc1
);
525 LOG_DEBUG("did0 0x%" PRIx32
", did1 0x%" PRIx32
", dc0 0x%" PRIx32
", dc1 0x%" PRIx32
"",
526 did0
, did1
, stellaris_info
->dc0
, stellaris_info
->dc1
);
529 if ((ver
!= 0) && (ver
!= 1))
531 LOG_WARNING("Unknown did0 version, cannot identify target");
532 return ERROR_FLASH_OPERATION_FAILED
;
537 LOG_WARNING("Cannot identify target as a Stellaris");
538 return ERROR_FLASH_OPERATION_FAILED
;
542 fam
= (did1
>> 24) & 0xF;
543 if (((ver
!= 0) && (ver
!= 1)) || (fam
!= 0))
545 LOG_WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris");
548 /* For Sandstorm, Fury, DustDevil: current data sheets say IOSC
549 * is 12 MHz, but some older parts have 15 MHz. A few data sheets
550 * even give _both_ numbers! We'll use current numbers; IOSC is
551 * always approximate.
553 * For Tempest: IOSC is calibrated, 16 MHz
555 stellaris_info
->iosc_freq
= 12000000;
556 stellaris_info
->iosc_desc
= " (±30%)";
557 stellaris_info
->xtal_mask
= 0x0f;
559 switch ((did0
>> 28) & 0x7) {
560 case 0: /* Sandstorm */
562 * Current (2009-August) parts seem to be rev C2 and use 12 MHz.
563 * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
564 * (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
566 if (((did0
>> 8) & 0xff) < 2) {
567 stellaris_info
->iosc_freq
= 15000000;
568 stellaris_info
->iosc_desc
= " (±50%)";
572 switch ((did0
>> 16) & 0xff) {
575 case 4: /* Tempest */
576 stellaris_info
->iosc_freq
= 16000000; /* +/- 1% */
577 stellaris_info
->iosc_desc
= " (±1%)";
579 case 3: /* DustDevil */
580 stellaris_info
->xtal_mask
= 0x1f;
583 LOG_WARNING("Unknown did0 class");
587 LOG_WARNING("Unknown did0 version");
590 for (i
= 0; StellarisParts
[i
].partno
; i
++)
592 if (StellarisParts
[i
].partno
== ((did1
>> 16) & 0xFFFF))
596 stellaris_info
->target_name
= StellarisParts
[i
].partname
;
598 stellaris_info
->did0
= did0
;
599 stellaris_info
->did1
= did1
;
601 stellaris_info
->num_lockbits
= 1 + (stellaris_info
->dc0
& 0xFFFF);
602 stellaris_info
->num_pages
= 2 *(1 + (stellaris_info
->dc0
& 0xFFFF));
603 stellaris_info
->pagesize
= 1024;
604 bank
->size
= 1024 * stellaris_info
->num_pages
;
605 stellaris_info
->pages_in_lockregion
= 2;
607 /* provide this for the benefit of the higher flash driver layers */
608 bank
->num_sectors
= stellaris_info
->num_pages
;
609 bank
->sectors
= malloc(sizeof(struct flash_sector
) * bank
->num_sectors
);
610 for (i
= 0; i
< bank
->num_sectors
; i
++)
612 bank
->sectors
[i
].offset
= i
* stellaris_info
->pagesize
;
613 bank
->sectors
[i
].size
= stellaris_info
->pagesize
;
614 bank
->sectors
[i
].is_erased
= -1;
615 bank
->sectors
[i
].is_protected
= -1;
618 /* Read main and master clock freqency register */
619 stellaris_read_clock_info(bank
);
621 status
= stellaris_get_flash_status(bank
);
626 /***************************************************************************
628 ***************************************************************************/
630 static int stellaris_protect_check(struct flash_bank
*bank
)
632 struct stellaris_flash_bank
*stellaris
= bank
->driver_priv
;
633 int status
= ERROR_OK
;
637 if (stellaris
->did1
== 0)
639 status
= stellaris_read_part_info(bank
);
644 for (i
= 0; i
< (unsigned) bank
->num_sectors
; i
++)
645 bank
->sectors
[i
].is_protected
= -1;
647 /* Read each Flash Memory Protection Program Enable (FMPPE) register
648 * to report any pages that we can't write. Ignore the Read Enable
651 for (i
= 0, page
= 0;
652 i
< DIV_ROUND_UP(stellaris
->num_lockbits
, 32u);
656 status
= target_read_u32(bank
->target
,
657 SCB_BASE
+ (i
? (FMPPE0
+ 4 * i
) : FMPPE
),
659 LOG_DEBUG("FMPPE%d = %#8.8x (status %d)", i
,
660 (unsigned) lockbits
, status
);
661 if (status
!= ERROR_OK
)
664 for (unsigned j
= 0; j
< 32; j
++) {
667 for (k
= 0; k
< stellaris
->pages_in_lockregion
; k
++) {
668 if (page
>= (unsigned) bank
->num_sectors
)
670 bank
->sectors
[page
++].is_protected
=
671 !(lockbits
& (1 << j
));
680 static int stellaris_erase(struct flash_bank
*bank
, int first
, int last
)
683 uint32_t flash_fmc
, flash_cris
;
684 struct stellaris_flash_bank
*stellaris_info
= bank
->driver_priv
;
685 struct target
*target
= bank
->target
;
687 if (bank
->target
->state
!= TARGET_HALTED
)
689 LOG_ERROR("Target not halted");
690 return ERROR_TARGET_NOT_HALTED
;
693 if (stellaris_info
->did1
== 0)
695 stellaris_read_part_info(bank
);
698 if (stellaris_info
->did1
== 0)
700 LOG_WARNING("Cannot identify target as Stellaris");
701 return ERROR_FLASH_OPERATION_FAILED
;
704 if ((first
< 0) || (last
< first
) || (last
>= (int)stellaris_info
->num_pages
))
706 return ERROR_FLASH_SECTOR_INVALID
;
709 if ((first
== 0) && (last
== ((int)stellaris_info
->num_pages
-1)))
711 return stellaris_mass_erase(bank
);
714 /* Refresh flash controller timing */
715 stellaris_read_clock_info(bank
);
716 stellaris_set_flash_timing(bank
);
718 /* Clear and disable flash programming interrupts */
719 target_write_u32(target
, FLASH_CIM
, 0);
720 target_write_u32(target
, FLASH_MISC
, PMISC
| AMISC
);
722 for (banknr
= first
; banknr
<= last
; banknr
++)
724 /* Address is first word in page */
725 target_write_u32(target
, FLASH_FMA
, banknr
* stellaris_info
->pagesize
);
726 /* Write erase command */
727 target_write_u32(target
, FLASH_FMC
, FMC_WRKEY
| FMC_ERASE
);
728 /* Wait until erase complete */
731 target_read_u32(target
, FLASH_FMC
, &flash_fmc
);
733 while (flash_fmc
& FMC_ERASE
);
735 /* Check acess violations */
736 target_read_u32(target
, FLASH_CRIS
, &flash_cris
);
737 if (flash_cris
& (AMASK
))
739 LOG_WARNING("Error erasing flash page %i, flash_cris 0x%" PRIx32
"", banknr
, flash_cris
);
740 target_write_u32(target
, FLASH_CRIS
, 0);
741 return ERROR_FLASH_OPERATION_FAILED
;
744 bank
->sectors
[banknr
].is_erased
= 1;
750 static int stellaris_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
752 uint32_t fmppe
, flash_fmc
, flash_cris
;
755 struct stellaris_flash_bank
*stellaris_info
= bank
->driver_priv
;
756 struct target
*target
= bank
->target
;
758 if (bank
->target
->state
!= TARGET_HALTED
)
760 LOG_ERROR("Target not halted");
761 return ERROR_TARGET_NOT_HALTED
;
766 LOG_ERROR("Can't unprotect write-protected pages.");
767 /* except by the "recover locked device" procedure ... */
768 return ERROR_INVALID_ARGUMENTS
;
771 /* lockregions are 2 pages ... must protect [even..odd] */
772 if ((first
< 0) || (first
& 1)
773 || (last
< first
) || !(last
& 1)
774 || (last
>= 2 * stellaris_info
->num_lockbits
))
776 LOG_ERROR("Can't protect unaligned or out-of-range sectors.");
777 return ERROR_FLASH_SECTOR_INVALID
;
780 if (stellaris_info
->did1
== 0)
782 stellaris_read_part_info(bank
);
785 if (stellaris_info
->did1
== 0)
787 LOG_WARNING("Cannot identify target as an Stellaris MCU");
788 return ERROR_FLASH_OPERATION_FAILED
;
791 /* Refresh flash controller timing */
792 stellaris_read_clock_info(bank
);
793 stellaris_set_flash_timing(bank
);
795 /* convert from pages to lockregions */
799 /* FIXME this assumes single FMPPE, for a max of 64K of flash!!
800 * Current parts can be much bigger.
803 LOG_ERROR("No support yet for protection > 64K");
804 return ERROR_FLASH_OPERATION_FAILED
;
807 target_read_u32(target
, SCB_BASE
| FMPPE
, &fmppe
);
809 for (lockregion
= first
; lockregion
<= last
; lockregion
++)
810 fmppe
&= ~(1 << lockregion
);
812 /* Clear and disable flash programming interrupts */
813 target_write_u32(target
, FLASH_CIM
, 0);
814 target_write_u32(target
, FLASH_MISC
, PMISC
| AMISC
);
816 LOG_DEBUG("fmppe 0x%" PRIx32
"",fmppe
);
817 target_write_u32(target
, SCB_BASE
| FMPPE
, fmppe
);
820 target_write_u32(target
, FLASH_FMA
, 1);
822 /* Write commit command */
823 /* REVISIT safety check, since this cannot be undone
824 * except by the "Recover a locked device" procedure.
826 LOG_WARNING("Flash protection cannot be removed once commited, commit is NOT executed !");
827 /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
829 /* Wait until erase complete */
832 target_read_u32(target
, FLASH_FMC
, &flash_fmc
);
834 while (flash_fmc
& FMC_COMT
);
836 /* Check acess violations */
837 target_read_u32(target
, FLASH_CRIS
, &flash_cris
);
838 if (flash_cris
& (AMASK
))
840 LOG_WARNING("Error setting flash page protection, flash_cris 0x%" PRIx32
"", flash_cris
);
841 target_write_u32(target
, FLASH_CRIS
, 0);
842 return ERROR_FLASH_OPERATION_FAILED
;
848 static const uint8_t stellaris_write_code
[] =
853 r1 = destination address
854 r2 = bytecount (in) - endaddr (work)
857 r3 = pFLASH_CTRL_BASE
863 0x07,0x4B, /* ldr r3,pFLASH_CTRL_BASE */
864 0x08,0x4C, /* ldr r4,FLASHWRITECMD */
865 0x01,0x25, /* movs r5, 1 */
866 0x00,0x26, /* movs r6, #0 */
868 0x19,0x60, /* str r1, [r3, #0] */
869 0x87,0x59, /* ldr r7, [r0, r6] */
870 0x5F,0x60, /* str r7, [r3, #4] */
871 0x9C,0x60, /* str r4, [r3, #8] */
873 0x9F,0x68, /* ldr r7, [r3, #8] */
874 0x2F,0x42, /* tst r7, r5 */
875 0xFC,0xD1, /* bne waitloop */
876 0x04,0x31, /* adds r1, r1, #4 */
877 0x04,0x36, /* adds r6, r6, #4 */
878 0x96,0x42, /* cmp r6, r2 */
879 0xF4,0xD1, /* bne mainloop */
881 0xFE,0xE7, /* b exit */
882 /* pFLASH_CTRL_BASE: */
883 0x00,0xD0,0x0F,0x40, /* .word 0x400FD000 */
885 0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */
888 static int stellaris_write_block(struct flash_bank
*bank
,
889 uint8_t *buffer
, uint32_t offset
, uint32_t wcount
)
891 struct target
*target
= bank
->target
;
892 uint32_t buffer_size
= 8192;
893 struct working_area
*source
;
894 struct working_area
*write_algorithm
;
895 uint32_t address
= bank
->base
+ offset
;
896 struct reg_param reg_params
[3];
897 struct armv7m_algorithm armv7m_info
;
898 int retval
= ERROR_OK
;
900 LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32
" wcount=%08" PRIx32
"",
901 bank
, buffer
, offset
, wcount
);
903 /* flash write code */
904 if (target_alloc_working_area(target
, sizeof(stellaris_write_code
), &write_algorithm
) != ERROR_OK
)
906 LOG_WARNING("no working area available, can't do block memory writes");
907 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
910 target_write_buffer(target
, write_algorithm
->address
,
911 sizeof(stellaris_write_code
),
912 (uint8_t *) stellaris_write_code
);
915 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
917 LOG_DEBUG("called target_alloc_working_area(target=%p buffer_size=%08" PRIx32
" source=%p)",
918 target
, buffer_size
, source
);
920 if (buffer_size
<= 256)
922 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
924 target_free_working_area(target
, write_algorithm
);
926 LOG_WARNING("no large enough working area available, can't do block memory writes");
927 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
931 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
932 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
934 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
935 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
936 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
940 uint32_t thisrun_count
= (wcount
> (buffer_size
/ 4)) ? (buffer_size
/ 4) : wcount
;
942 target_write_buffer(target
, source
->address
, thisrun_count
* 4, buffer
);
944 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
945 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
946 buf_set_u32(reg_params
[2].value
, 0, 32, 4*thisrun_count
);
947 LOG_INFO("Algorithm flash write %" PRIi32
" words to 0x%" PRIx32
", %" PRIi32
" remaining", thisrun_count
, address
, (wcount
- thisrun_count
));
948 LOG_DEBUG("Algorithm flash write %" PRIi32
" words to 0x%" PRIx32
", %" PRIi32
" remaining", thisrun_count
, address
, (wcount
- thisrun_count
));
949 if ((retval
= target_run_algorithm(target
, 0, NULL
, 3, reg_params
, write_algorithm
->address
, write_algorithm
->address
+ sizeof(stellaris_write_code
)-10, 10000, &armv7m_info
)) != ERROR_OK
)
951 LOG_ERROR("error executing stellaris flash write algorithm");
952 retval
= ERROR_FLASH_OPERATION_FAILED
;
956 buffer
+= thisrun_count
* 4;
957 address
+= thisrun_count
* 4;
958 wcount
-= thisrun_count
;
961 target_free_working_area(target
, write_algorithm
);
962 target_free_working_area(target
, source
);
964 destroy_reg_param(®_params
[0]);
965 destroy_reg_param(®_params
[1]);
966 destroy_reg_param(®_params
[2]);
971 static int stellaris_write(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
973 struct stellaris_flash_bank
*stellaris_info
= bank
->driver_priv
;
974 struct target
*target
= bank
->target
;
975 uint32_t address
= offset
;
976 uint32_t flash_cris
, flash_fmc
;
977 uint32_t words_remaining
= (count
/ 4);
978 uint32_t bytes_remaining
= (count
& 0x00000003);
979 uint32_t bytes_written
= 0;
982 if (bank
->target
->state
!= TARGET_HALTED
)
984 LOG_ERROR("Target not halted");
985 return ERROR_TARGET_NOT_HALTED
;
988 LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32
" count=%08" PRIx32
"",
989 bank
, buffer
, offset
, count
);
991 if (stellaris_info
->did1
== 0)
993 stellaris_read_part_info(bank
);
996 if (stellaris_info
->did1
== 0)
998 LOG_WARNING("Cannot identify target as a Stellaris processor");
999 return ERROR_FLASH_OPERATION_FAILED
;
1004 LOG_WARNING("offset size must be word aligned");
1005 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
1008 if (offset
+ count
> bank
->size
)
1009 return ERROR_FLASH_DST_OUT_OF_BANK
;
1011 /* Refresh flash controller timing */
1012 stellaris_read_clock_info(bank
);
1013 stellaris_set_flash_timing(bank
);
1015 /* Clear and disable flash programming interrupts */
1016 target_write_u32(target
, FLASH_CIM
, 0);
1017 target_write_u32(target
, FLASH_MISC
, PMISC
| AMISC
);
1019 /* multiple words to be programmed? */
1020 if (words_remaining
> 0)
1022 /* try using a block write */
1023 if ((retval
= stellaris_write_block(bank
, buffer
, offset
, words_remaining
)) != ERROR_OK
)
1025 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1027 /* if block write failed (no sufficient working area),
1028 * we use normal (slow) single dword accesses */
1029 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
1031 else if (retval
== ERROR_FLASH_OPERATION_FAILED
)
1033 /* if an error occured, we examine the reason, and quit */
1034 target_read_u32(target
, FLASH_CRIS
, &flash_cris
);
1036 LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32
"", flash_cris
);
1037 return ERROR_FLASH_OPERATION_FAILED
;
1042 buffer
+= words_remaining
* 4;
1043 address
+= words_remaining
* 4;
1044 words_remaining
= 0;
1048 while (words_remaining
> 0)
1050 if (!(address
& 0xff))
1051 LOG_DEBUG("0x%" PRIx32
"", address
);
1053 /* Program one word */
1054 target_write_u32(target
, FLASH_FMA
, address
);
1055 target_write_buffer(target
, FLASH_FMD
, 4, buffer
);
1056 target_write_u32(target
, FLASH_FMC
, FMC_WRKEY
| FMC_WRITE
);
1057 /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
1058 /* Wait until write complete */
1061 target_read_u32(target
, FLASH_FMC
, &flash_fmc
);
1062 } while (flash_fmc
& FMC_WRITE
);
1069 if (bytes_remaining
)
1071 uint8_t last_word
[4] = {0xff, 0xff, 0xff, 0xff};
1074 while (bytes_remaining
> 0)
1076 last_word
[i
++] = *(buffer
+ bytes_written
);
1081 if (!(address
& 0xff))
1082 LOG_DEBUG("0x%" PRIx32
"", address
);
1084 /* Program one word */
1085 target_write_u32(target
, FLASH_FMA
, address
);
1086 target_write_buffer(target
, FLASH_FMD
, 4, last_word
);
1087 target_write_u32(target
, FLASH_FMC
, FMC_WRKEY
| FMC_WRITE
);
1088 /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
1089 /* Wait until write complete */
1092 target_read_u32(target
, FLASH_FMC
, &flash_fmc
);
1093 } while (flash_fmc
& FMC_WRITE
);
1096 /* Check access violations */
1097 target_read_u32(target
, FLASH_CRIS
, &flash_cris
);
1098 if (flash_cris
& (AMASK
))
1100 LOG_DEBUG("flash_cris 0x%" PRIx32
"", flash_cris
);
1101 return ERROR_FLASH_OPERATION_FAILED
;
1106 static int stellaris_probe(struct flash_bank
*bank
)
1108 /* we can't probe on an stellaris
1109 * if this is an stellaris, it has the configured flash
1112 if (bank
->target
->state
!= TARGET_HALTED
)
1114 LOG_ERROR("Target not halted");
1115 return ERROR_TARGET_NOT_HALTED
;
1118 /* stellaris_read_part_info() already takes care about error checking and reporting */
1119 return stellaris_read_part_info(bank
);
1122 static int stellaris_auto_probe(struct flash_bank
*bank
)
1124 struct stellaris_flash_bank
*stellaris_info
= bank
->driver_priv
;
1125 if (stellaris_info
->did1
)
1127 return stellaris_probe(bank
);
1130 static int stellaris_mass_erase(struct flash_bank
*bank
)
1132 struct target
*target
= NULL
;
1133 struct stellaris_flash_bank
*stellaris_info
= NULL
;
1136 stellaris_info
= bank
->driver_priv
;
1137 target
= bank
->target
;
1139 if (target
->state
!= TARGET_HALTED
)
1141 LOG_ERROR("Target not halted");
1142 return ERROR_TARGET_NOT_HALTED
;
1145 if (stellaris_info
->did1
== 0)
1147 stellaris_read_part_info(bank
);
1150 if (stellaris_info
->did1
== 0)
1152 LOG_WARNING("Cannot identify target as Stellaris");
1153 return ERROR_FLASH_OPERATION_FAILED
;
1156 /* Refresh flash controller timing */
1157 stellaris_read_clock_info(bank
);
1158 stellaris_set_flash_timing(bank
);
1160 /* Clear and disable flash programming interrupts */
1161 target_write_u32(target
, FLASH_CIM
, 0);
1162 target_write_u32(target
, FLASH_MISC
, PMISC
| AMISC
);
1164 target_write_u32(target
, FLASH_FMA
, 0);
1165 target_write_u32(target
, FLASH_FMC
, FMC_WRKEY
| FMC_MERASE
);
1166 /* Wait until erase complete */
1169 target_read_u32(target
, FLASH_FMC
, &flash_fmc
);
1171 while (flash_fmc
& FMC_MERASE
);
1173 /* if device has > 128k, then second erase cycle is needed
1174 * this is only valid for older devices, but will not hurt */
1175 if (stellaris_info
->num_pages
* stellaris_info
->pagesize
> 0x20000)
1177 target_write_u32(target
, FLASH_FMA
, 0x20000);
1178 target_write_u32(target
, FLASH_FMC
, FMC_WRKEY
| FMC_MERASE
);
1179 /* Wait until erase complete */
1182 target_read_u32(target
, FLASH_FMC
, &flash_fmc
);
1184 while (flash_fmc
& FMC_MERASE
);
1190 COMMAND_HANDLER(stellaris_handle_mass_erase_command
)
1196 command_print(CMD_CTX
, "stellaris mass_erase <bank>");
1200 struct flash_bank
*bank
;
1201 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1202 if (ERROR_OK
!= retval
)
1205 if (stellaris_mass_erase(bank
) == ERROR_OK
)
1207 /* set all sectors as erased */
1208 for (i
= 0; i
< bank
->num_sectors
; i
++)
1210 bank
->sectors
[i
].is_erased
= 1;
1213 command_print(CMD_CTX
, "stellaris mass erase complete");
1217 command_print(CMD_CTX
, "stellaris mass erase failed");
1223 static const struct command_registration stellaris_exec_command_handlers
[] = {
1225 .name
= "mass_erase",
1226 .handler
= &stellaris_handle_mass_erase_command
,
1227 .mode
= COMMAND_EXEC
,
1228 .help
= "erase entire device",
1230 COMMAND_REGISTRATION_DONE
1232 static const struct command_registration stellaris_command_handlers
[] = {
1234 .name
= "stellaris",
1235 .mode
= COMMAND_ANY
,
1236 .help
= "Stellaris flash command group",
1237 .chain
= stellaris_exec_command_handlers
,
1239 COMMAND_REGISTRATION_DONE
1242 struct flash_driver stellaris_flash
= {
1243 .name
= "stellaris",
1244 .commands
= stellaris_command_handlers
,
1245 .flash_bank_command
= stellaris_flash_bank_command
,
1246 .erase
= stellaris_erase
,
1247 .protect
= stellaris_protect
,
1248 .write
= stellaris_write
,
1249 .probe
= stellaris_probe
,
1250 .auto_probe
= stellaris_auto_probe
,
1251 .erase_check
= default_flash_mem_blank_check
,
1252 .protect_check
= stellaris_protect_check
,
1253 .info
= stellaris_info
,
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