1 /* SPDX-License-Identifier: GPL-2.0 */
3 * SH QSPI (Quad SPI) driver
4 * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
6 * Based on U-Boot SH QSPI driver
7 * Copyright (C) 2013 Renesas Electronics Corporation
8 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
17 #include <helper/binarybuffer.h>
18 #include <helper/bits.h>
19 #include <helper/time_support.h>
20 #include <helper/types.h>
21 #include <jtag/jtag.h>
22 #include <target/algorithm.h>
23 #include <target/arm.h>
24 #include <target/arm_opcodes.h>
25 #include <target/target.h>
27 /* SH QSPI register bit masks <REG>_<BIT> */
28 #define SPCR_MSTR 0x08
30 #define SPSR_SPRFF 0x80
31 #define SPSR_SPTEF 0x20
32 #define SPPCR_IO3FV 0x04
33 #define SPPCR_IO2FV 0x02
34 #define SPPCR_IO1FV 0x01
35 #define SPBDCR_RXBC0 BIT(0)
36 #define SPCMD_SCKDEN BIT(15)
37 #define SPCMD_SLNDEN BIT(14)
38 #define SPCMD_SPNDEN BIT(13)
39 #define SPCMD_SSLKP BIT(7)
40 #define SPCMD_BRDV0 BIT(2)
41 #define SPCMD_INIT1 (SPCMD_SCKDEN | SPCMD_SLNDEN | \
42 SPCMD_SPNDEN | SPCMD_SSLKP | \
44 #define SPCMD_INIT2 (SPCMD_SPNDEN | SPCMD_SSLKP | \
46 #define SPBFCR_TXRST BIT(7)
47 #define SPBFCR_RXRST BIT(6)
48 #define SPBFCR_TXTRG 0x30
49 #define SPBFCR_RXTRG 0x07
51 /* SH QSPI register set */
52 #define SH_QSPI_SPCR 0x00
53 #define SH_QSPI_SSLP 0x01
54 #define SH_QSPI_SPPCR 0x02
55 #define SH_QSPI_SPSR 0x03
56 #define SH_QSPI_SPDR 0x04
57 #define SH_QSPI_SPSCR 0x08
58 #define SH_QSPI_SPSSR 0x09
59 #define SH_QSPI_SPBR 0x0a
60 #define SH_QSPI_SPDCR 0x0b
61 #define SH_QSPI_SPCKD 0x0c
62 #define SH_QSPI_SSLND 0x0d
63 #define SH_QSPI_SPND 0x0e
64 #define SH_QSPI_DUMMY0 0x0f
65 #define SH_QSPI_SPCMD0 0x10
66 #define SH_QSPI_SPCMD1 0x12
67 #define SH_QSPI_SPCMD2 0x14
68 #define SH_QSPI_SPCMD3 0x16
69 #define SH_QSPI_SPBFCR 0x18
70 #define SH_QSPI_DUMMY1 0x19
71 #define SH_QSPI_SPBDCR 0x1a
72 #define SH_QSPI_SPBMUL0 0x1c
73 #define SH_QSPI_SPBMUL1 0x20
74 #define SH_QSPI_SPBMUL2 0x24
75 #define SH_QSPI_SPBMUL3 0x28
77 struct sh_qspi_flash_bank
{
78 const struct flash_device
*dev
;
81 struct working_area
*io_algorithm
;
82 struct working_area
*source
;
83 unsigned int buffer_size
;
86 struct sh_qspi_target
{
92 static const struct sh_qspi_target target_devices
[] = {
93 /* name, tap_idcode, io_base */
94 { "SH QSPI", 0x4ba00477, 0xe6b10000 },
98 static int sh_qspi_init(struct flash_bank
*bank
)
100 struct target
*target
= bank
->target
;
101 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
105 /* QSPI initialize */
106 /* Set master mode only */
107 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, SPCR_MSTR
);
111 /* Set SSL signal level */
112 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SSLP
, 0x00);
116 /* Set MOSI signal value when transfer is in idle state */
117 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPPCR
,
118 SPPCR_IO3FV
| SPPCR_IO2FV
);
122 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
123 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPBR
, 0x01);
127 /* Disable Dummy Data Transmission */
128 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPDCR
, 0x00);
132 /* Set clock delay value */
133 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPCKD
, 0x00);
137 /* Set SSL negation delay value */
138 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SSLND
, 0x00);
142 /* Set next-access delay value */
143 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPND
, 0x00);
147 /* Set equence command */
148 ret
= target_write_u16(target
, info
->io_base
+ SH_QSPI_SPCMD0
,
153 /* Reset transfer and receive Buffer */
154 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, &val
);
158 val
|= SPBFCR_TXRST
| SPBFCR_RXRST
;
160 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, val
);
164 /* Clear transfer and receive Buffer control bit */
165 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, &val
);
169 val
&= ~(SPBFCR_TXRST
| SPBFCR_RXRST
);
171 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, val
);
175 /* Set equence control method. Use equence0 only */
176 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPSCR
, 0x00);
180 /* Enable SPI function */
181 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, &val
);
187 return target_write_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, val
);
190 static int sh_qspi_cs_activate(struct flash_bank
*bank
)
192 struct target
*target
= bank
->target
;
193 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
197 /* Set master mode only */
198 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, SPCR_MSTR
);
203 ret
= target_write_u16(target
, info
->io_base
+ SH_QSPI_SPCMD0
,
208 /* Reset transfer and receive Buffer */
209 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, &val
);
213 val
|= SPBFCR_TXRST
| SPBFCR_RXRST
;
215 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, val
);
219 /* Clear transfer and receive Buffer control bit */
220 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, &val
);
224 val
&= ~(SPBFCR_TXRST
| SPBFCR_RXRST
);
226 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
, val
);
230 /* Set equence control method. Use equence0 only */
231 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPSCR
, 0x00);
235 /* Enable SPI function */
236 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, &val
);
242 return target_write_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, val
);
245 static int sh_qspi_cs_deactivate(struct flash_bank
*bank
)
247 struct target
*target
= bank
->target
;
248 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
252 /* Disable SPI Function */
253 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, &val
);
259 return target_write_u8(target
, info
->io_base
+ SH_QSPI_SPCR
, val
);
262 static int sh_qspi_wait_for_bit(struct flash_bank
*bank
, uint8_t reg
,
263 uint32_t mask
, bool set
,
264 unsigned long timeout
)
266 struct target
*target
= bank
->target
;
267 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
272 endtime
= timeval_ms() + timeout
;
274 ret
= target_read_u8(target
, info
->io_base
+ reg
, &val
);
281 if ((val
& mask
) == mask
)
285 } while (timeval_ms() < endtime
);
287 LOG_ERROR("timeout");
288 return ERROR_TIMEOUT_REACHED
;
291 static int sh_qspi_xfer_common(struct flash_bank
*bank
,
292 const uint8_t *dout
, unsigned int outlen
,
293 uint8_t *din
, unsigned int inlen
,
294 bool xfer_start
, bool xfer_end
)
296 struct target
*target
= bank
->target
;
297 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
298 uint8_t tdata
, rdata
;
300 unsigned int nbyte
= outlen
+ inlen
;
304 ret
= sh_qspi_cs_activate(bank
);
308 ret
= target_write_u32(target
, info
->io_base
+ SH_QSPI_SPBMUL0
,
313 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
,
318 val
&= ~(SPBFCR_TXTRG
| SPBFCR_RXTRG
);
320 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPBFCR
,
327 ret
= sh_qspi_wait_for_bit(bank
, SH_QSPI_SPSR
, SPSR_SPTEF
,
332 tdata
= outlen
? *dout
++ : 0;
333 ret
= target_write_u8(target
, info
->io_base
+ SH_QSPI_SPDR
,
338 ret
= sh_qspi_wait_for_bit(bank
, SH_QSPI_SPSR
, SPSR_SPRFF
,
343 ret
= target_read_u8(target
, info
->io_base
+ SH_QSPI_SPDR
,
347 if (!outlen
&& inlen
) {
359 return sh_qspi_cs_deactivate(bank
);
364 /* Send "write enable" command to SPI flash chip. */
365 static int sh_qspi_write_enable(struct flash_bank
*bank
)
367 uint8_t dout
= SPIFLASH_WRITE_ENABLE
;
369 return sh_qspi_xfer_common(bank
, &dout
, 1, NULL
, 0, 1, 1);
372 /* Read the status register of the external SPI flash chip. */
373 static int read_status_reg(struct flash_bank
*bank
, uint32_t *status
)
375 uint8_t dout
= SPIFLASH_READ_STATUS
;
379 ret
= sh_qspi_xfer_common(bank
, &dout
, 1, &din
, 1, 1, 1);
383 *status
= din
& 0xff;
388 /* check for WIP (write in progress) bit in status register */
390 static int wait_till_ready(struct flash_bank
*bank
, int timeout
)
396 endtime
= timeval_ms() + timeout
;
398 /* read flash status register */
399 ret
= read_status_reg(bank
, &status
);
403 if ((status
& SPIFLASH_BSY_BIT
) == 0)
406 } while (timeval_ms() < endtime
);
408 LOG_ERROR("timeout");
409 return ERROR_TIMEOUT_REACHED
;
412 static int sh_qspi_erase_sector(struct flash_bank
*bank
, int sector
)
414 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
415 bool addr4b
= info
->dev
->size_in_bytes
> (1UL << 24);
416 uint32_t address
= (sector
* info
->dev
->sectorsize
) <<
419 info
->dev
->erase_cmd
,
420 (address
>> 24) & 0xff, (address
>> 16) & 0xff,
421 (address
>> 8) & 0xff, (address
>> 0) & 0xff
423 unsigned int doutlen
= addr4b
? 5 : 4;
427 ret
= sh_qspi_write_enable(bank
);
432 ret
= sh_qspi_xfer_common(bank
, dout
, doutlen
, NULL
, 0, 1, 1);
436 /* Poll status register */
437 return wait_till_ready(bank
, 3000);
440 static int sh_qspi_erase(struct flash_bank
*bank
, int first
, int last
)
442 struct target
*target
= bank
->target
;
443 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
444 int retval
= ERROR_OK
;
447 LOG_DEBUG("%s: from sector %d to sector %d", __func__
, first
, last
);
449 if (target
->state
!= TARGET_HALTED
) {
450 LOG_ERROR("Target not halted");
451 return ERROR_TARGET_NOT_HALTED
;
454 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
)) {
455 LOG_ERROR("Flash sector invalid");
456 return ERROR_FLASH_SECTOR_INVALID
;
460 LOG_ERROR("Flash bank not probed");
461 return ERROR_FLASH_BANK_NOT_PROBED
;
464 if (info
->dev
->erase_cmd
== 0x00)
465 return ERROR_FLASH_OPER_UNSUPPORTED
;
467 for (sector
= first
; sector
<= last
; sector
++) {
468 if (bank
->sectors
[sector
].is_protected
) {
469 LOG_ERROR("Flash sector %d protected", sector
);
474 for (sector
= first
; sector
<= last
; sector
++) {
475 retval
= sh_qspi_erase_sector(bank
, sector
);
476 if (retval
!= ERROR_OK
)
484 static int sh_qspi_write(struct flash_bank
*bank
, const uint8_t *buffer
,
485 uint32_t offset
, uint32_t count
)
487 struct target
*target
= bank
->target
;
488 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
489 struct reg_param reg_params
[4];
490 struct arm_algorithm arm_algo
;
491 uint32_t io_base
= (uint32_t)(info
->io_base
);
492 uint32_t src_base
= (uint32_t)(info
->source
->address
);
494 bool addr4b
= !!(info
->dev
->size_in_bytes
> (1UL << 24));
498 LOG_DEBUG("%s: offset=0x%08" PRIx32
" count=0x%08" PRIx32
,
499 __func__
, offset
, count
);
501 if (target
->state
!= TARGET_HALTED
) {
502 LOG_ERROR("Target not halted");
503 return ERROR_TARGET_NOT_HALTED
;
506 if (offset
+ count
> bank
->size
) {
507 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
508 count
= bank
->size
- offset
;
512 LOG_ERROR("sh_qspi_write_page: unaligned write address: %08x",
517 /* Check sector protection */
518 for (sector
= 0; sector
< bank
->num_sectors
; sector
++) {
519 /* Start offset in or before this sector? */
520 /* End offset in or behind this sector? */
521 struct flash_sector
*bs
= &bank
->sectors
[sector
];
523 if ((offset
< (bs
->offset
+ bs
->size
)) &&
524 ((offset
+ count
- 1) >= bs
->offset
) &&
526 LOG_ERROR("Flash sector %d protected", sector
);
531 LOG_DEBUG("%s: offset=0x%08" PRIx32
" count=0x%08" PRIx32
,
532 __func__
, offset
, count
);
534 if (target
->state
!= TARGET_HALTED
) {
535 LOG_ERROR("Target not halted");
536 return ERROR_TARGET_NOT_HALTED
;
539 if (offset
+ count
> bank
->size
) {
540 LOG_WARNING("Reads past end of flash. Extra data discarded.");
541 count
= bank
->size
- offset
;
544 arm_algo
.common_magic
= ARM_COMMON_MAGIC
;
545 arm_algo
.core_mode
= ARM_MODE_SVC
;
546 arm_algo
.core_state
= ARM_STATE_ARM
;
548 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
549 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
550 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
551 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
554 chunk
= (count
> info
->buffer_size
) ?
555 info
->buffer_size
: count
;
557 target_write_buffer(target
, info
->source
->address
,
560 buf_set_u32(reg_params
[0].value
, 0, 32, io_base
);
561 buf_set_u32(reg_params
[1].value
, 0, 32, src_base
);
562 buf_set_u32(reg_params
[2].value
, 0, 32,
563 (1 << 31) | (addr4b
<< 30) |
564 (info
->dev
->pprog_cmd
<< 20) | chunk
);
565 buf_set_u32(reg_params
[3].value
, 0, 32, offset
);
567 ret
= target_run_algorithm(target
, 0, NULL
, 4, reg_params
,
568 info
->io_algorithm
->address
,
569 0, 10000, &arm_algo
);
570 if (ret
!= ERROR_OK
) {
571 LOG_ERROR("error executing SH QSPI flash IO algorithm");
572 ret
= ERROR_FLASH_OPERATION_FAILED
;
581 destroy_reg_param(®_params
[0]);
582 destroy_reg_param(®_params
[1]);
583 destroy_reg_param(®_params
[2]);
584 destroy_reg_param(®_params
[3]);
589 static int sh_qspi_read(struct flash_bank
*bank
, uint8_t *buffer
,
590 uint32_t offset
, uint32_t count
)
592 struct target
*target
= bank
->target
;
593 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
594 struct reg_param reg_params
[4];
595 struct arm_algorithm arm_algo
;
596 uint32_t io_base
= (uint32_t)(info
->io_base
);
597 uint32_t src_base
= (uint32_t)(info
->source
->address
);
599 bool addr4b
= !!(info
->dev
->size_in_bytes
> (1UL << 24));
602 LOG_DEBUG("%s: offset=0x%08" PRIx32
" count=0x%08" PRIx32
,
603 __func__
, offset
, count
);
605 if (target
->state
!= TARGET_HALTED
) {
606 LOG_ERROR("Target not halted");
607 return ERROR_TARGET_NOT_HALTED
;
610 if (offset
+ count
> bank
->size
) {
611 LOG_WARNING("Reads past end of flash. Extra data discarded.");
612 count
= bank
->size
- offset
;
615 arm_algo
.common_magic
= ARM_COMMON_MAGIC
;
616 arm_algo
.core_mode
= ARM_MODE_SVC
;
617 arm_algo
.core_state
= ARM_STATE_ARM
;
619 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
620 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
621 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
622 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
625 chunk
= (count
> info
->buffer_size
) ?
626 info
->buffer_size
: count
;
628 buf_set_u32(reg_params
[0].value
, 0, 32, io_base
);
629 buf_set_u32(reg_params
[1].value
, 0, 32, src_base
);
630 buf_set_u32(reg_params
[2].value
, 0, 32,
631 (addr4b
<< 30) | (info
->dev
->read_cmd
<< 20) |
633 buf_set_u32(reg_params
[3].value
, 0, 32, offset
);
635 ret
= target_run_algorithm(target
, 0, NULL
, 4, reg_params
,
636 info
->io_algorithm
->address
,
637 0, 10000, &arm_algo
);
638 if (ret
!= ERROR_OK
) {
639 LOG_ERROR("error executing SH QSPI flash IO algorithm");
640 ret
= ERROR_FLASH_OPERATION_FAILED
;
644 target_read_buffer(target
, info
->source
->address
,
652 destroy_reg_param(®_params
[0]);
653 destroy_reg_param(®_params
[1]);
654 destroy_reg_param(®_params
[2]);
655 destroy_reg_param(®_params
[3]);
660 /* Return ID of flash device */
661 static int read_flash_id(struct flash_bank
*bank
, uint32_t *id
)
663 struct target
*target
= bank
->target
;
664 uint8_t dout
= SPIFLASH_READ_ID
;
665 uint8_t din
[3] = { 0, 0, 0 };
668 if (target
->state
!= TARGET_HALTED
) {
669 LOG_ERROR("Target not halted");
670 return ERROR_TARGET_NOT_HALTED
;
673 ret
= sh_qspi_xfer_common(bank
, &dout
, 1, din
, 3, 1, 1);
677 *id
= (din
[0] << 0) | (din
[1] << 8) | (din
[2] << 16);
679 if (*id
== 0xffffff) {
680 LOG_ERROR("No SPI flash found");
687 static int sh_qspi_protect(struct flash_bank
*bank
, int set
,
692 for (sector
= first
; sector
<= last
; sector
++)
693 bank
->sectors
[sector
].is_protected
= set
;
698 static int sh_qspi_upload_helper(struct flash_bank
*bank
)
700 struct target
*target
= bank
->target
;
701 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
703 /* see contrib/loaders/flash/sh_qspi.s for src */
704 static const uint8_t sh_qspi_io_code
[] = {
705 #include "../../../contrib/loaders/flash/sh_qspi/sh_qspi.inc"
710 target_free_working_area(target
, info
->source
);
711 if (info
->io_algorithm
)
712 target_free_working_area(target
, info
->io_algorithm
);
714 /* flash write code */
715 if (target_alloc_working_area(target
, sizeof(sh_qspi_io_code
),
716 &info
->io_algorithm
) != ERROR_OK
) {
717 LOG_WARNING("no working area available, can't do block memory writes");
718 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
721 target_write_buffer(target
, info
->io_algorithm
->address
,
722 sizeof(sh_qspi_io_code
), sh_qspi_io_code
);
725 * Try to allocate as big work area buffer as possible, start
726 * with 32 kiB and count down. If there is less than 256 Bytes
727 * of work area available, abort.
729 info
->buffer_size
= 32768;
731 ret
= target_alloc_working_area_try(target
, info
->buffer_size
,
736 info
->buffer_size
/= 2;
737 if (info
->buffer_size
<= 256) {
738 target_free_working_area(target
, info
->io_algorithm
);
740 LOG_WARNING("no large enough working area available, can't do block memory writes");
741 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
748 static int sh_qspi_probe(struct flash_bank
*bank
)
750 struct target
*target
= bank
->target
;
751 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
752 struct flash_sector
*sectors
;
753 uint32_t id
= 0; /* silence uninitialized warning */
755 const struct sh_qspi_target
*target_device
;
763 for (target_device
= target_devices
; target_device
->name
;
765 if (target_device
->tap_idcode
== target
->tap
->idcode
)
767 if (!target_device
->name
) {
768 LOG_ERROR("Device ID 0x%" PRIx32
" is not known",
769 target
->tap
->idcode
);
773 info
->io_base
= target_device
->io_base
;
775 LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT
,
776 target_device
->name
, bank
->base
);
778 ret
= sh_qspi_upload_helper(bank
);
782 ret
= sh_qspi_init(bank
);
786 ret
= read_flash_id(bank
, &id
);
791 for (const struct flash_device
*p
= flash_devices
; p
->name
; p
++)
792 if (p
->device_id
== id
) {
798 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32
")", id
);
802 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32
")",
803 info
->dev
->name
, info
->dev
->device_id
);
805 /* Set correct size value */
806 bank
->size
= info
->dev
->size_in_bytes
;
807 if (bank
->size
<= (1UL << 16))
808 LOG_WARNING("device needs 2-byte addresses - not implemented");
810 /* if no sectors, treat whole bank as single sector */
811 sectorsize
= info
->dev
->sectorsize
?
812 info
->dev
->sectorsize
:
813 info
->dev
->size_in_bytes
;
815 /* create and fill sectors array */
816 bank
->num_sectors
= info
->dev
->size_in_bytes
/ sectorsize
;
817 sectors
= calloc(1, sizeof(*sectors
) * bank
->num_sectors
);
819 LOG_ERROR("not enough memory");
823 for (int sector
= 0; sector
< bank
->num_sectors
; sector
++) {
824 sectors
[sector
].offset
= sector
* sectorsize
;
825 sectors
[sector
].size
= sectorsize
;
826 sectors
[sector
].is_erased
= 0;
827 sectors
[sector
].is_protected
= 0;
830 bank
->sectors
= sectors
;
835 static int sh_qspi_auto_probe(struct flash_bank
*bank
)
837 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
842 return sh_qspi_probe(bank
);
845 static int sh_qspi_flash_blank_check(struct flash_bank
*bank
)
847 /* Not implemented */
851 static int sh_qspi_protect_check(struct flash_bank
*bank
)
853 /* Not implemented */
857 static int sh_qspi_get_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
859 struct sh_qspi_flash_bank
*info
= bank
->driver_priv
;
862 snprintf(buf
, buf_size
,
863 "\nSH QSPI flash bank not probed yet\n");
867 snprintf(buf
, buf_size
, "\nSH QSPI flash information:\n"
868 " Device \'%s\' (ID 0x%08" PRIx32
")\n",
869 info
->dev
->name
, info
->dev
->device_id
);
874 FLASH_BANK_COMMAND_HANDLER(sh_qspi_flash_bank_command
)
876 struct sh_qspi_flash_bank
*info
;
878 LOG_DEBUG("%s", __func__
);
880 if (CMD_ARGC
< 6 || CMD_ARGC
> 7)
881 return ERROR_COMMAND_SYNTAX_ERROR
;
883 if ((CMD_ARGC
== 7) && strcmp(CMD_ARGV
[6], "cs0")) {
884 LOG_ERROR("Unknown arg: %s", CMD_ARGV
[6]);
885 return ERROR_COMMAND_SYNTAX_ERROR
;
888 info
= calloc(1, sizeof(struct sh_qspi_flash_bank
));
890 LOG_ERROR("not enough memory");
894 bank
->driver_priv
= info
;
899 const struct flash_driver sh_qspi_flash
= {
901 .flash_bank_command
= sh_qspi_flash_bank_command
,
902 .erase
= sh_qspi_erase
,
903 .protect
= sh_qspi_protect
,
904 .write
= sh_qspi_write
,
905 .read
= sh_qspi_read
,
906 .probe
= sh_qspi_probe
,
907 .auto_probe
= sh_qspi_auto_probe
,
908 .erase_check
= sh_qspi_flash_blank_check
,
909 .protect_check
= sh_qspi_protect_check
,
910 .info
= sh_qspi_get_info
,
911 .free_driver_priv
= default_flash_free_driver_priv
,
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