1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
21 ***************************************************************************/
28 #include <target/algorithm.h>
29 #include <target/armv7m.h>
30 #include <helper/types.h>
33 NRF51_FLASH_BASE
= 0x00000000,
36 enum nrf51_ficr_registers
{
37 NRF51_FICR_BASE
= 0x10000000, /* Factory Information Configuration Registers */
39 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
41 NRF51_FICR_CODEPAGESIZE
= NRF51_FICR_REG(0x010),
42 NRF51_FICR_CODESIZE
= NRF51_FICR_REG(0x014),
43 NRF51_FICR_CLENR0
= NRF51_FICR_REG(0x028),
44 NRF51_FICR_PPFC
= NRF51_FICR_REG(0x02C),
45 NRF51_FICR_NUMRAMBLOCK
= NRF51_FICR_REG(0x034),
46 NRF51_FICR_SIZERAMBLOCK0
= NRF51_FICR_REG(0x038),
47 NRF51_FICR_SIZERAMBLOCK1
= NRF51_FICR_REG(0x03C),
48 NRF51_FICR_SIZERAMBLOCK2
= NRF51_FICR_REG(0x040),
49 NRF51_FICR_SIZERAMBLOCK3
= NRF51_FICR_REG(0x044),
50 NRF51_FICR_CONFIGID
= NRF51_FICR_REG(0x05C),
51 NRF51_FICR_DEVICEID0
= NRF51_FICR_REG(0x060),
52 NRF51_FICR_DEVICEID1
= NRF51_FICR_REG(0x064),
53 NRF51_FICR_ER0
= NRF51_FICR_REG(0x080),
54 NRF51_FICR_ER1
= NRF51_FICR_REG(0x084),
55 NRF51_FICR_ER2
= NRF51_FICR_REG(0x088),
56 NRF51_FICR_ER3
= NRF51_FICR_REG(0x08C),
57 NRF51_FICR_IR0
= NRF51_FICR_REG(0x090),
58 NRF51_FICR_IR1
= NRF51_FICR_REG(0x094),
59 NRF51_FICR_IR2
= NRF51_FICR_REG(0x098),
60 NRF51_FICR_IR3
= NRF51_FICR_REG(0x09C),
61 NRF51_FICR_DEVICEADDRTYPE
= NRF51_FICR_REG(0x0A0),
62 NRF51_FICR_DEVICEADDR0
= NRF51_FICR_REG(0x0A4),
63 NRF51_FICR_DEVICEADDR1
= NRF51_FICR_REG(0x0A8),
64 NRF51_FICR_OVERRIDEN
= NRF51_FICR_REG(0x0AC),
65 NRF51_FICR_NRF_1MBIT0
= NRF51_FICR_REG(0x0B0),
66 NRF51_FICR_NRF_1MBIT1
= NRF51_FICR_REG(0x0B4),
67 NRF51_FICR_NRF_1MBIT2
= NRF51_FICR_REG(0x0B8),
68 NRF51_FICR_NRF_1MBIT3
= NRF51_FICR_REG(0x0BC),
69 NRF51_FICR_NRF_1MBIT4
= NRF51_FICR_REG(0x0C0),
70 NRF51_FICR_BLE_1MBIT0
= NRF51_FICR_REG(0x0EC),
71 NRF51_FICR_BLE_1MBIT1
= NRF51_FICR_REG(0x0F0),
72 NRF51_FICR_BLE_1MBIT2
= NRF51_FICR_REG(0x0F4),
73 NRF51_FICR_BLE_1MBIT3
= NRF51_FICR_REG(0x0F8),
74 NRF51_FICR_BLE_1MBIT4
= NRF51_FICR_REG(0x0FC),
77 enum nrf51_uicr_registers
{
78 NRF51_UICR_BASE
= 0x10001000, /* User Information
79 * Configuration Regsters */
81 NRF51_UICR_SIZE
= 0x100,
83 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
85 NRF51_UICR_CLENR0
= NRF51_UICR_REG(0x000),
86 NRF51_UICR_RBPCONF
= NRF51_UICR_REG(0x004),
87 NRF51_UICR_XTALFREQ
= NRF51_UICR_REG(0x008),
88 NRF51_UICR_FWID
= NRF51_UICR_REG(0x010),
91 enum nrf51_nvmc_registers
{
92 NRF51_NVMC_BASE
= 0x4001E000, /* Non-Volatile Memory
93 * Controller Regsters */
95 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
97 NRF51_NVMC_READY
= NRF51_NVMC_REG(0x400),
98 NRF51_NVMC_CONFIG
= NRF51_NVMC_REG(0x504),
99 NRF51_NVMC_ERASEPAGE
= NRF51_NVMC_REG(0x508),
100 NRF51_NVMC_ERASEALL
= NRF51_NVMC_REG(0x50C),
101 NRF51_NVMC_ERASEUICR
= NRF51_NVMC_REG(0x514),
104 enum nrf51_nvmc_config_bits
{
105 NRF51_NVMC_CONFIG_REN
= 0x00,
106 NRF51_NVMC_CONFIG_WEN
= 0x01,
107 NRF51_NVMC_CONFIG_EEN
= 0x02,
112 uint32_t code_page_size
;
113 uint32_t code_memory_size
;
117 int (*write
) (struct flash_bank
*bank
,
118 struct nrf51_info
*chip
,
119 const uint8_t *buffer
, uint32_t offset
, uint32_t count
);
121 struct target
*target
;
124 struct nrf51_device_spec
{
127 const char *build_code
;
128 unsigned int flash_size_kb
;
131 /* The known devices table below is derived from the "nRF51 Series
132 * Compatibility Matrix" document, which can be found by searching for
133 * ATTN-51 on the Nordic Semi website:
135 * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
137 * Up to date with Matrix v2.0, plus some additional HWIDs.
139 * The additional HWIDs apply where the build code in the matrix is
140 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
141 * for x==0, x!=0 means different (unspecified) HWIDs.
143 static const struct nrf51_device_spec nrf51_known_devices_table
[] = {
144 /* nRF51822 Devices (IC rev 1). */
148 .build_code
= "CA/C0",
149 .flash_size_kb
= 256,
155 .flash_size_kb
= 128,
161 .flash_size_kb
= 128,
167 .flash_size_kb
= 256,
173 .flash_size_kb
= 256,
176 /* nRF51822 Devices (IC rev 2). */
181 .flash_size_kb
= 256,
187 .flash_size_kb
= 256,
193 .flash_size_kb
= 256,
199 .flash_size_kb
= 128,
205 .flash_size_kb
= 256,
211 .flash_size_kb
= 256,
217 .flash_size_kb
= 256,
220 /* nRF51822 Devices (IC rev 3). */
225 .flash_size_kb
= 256,
231 .flash_size_kb
= 128,
237 .flash_size_kb
= 256,
243 .flash_size_kb
= 128,
249 .flash_size_kb
= 256,
255 .flash_size_kb
= 256,
258 /* nRF51422 Devices (IC rev 1). */
263 .flash_size_kb
= 256,
269 .flash_size_kb
= 256,
275 .flash_size_kb
= 256,
278 /* nRF51422 Devices (IC rev 2). */
283 .flash_size_kb
= 256,
289 .flash_size_kb
= 256,
295 .flash_size_kb
= 128,
301 .flash_size_kb
= 256,
304 /* nRF51422 Devices (IC rev 3). */
309 .flash_size_kb
= 256,
315 .flash_size_kb
= 128,
321 .flash_size_kb
= 256,
327 .flash_size_kb
= 256,
333 .flash_size_kb
= 256,
339 .flash_size_kb
= 128,
345 .flash_size_kb
= 256,
351 .flash_size_kb
= 256,
354 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
355 with built-in jlink seem to use engineering samples not listed
356 in the nRF51 Series Compatibility Matrix V1.0. */
361 .flash_size_kb
= 256,
365 static int nrf51_bank_is_probed(struct flash_bank
*bank
)
367 struct nrf51_info
*chip
= bank
->driver_priv
;
369 assert(chip
!= NULL
);
371 return chip
->bank
[bank
->bank_number
].probed
;
373 static int nrf51_probe(struct flash_bank
*bank
);
375 static int nrf51_get_probed_chip_if_halted(struct flash_bank
*bank
, struct nrf51_info
**chip
)
377 if (bank
->target
->state
!= TARGET_HALTED
) {
378 LOG_ERROR("Target not halted");
379 return ERROR_TARGET_NOT_HALTED
;
382 *chip
= bank
->driver_priv
;
384 int probed
= nrf51_bank_is_probed(bank
);
388 return nrf51_probe(bank
);
393 static int nrf51_wait_for_nvmc(struct nrf51_info
*chip
)
400 res
= target_read_u32(chip
->target
, NRF51_NVMC_READY
, &ready
);
401 if (res
!= ERROR_OK
) {
402 LOG_ERROR("Couldn't read NVMC_READY register");
406 if (ready
== 0x00000001)
412 LOG_DEBUG("Timed out waiting for NVMC_READY");
413 return ERROR_FLASH_BUSY
;
416 static int nrf51_nvmc_erase_enable(struct nrf51_info
*chip
)
419 res
= target_write_u32(chip
->target
,
421 NRF51_NVMC_CONFIG_EEN
);
423 if (res
!= ERROR_OK
) {
424 LOG_ERROR("Failed to enable erase operation");
429 According to NVMC examples in Nordic SDK busy status must be
430 checked after writing to NVMC_CONFIG
432 res
= nrf51_wait_for_nvmc(chip
);
434 LOG_ERROR("Erase enable did not complete");
439 static int nrf51_nvmc_write_enable(struct nrf51_info
*chip
)
442 res
= target_write_u32(chip
->target
,
444 NRF51_NVMC_CONFIG_WEN
);
446 if (res
!= ERROR_OK
) {
447 LOG_ERROR("Failed to enable write operation");
452 According to NVMC examples in Nordic SDK busy status must be
453 checked after writing to NVMC_CONFIG
455 res
= nrf51_wait_for_nvmc(chip
);
457 LOG_ERROR("Write enable did not complete");
462 static int nrf51_nvmc_read_only(struct nrf51_info
*chip
)
465 res
= target_write_u32(chip
->target
,
467 NRF51_NVMC_CONFIG_REN
);
469 if (res
!= ERROR_OK
) {
470 LOG_ERROR("Failed to enable read-only operation");
474 According to NVMC examples in Nordic SDK busy status must be
475 checked after writing to NVMC_CONFIG
477 res
= nrf51_wait_for_nvmc(chip
);
479 LOG_ERROR("Read only enable did not complete");
484 static int nrf51_nvmc_generic_erase(struct nrf51_info
*chip
,
485 uint32_t erase_register
, uint32_t erase_value
)
489 res
= nrf51_nvmc_erase_enable(chip
);
493 res
= target_write_u32(chip
->target
,
499 res
= nrf51_wait_for_nvmc(chip
);
503 return nrf51_nvmc_read_only(chip
);
506 nrf51_nvmc_read_only(chip
);
508 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32
,
509 erase_register
, erase_value
);
513 static int nrf51_protect_check(struct flash_bank
*bank
)
518 /* UICR cannot be write protected so just return early */
519 if (bank
->base
== NRF51_UICR_BASE
)
522 struct nrf51_info
*chip
= bank
->driver_priv
;
524 assert(chip
!= NULL
);
526 res
= target_read_u32(chip
->target
, NRF51_FICR_CLENR0
,
528 if (res
!= ERROR_OK
) {
529 LOG_ERROR("Couldn't read code region 0 size[FICR]");
533 if (clenr0
== 0xFFFFFFFF) {
534 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
536 if (res
!= ERROR_OK
) {
537 LOG_ERROR("Couldn't read code region 0 size[UICR]");
542 for (int i
= 0; i
< bank
->num_sectors
; i
++)
543 bank
->sectors
[i
].is_protected
=
544 clenr0
!= 0xFFFFFFFF && bank
->sectors
[i
].offset
< clenr0
;
549 static int nrf51_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
552 uint32_t clenr0
, ppfc
;
553 struct nrf51_info
*chip
;
555 /* UICR cannot be write protected so just bail out early */
556 if (bank
->base
== NRF51_UICR_BASE
)
559 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
564 LOG_ERROR("Code region 0 must start at the begining of the bank");
568 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
570 if (res
!= ERROR_OK
) {
571 LOG_ERROR("Couldn't read PPFC register");
575 if ((ppfc
& 0xFF) == 0x00) {
576 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
580 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
582 if (res
!= ERROR_OK
) {
583 LOG_ERROR("Couldn't read code region 0 size[UICR]");
587 if (clenr0
== 0xFFFFFFFF) {
588 res
= target_write_u32(chip
->target
, NRF51_UICR_CLENR0
,
590 if (res
!= ERROR_OK
) {
591 LOG_ERROR("Couldn't write code region 0 size[UICR]");
596 LOG_ERROR("You need to perform chip erase before changing the protection settings");
599 nrf51_protect_check(bank
);
604 static int nrf51_probe(struct flash_bank
*bank
)
608 struct nrf51_info
*chip
= bank
->driver_priv
;
610 res
= target_read_u32(chip
->target
, NRF51_FICR_CONFIGID
, &hwid
);
611 if (res
!= ERROR_OK
) {
612 LOG_ERROR("Couldn't read CONFIGID register");
616 hwid
&= 0xFFFF; /* HWID is stored in the lower two
617 * bytes of the CONFIGID register */
619 const struct nrf51_device_spec
*spec
= NULL
;
620 for (size_t i
= 0; i
< ARRAY_SIZE(nrf51_known_devices_table
); i
++)
621 if (hwid
== nrf51_known_devices_table
[i
].hwid
) {
622 spec
= &nrf51_known_devices_table
[i
];
626 if (!chip
->bank
[0].probed
&& !chip
->bank
[1].probed
) {
628 LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
629 spec
->variant
, spec
->build_code
, spec
->flash_size_kb
);
631 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32
")", hwid
);
635 if (bank
->base
== NRF51_FLASH_BASE
) {
636 res
= target_read_u32(chip
->target
, NRF51_FICR_CODEPAGESIZE
,
637 &chip
->code_page_size
);
638 if (res
!= ERROR_OK
) {
639 LOG_ERROR("Couldn't read code page size");
643 res
= target_read_u32(chip
->target
, NRF51_FICR_CODESIZE
,
644 &chip
->code_memory_size
);
645 if (res
!= ERROR_OK
) {
646 LOG_ERROR("Couldn't read code memory size");
650 if (spec
&& chip
->code_memory_size
!= spec
->flash_size_kb
) {
651 LOG_ERROR("Chip's reported Flash capacity does not match expected one");
655 bank
->size
= chip
->code_memory_size
* 1024;
656 bank
->num_sectors
= bank
->size
/ chip
->code_page_size
;
657 bank
->sectors
= calloc(bank
->num_sectors
,
658 sizeof((bank
->sectors
)[0]));
660 return ERROR_FLASH_BANK_NOT_PROBED
;
662 /* Fill out the sector information: all NRF51 sectors are the same size and
663 * there is always a fixed number of them. */
664 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
665 bank
->sectors
[i
].size
= chip
->code_page_size
;
666 bank
->sectors
[i
].offset
= i
* chip
->code_page_size
;
668 /* mark as unknown */
669 bank
->sectors
[i
].is_erased
= -1;
670 bank
->sectors
[i
].is_protected
= -1;
673 nrf51_protect_check(bank
);
675 chip
->bank
[0].probed
= true;
677 bank
->size
= NRF51_UICR_SIZE
;
678 bank
->num_sectors
= 1;
679 bank
->sectors
= calloc(bank
->num_sectors
,
680 sizeof((bank
->sectors
)[0]));
682 return ERROR_FLASH_BANK_NOT_PROBED
;
684 bank
->sectors
[0].size
= bank
->size
;
685 bank
->sectors
[0].offset
= 0;
687 /* mark as unknown */
688 bank
->sectors
[0].is_erased
= 0;
689 bank
->sectors
[0].is_protected
= 0;
691 chip
->bank
[1].probed
= true;
697 static int nrf51_auto_probe(struct flash_bank
*bank
)
699 int probed
= nrf51_bank_is_probed(bank
);
706 return nrf51_probe(bank
);
709 static struct flash_sector
*nrf51_find_sector_by_address(struct flash_bank
*bank
, uint32_t address
)
711 struct nrf51_info
*chip
= bank
->driver_priv
;
713 for (int i
= 0; i
< bank
->num_sectors
; i
++)
714 if (bank
->sectors
[i
].offset
<= address
&&
715 address
< (bank
->sectors
[i
].offset
+ chip
->code_page_size
))
716 return &bank
->sectors
[i
];
720 static int nrf51_erase_all(struct nrf51_info
*chip
)
722 LOG_DEBUG("Erasing all non-volatile memory");
723 return nrf51_nvmc_generic_erase(chip
,
728 static int nrf51_erase_page(struct flash_bank
*bank
,
729 struct nrf51_info
*chip
,
730 struct flash_sector
*sector
)
734 LOG_DEBUG("Erasing page at 0x%"PRIx32
, sector
->offset
);
735 if (sector
->is_protected
) {
736 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32
, sector
->offset
);
740 if (bank
->base
== NRF51_UICR_BASE
) {
742 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
744 if (res
!= ERROR_OK
) {
745 LOG_ERROR("Couldn't read PPFC register");
749 if ((ppfc
& 0xFF) == 0xFF) {
750 /* We can't erase the UICR. Double-check to
751 see if it's already erased before complaining. */
752 default_flash_blank_check(bank
);
753 if (sector
->is_erased
== 1)
756 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
760 res
= nrf51_nvmc_generic_erase(chip
,
761 NRF51_NVMC_ERASEUICR
,
766 res
= nrf51_nvmc_generic_erase(chip
,
767 NRF51_NVMC_ERASEPAGE
,
772 sector
->is_erased
= 1;
777 static const uint8_t nrf51_flash_write_code
[] = {
778 /* See contrib/loaders/flash/cortex-m0.S */
780 0x0d, 0x68, /* ldr r5, [r1, #0] */
781 0x00, 0x2d, /* cmp r5, #0 */
782 0x0b, 0xd0, /* beq.n 1e <exit> */
783 0x4c, 0x68, /* ldr r4, [r1, #4] */
784 0xac, 0x42, /* cmp r4, r5 */
785 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
786 0x20, 0xcc, /* ldmia r4!, {r5} */
787 0x20, 0xc3, /* stmia r3!, {r5} */
788 0x94, 0x42, /* cmp r4, r2 */
789 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
790 0x0c, 0x46, /* mov r4, r1 */
791 0x08, 0x34, /* adds r4, #8 */
793 0x4c, 0x60, /* str r4, [r1, #4] */
794 0x04, 0x38, /* subs r0, #4 */
795 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
797 0x00, 0xbe /* bkpt 0x0000 */
801 /* Start a low level flash write for the specified region */
802 static int nrf51_ll_flash_write(struct nrf51_info
*chip
, uint32_t offset
, const uint8_t *buffer
, uint32_t bytes
)
804 struct target
*target
= chip
->target
;
805 uint32_t buffer_size
= 8192;
806 struct working_area
*write_algorithm
;
807 struct working_area
*source
;
808 uint32_t address
= NRF51_FLASH_BASE
+ offset
;
809 struct reg_param reg_params
[4];
810 struct armv7m_algorithm armv7m_info
;
811 int retval
= ERROR_OK
;
814 LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32
" bytes=0x%"PRIx32
, offset
, bytes
);
815 assert(bytes
% 4 == 0);
817 /* allocate working area with flash programming code */
818 if (target_alloc_working_area(target
, sizeof(nrf51_flash_write_code
),
819 &write_algorithm
) != ERROR_OK
) {
820 LOG_WARNING("no working area available, falling back to slow memory writes");
822 for (; bytes
> 0; bytes
-= 4) {
823 retval
= target_write_memory(chip
->target
, offset
, 4, 1, buffer
);
824 if (retval
!= ERROR_OK
)
827 retval
= nrf51_wait_for_nvmc(chip
);
828 if (retval
!= ERROR_OK
)
838 LOG_WARNING("using fast async flash loader. This is currently supported");
839 LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
840 LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg to disable it");
842 retval
= target_write_buffer(target
, write_algorithm
->address
,
843 sizeof(nrf51_flash_write_code
),
844 nrf51_flash_write_code
);
845 if (retval
!= ERROR_OK
)
849 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
) {
851 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
852 if (buffer_size
<= 256) {
853 /* free working area, write algorithm already allocated */
854 target_free_working_area(target
, write_algorithm
);
856 LOG_WARNING("No large enough working area available, can't do block memory writes");
857 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
861 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
862 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
864 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* byte count */
865 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer start */
866 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer end */
867 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
); /* target address */
869 buf_set_u32(reg_params
[0].value
, 0, 32, bytes
);
870 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
871 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
+ source
->size
);
872 buf_set_u32(reg_params
[3].value
, 0, 32, address
);
874 retval
= target_run_flash_async_algorithm(target
, buffer
, bytes
/4, 4,
877 source
->address
, source
->size
,
878 write_algorithm
->address
, 0,
881 target_free_working_area(target
, source
);
882 target_free_working_area(target
, write_algorithm
);
884 destroy_reg_param(®_params
[0]);
885 destroy_reg_param(®_params
[1]);
886 destroy_reg_param(®_params
[2]);
887 destroy_reg_param(®_params
[3]);
892 /* Check and erase flash sectors in specified range then start a low level page write.
893 start/end must be sector aligned.
895 static int nrf51_write_pages(struct flash_bank
*bank
, uint32_t start
, uint32_t end
, const uint8_t *buffer
)
897 int res
= ERROR_FAIL
;
898 struct nrf51_info
*chip
= bank
->driver_priv
;
899 struct flash_sector
*sector
;
902 assert(start
% chip
->code_page_size
== 0);
903 assert(end
% chip
->code_page_size
== 0);
905 /* Erase all sectors */
906 for (offset
= start
; offset
< end
; offset
+= chip
->code_page_size
) {
907 sector
= nrf51_find_sector_by_address(bank
, offset
);
909 LOG_ERROR("Invalid sector @ 0x%08"PRIx32
, offset
);
910 return ERROR_FLASH_SECTOR_INVALID
;
913 if (sector
->is_protected
) {
914 LOG_ERROR("Can't erase protected sector @ 0x%08"PRIx32
, offset
);
918 if (sector
->is_erased
!= 1) { /* 1 = erased, 0= not erased, -1 = unknown */
919 res
= nrf51_erase_page(bank
, chip
, sector
);
920 if (res
!= ERROR_OK
) {
921 LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32
, sector
->offset
);
925 sector
->is_erased
= 0;
928 res
= nrf51_nvmc_write_enable(chip
);
932 res
= nrf51_ll_flash_write(chip
, start
, buffer
, (end
- start
));
936 return nrf51_nvmc_read_only(chip
);
939 nrf51_nvmc_read_only(chip
);
941 LOG_ERROR("Failed to write to nrf51 flash");
945 static int nrf51_erase(struct flash_bank
*bank
, int first
, int last
)
948 struct nrf51_info
*chip
;
950 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
954 /* For each sector to be erased */
955 for (int s
= first
; s
<= last
&& res
== ERROR_OK
; s
++)
956 res
= nrf51_erase_page(bank
, chip
, &bank
->sectors
[s
]);
961 static int nrf51_code_flash_write(struct flash_bank
*bank
,
962 struct nrf51_info
*chip
,
963 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
967 /* Need to perform reads to fill any gaps we need to preserve in the first page,
968 before the start of buffer, or in the last page, after the end of buffer */
969 uint32_t first_page
= offset
/chip
->code_page_size
;
970 uint32_t last_page
= DIV_ROUND_UP(offset
+count
, chip
->code_page_size
);
972 uint32_t first_page_offset
= first_page
* chip
->code_page_size
;
973 uint32_t last_page_offset
= last_page
* chip
->code_page_size
;
975 LOG_DEBUG("Padding write from 0x%08"PRIx32
"-0x%08"PRIx32
" as 0x%08"PRIx32
"-0x%08"PRIx32
,
976 offset
, offset
+count
, first_page_offset
, last_page_offset
);
978 uint32_t page_cnt
= last_page
- first_page
;
979 uint8_t buffer_to_flash
[page_cnt
*chip
->code_page_size
];
981 /* Fill in any space between start of first page and start of buffer */
982 uint32_t pre
= offset
- first_page_offset
;
984 res
= target_read_memory(bank
->target
,
993 /* Fill in main contents of buffer */
994 memcpy(buffer_to_flash
+pre
, buffer
, count
);
996 /* Fill in any space between end of buffer and end of last page */
997 uint32_t post
= last_page_offset
- (offset
+count
);
999 /* Retrieve the full row contents from Flash */
1000 res
= target_read_memory(bank
->target
,
1004 buffer_to_flash
+pre
+count
);
1005 if (res
!= ERROR_OK
)
1009 return nrf51_write_pages(bank
, first_page_offset
, last_page_offset
, buffer_to_flash
);
1012 static int nrf51_uicr_flash_write(struct flash_bank
*bank
,
1013 struct nrf51_info
*chip
,
1014 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
1017 uint8_t uicr
[NRF51_UICR_SIZE
];
1018 struct flash_sector
*sector
= &bank
->sectors
[0];
1020 if ((offset
+ count
) > NRF51_UICR_SIZE
)
1023 res
= target_read_memory(bank
->target
,
1029 if (res
!= ERROR_OK
)
1032 if (sector
->is_erased
!= 1) {
1033 res
= nrf51_erase_page(bank
, chip
, sector
);
1034 if (res
!= ERROR_OK
)
1038 res
= nrf51_nvmc_write_enable(chip
);
1039 if (res
!= ERROR_OK
)
1042 memcpy(&uicr
[offset
], buffer
, count
);
1044 res
= nrf51_ll_flash_write(chip
, NRF51_UICR_BASE
, uicr
, NRF51_UICR_SIZE
);
1045 if (res
!= ERROR_OK
) {
1046 nrf51_nvmc_read_only(chip
);
1050 return nrf51_nvmc_read_only(chip
);
1054 static int nrf51_write(struct flash_bank
*bank
, const uint8_t *buffer
,
1055 uint32_t offset
, uint32_t count
)
1058 struct nrf51_info
*chip
;
1060 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
1061 if (res
!= ERROR_OK
)
1064 return chip
->bank
[bank
->bank_number
].write(bank
, chip
, buffer
, offset
, count
);
1068 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command
)
1070 static struct nrf51_info
*chip
;
1072 switch (bank
->base
) {
1073 case NRF51_FLASH_BASE
:
1074 bank
->bank_number
= 0;
1076 case NRF51_UICR_BASE
:
1077 bank
->bank_number
= 1;
1080 LOG_ERROR("Invalid bank address 0x%08" PRIx32
, bank
->base
);
1085 /* Create a new chip */
1086 chip
= calloc(1, sizeof(*chip
));
1090 chip
->target
= bank
->target
;
1093 switch (bank
->base
) {
1094 case NRF51_FLASH_BASE
:
1095 chip
->bank
[bank
->bank_number
].write
= nrf51_code_flash_write
;
1097 case NRF51_UICR_BASE
:
1098 chip
->bank
[bank
->bank_number
].write
= nrf51_uicr_flash_write
;
1102 chip
->bank
[bank
->bank_number
].probed
= false;
1103 bank
->driver_priv
= chip
;
1108 COMMAND_HANDLER(nrf51_handle_mass_erase_command
)
1111 struct flash_bank
*bank
= NULL
;
1112 struct target
*target
= get_current_target(CMD_CTX
);
1114 res
= get_flash_bank_by_addr(target
, NRF51_FLASH_BASE
, true, &bank
);
1115 if (res
!= ERROR_OK
)
1118 assert(bank
!= NULL
);
1120 struct nrf51_info
*chip
;
1122 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
1123 if (res
!= ERROR_OK
)
1128 res
= target_read_u32(target
, NRF51_FICR_PPFC
,
1130 if (res
!= ERROR_OK
) {
1131 LOG_ERROR("Couldn't read PPFC register");
1135 if ((ppfc
& 0xFF) == 0x00) {
1136 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1137 "mass erase command won't work.");
1141 res
= nrf51_erase_all(chip
);
1142 if (res
!= ERROR_OK
) {
1143 LOG_ERROR("Failed to erase the chip");
1144 nrf51_protect_check(bank
);
1148 for (int i
= 0; i
< bank
->num_sectors
; i
++)
1149 bank
->sectors
[i
].is_erased
= 1;
1151 res
= nrf51_protect_check(bank
);
1152 if (res
!= ERROR_OK
) {
1153 LOG_ERROR("Failed to check chip's write protection");
1157 res
= get_flash_bank_by_addr(target
, NRF51_UICR_BASE
, true, &bank
);
1158 if (res
!= ERROR_OK
)
1161 bank
->sectors
[0].is_erased
= 1;
1166 static int nrf51_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1170 struct nrf51_info
*chip
;
1172 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
1173 if (res
!= ERROR_OK
)
1177 const uint32_t address
;
1180 { .address
= NRF51_FICR_CODEPAGESIZE
},
1181 { .address
= NRF51_FICR_CODESIZE
},
1182 { .address
= NRF51_FICR_CLENR0
},
1183 { .address
= NRF51_FICR_PPFC
},
1184 { .address
= NRF51_FICR_NUMRAMBLOCK
},
1185 { .address
= NRF51_FICR_SIZERAMBLOCK0
},
1186 { .address
= NRF51_FICR_SIZERAMBLOCK1
},
1187 { .address
= NRF51_FICR_SIZERAMBLOCK2
},
1188 { .address
= NRF51_FICR_SIZERAMBLOCK3
},
1189 { .address
= NRF51_FICR_CONFIGID
},
1190 { .address
= NRF51_FICR_DEVICEID0
},
1191 { .address
= NRF51_FICR_DEVICEID1
},
1192 { .address
= NRF51_FICR_ER0
},
1193 { .address
= NRF51_FICR_ER1
},
1194 { .address
= NRF51_FICR_ER2
},
1195 { .address
= NRF51_FICR_ER3
},
1196 { .address
= NRF51_FICR_IR0
},
1197 { .address
= NRF51_FICR_IR1
},
1198 { .address
= NRF51_FICR_IR2
},
1199 { .address
= NRF51_FICR_IR3
},
1200 { .address
= NRF51_FICR_DEVICEADDRTYPE
},
1201 { .address
= NRF51_FICR_DEVICEADDR0
},
1202 { .address
= NRF51_FICR_DEVICEADDR1
},
1203 { .address
= NRF51_FICR_OVERRIDEN
},
1204 { .address
= NRF51_FICR_NRF_1MBIT0
},
1205 { .address
= NRF51_FICR_NRF_1MBIT1
},
1206 { .address
= NRF51_FICR_NRF_1MBIT2
},
1207 { .address
= NRF51_FICR_NRF_1MBIT3
},
1208 { .address
= NRF51_FICR_NRF_1MBIT4
},
1209 { .address
= NRF51_FICR_BLE_1MBIT0
},
1210 { .address
= NRF51_FICR_BLE_1MBIT1
},
1211 { .address
= NRF51_FICR_BLE_1MBIT2
},
1212 { .address
= NRF51_FICR_BLE_1MBIT3
},
1213 { .address
= NRF51_FICR_BLE_1MBIT4
},
1215 { .address
= NRF51_UICR_CLENR0
, },
1216 { .address
= NRF51_UICR_RBPCONF
},
1217 { .address
= NRF51_UICR_XTALFREQ
},
1218 { .address
= NRF51_UICR_FWID
},
1221 for (size_t i
= 0; i
< ARRAY_SIZE(ficr
); i
++) {
1222 res
= target_read_u32(chip
->target
, ficr
[i
].address
,
1224 if (res
!= ERROR_OK
) {
1225 LOG_ERROR("Couldn't read %" PRIx32
, ficr
[i
].address
);
1230 for (size_t i
= 0; i
< ARRAY_SIZE(uicr
); i
++) {
1231 res
= target_read_u32(chip
->target
, uicr
[i
].address
,
1233 if (res
!= ERROR_OK
) {
1234 LOG_ERROR("Couldn't read %" PRIx32
, uicr
[i
].address
);
1239 snprintf(buf
, buf_size
,
1240 "\n[factory information control block]\n\n"
1241 "code page size: %"PRIu32
"B\n"
1242 "code memory size: %"PRIu32
"kB\n"
1243 "code region 0 size: %"PRIu32
"kB\n"
1244 "pre-programmed code: %s\n"
1245 "number of ram blocks: %"PRIu32
"\n"
1246 "ram block 0 size: %"PRIu32
"B\n"
1247 "ram block 1 size: %"PRIu32
"B\n"
1248 "ram block 2 size: %"PRIu32
"B\n"
1249 "ram block 3 size: %"PRIu32
"B\n"
1250 "config id: %" PRIx32
"\n"
1251 "device id: 0x%"PRIx32
"%08"PRIx32
"\n"
1252 "encryption root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1253 "identity root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1254 "device address type: 0x%"PRIx32
"\n"
1255 "device address: 0x%"PRIx32
"%08"PRIx32
"\n"
1256 "override enable: %"PRIx32
"\n"
1257 "NRF_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1258 "BLE_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1259 "\n[user information control block]\n\n"
1260 "code region 0 size: %"PRIu32
"kB\n"
1261 "read back protection configuration: %"PRIx32
"\n"
1262 "reset value for XTALFREQ: %"PRIx32
"\n"
1263 "firmware id: 0x%04"PRIx32
,
1266 (ficr
[2].value
== 0xFFFFFFFF) ? 0 : ficr
[2].value
/ 1024,
1267 ((ficr
[3].value
& 0xFF) == 0x00) ? "present" : "not present",
1270 (ficr
[6].value
== 0xFFFFFFFF) ? 0 : ficr
[6].value
,
1271 (ficr
[7].value
== 0xFFFFFFFF) ? 0 : ficr
[7].value
,
1272 (ficr
[8].value
== 0xFFFFFFFF) ? 0 : ficr
[8].value
,
1274 ficr
[10].value
, ficr
[11].value
,
1275 ficr
[12].value
, ficr
[13].value
, ficr
[14].value
, ficr
[15].value
,
1276 ficr
[16].value
, ficr
[17].value
, ficr
[18].value
, ficr
[19].value
,
1278 ficr
[21].value
, ficr
[22].value
,
1280 ficr
[24].value
, ficr
[25].value
, ficr
[26].value
, ficr
[27].value
, ficr
[28].value
,
1281 ficr
[29].value
, ficr
[30].value
, ficr
[31].value
, ficr
[32].value
, ficr
[33].value
,
1282 (uicr
[0].value
== 0xFFFFFFFF) ? 0 : uicr
[0].value
/ 1024,
1283 uicr
[1].value
& 0xFFFF,
1284 uicr
[2].value
& 0xFF,
1285 uicr
[3].value
& 0xFFFF);
1290 static const struct command_registration nrf51_exec_command_handlers
[] = {
1292 .name
= "mass_erase",
1293 .handler
= nrf51_handle_mass_erase_command
,
1294 .mode
= COMMAND_EXEC
,
1295 .help
= "Erase all flash contents of the chip.",
1297 COMMAND_REGISTRATION_DONE
1300 static const struct command_registration nrf51_command_handlers
[] = {
1303 .mode
= COMMAND_ANY
,
1304 .help
= "nrf51 flash command group",
1306 .chain
= nrf51_exec_command_handlers
,
1308 COMMAND_REGISTRATION_DONE
1311 struct flash_driver nrf51_flash
= {
1313 .commands
= nrf51_command_handlers
,
1314 .flash_bank_command
= nrf51_flash_bank_command
,
1316 .erase
= nrf51_erase
,
1317 .protect
= nrf51_protect
,
1318 .write
= nrf51_write
,
1319 .read
= default_flash_read
,
1320 .probe
= nrf51_probe
,
1321 .auto_probe
= nrf51_auto_probe
,
1322 .erase_check
= default_flash_blank_check
,
1323 .protect_check
= nrf51_protect_check
,
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