1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
21 ***************************************************************************/
28 #include <target/algorithm.h>
29 #include <target/armv7m.h>
30 #include <helper/types.h>
33 NRF51_FLASH_BASE
= 0x00000000,
36 enum nrf51_ficr_registers
{
37 NRF51_FICR_BASE
= 0x10000000, /* Factory Information Configuration Registers */
39 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
41 NRF51_FICR_CODEPAGESIZE
= NRF51_FICR_REG(0x010),
42 NRF51_FICR_CODESIZE
= NRF51_FICR_REG(0x014),
43 NRF51_FICR_CLENR0
= NRF51_FICR_REG(0x028),
44 NRF51_FICR_PPFC
= NRF51_FICR_REG(0x02C),
45 NRF51_FICR_NUMRAMBLOCK
= NRF51_FICR_REG(0x034),
46 NRF51_FICR_SIZERAMBLOCK0
= NRF51_FICR_REG(0x038),
47 NRF51_FICR_SIZERAMBLOCK1
= NRF51_FICR_REG(0x03C),
48 NRF51_FICR_SIZERAMBLOCK2
= NRF51_FICR_REG(0x040),
49 NRF51_FICR_SIZERAMBLOCK3
= NRF51_FICR_REG(0x044),
50 NRF51_FICR_CONFIGID
= NRF51_FICR_REG(0x05C),
51 NRF51_FICR_DEVICEID0
= NRF51_FICR_REG(0x060),
52 NRF51_FICR_DEVICEID1
= NRF51_FICR_REG(0x064),
53 NRF51_FICR_ER0
= NRF51_FICR_REG(0x080),
54 NRF51_FICR_ER1
= NRF51_FICR_REG(0x084),
55 NRF51_FICR_ER2
= NRF51_FICR_REG(0x088),
56 NRF51_FICR_ER3
= NRF51_FICR_REG(0x08C),
57 NRF51_FICR_IR0
= NRF51_FICR_REG(0x090),
58 NRF51_FICR_IR1
= NRF51_FICR_REG(0x094),
59 NRF51_FICR_IR2
= NRF51_FICR_REG(0x098),
60 NRF51_FICR_IR3
= NRF51_FICR_REG(0x09C),
61 NRF51_FICR_DEVICEADDRTYPE
= NRF51_FICR_REG(0x0A0),
62 NRF51_FICR_DEVICEADDR0
= NRF51_FICR_REG(0x0A4),
63 NRF51_FICR_DEVICEADDR1
= NRF51_FICR_REG(0x0A8),
64 NRF51_FICR_OVERRIDEN
= NRF51_FICR_REG(0x0AC),
65 NRF51_FICR_NRF_1MBIT0
= NRF51_FICR_REG(0x0B0),
66 NRF51_FICR_NRF_1MBIT1
= NRF51_FICR_REG(0x0B4),
67 NRF51_FICR_NRF_1MBIT2
= NRF51_FICR_REG(0x0B8),
68 NRF51_FICR_NRF_1MBIT3
= NRF51_FICR_REG(0x0BC),
69 NRF51_FICR_NRF_1MBIT4
= NRF51_FICR_REG(0x0C0),
70 NRF51_FICR_BLE_1MBIT0
= NRF51_FICR_REG(0x0EC),
71 NRF51_FICR_BLE_1MBIT1
= NRF51_FICR_REG(0x0F0),
72 NRF51_FICR_BLE_1MBIT2
= NRF51_FICR_REG(0x0F4),
73 NRF51_FICR_BLE_1MBIT3
= NRF51_FICR_REG(0x0F8),
74 NRF51_FICR_BLE_1MBIT4
= NRF51_FICR_REG(0x0FC),
77 enum nrf51_uicr_registers
{
78 NRF51_UICR_BASE
= 0x10001000, /* User Information
79 * Configuration Regsters */
81 NRF51_UICR_SIZE
= 0x100,
83 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
85 NRF51_UICR_CLENR0
= NRF51_UICR_REG(0x000),
86 NRF51_UICR_RBPCONF
= NRF51_UICR_REG(0x004),
87 NRF51_UICR_XTALFREQ
= NRF51_UICR_REG(0x008),
88 NRF51_UICR_FWID
= NRF51_UICR_REG(0x010),
91 enum nrf51_nvmc_registers
{
92 NRF51_NVMC_BASE
= 0x4001E000, /* Non-Volatile Memory
93 * Controller Regsters */
95 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
97 NRF51_NVMC_READY
= NRF51_NVMC_REG(0x400),
98 NRF51_NVMC_CONFIG
= NRF51_NVMC_REG(0x504),
99 NRF51_NVMC_ERASEPAGE
= NRF51_NVMC_REG(0x508),
100 NRF51_NVMC_ERASEALL
= NRF51_NVMC_REG(0x50C),
101 NRF51_NVMC_ERASEUICR
= NRF51_NVMC_REG(0x514),
104 enum nrf51_nvmc_config_bits
{
105 NRF51_NVMC_CONFIG_REN
= 0x00,
106 NRF51_NVMC_CONFIG_WEN
= 0x01,
107 NRF51_NVMC_CONFIG_EEN
= 0x02,
112 uint32_t code_page_size
;
113 uint32_t code_memory_size
;
117 int (*write
) (struct flash_bank
*bank
,
118 struct nrf51_info
*chip
,
119 const uint8_t *buffer
, uint32_t offset
, uint32_t count
);
121 struct target
*target
;
124 struct nrf51_device_spec
{
127 const char *build_code
;
128 unsigned int flash_size_kb
;
131 /* The known devices table below is derived from the "nRF51 Series
132 * Compatibility Matrix" document, which can be found by searching for
133 * ATTN-51 on the Nordic Semi website:
135 * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
137 * Up to date with Matrix v2.0, plus some additional HWIDs.
139 * The additional HWIDs apply where the build code in the matrix is
140 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
141 * for x==0, x!=0 means different (unspecified) HWIDs.
143 static const struct nrf51_device_spec nrf51_known_devices_table
[] = {
144 /* nRF51822 Devices (IC rev 1). */
148 .build_code
= "CA/C0",
149 .flash_size_kb
= 256,
155 .flash_size_kb
= 128,
161 .flash_size_kb
= 128,
167 .flash_size_kb
= 256,
173 .flash_size_kb
= 256,
176 /* nRF51822 Devices (IC rev 2). */
181 .flash_size_kb
= 256,
187 .flash_size_kb
= 256,
193 .flash_size_kb
= 256,
199 .flash_size_kb
= 128,
205 .flash_size_kb
= 256,
211 .flash_size_kb
= 256,
217 .flash_size_kb
= 256,
220 /* nRF51822 Devices (IC rev 3). */
225 .flash_size_kb
= 256,
231 .flash_size_kb
= 128,
237 .flash_size_kb
= 256,
243 .flash_size_kb
= 128,
249 .flash_size_kb
= 256,
255 .flash_size_kb
= 256,
258 /* nRF51422 Devices (IC rev 1). */
263 .flash_size_kb
= 256,
269 .flash_size_kb
= 256,
275 .flash_size_kb
= 256,
278 /* nRF51422 Devices (IC rev 2). */
283 .flash_size_kb
= 256,
289 .flash_size_kb
= 256,
295 .flash_size_kb
= 128,
301 .flash_size_kb
= 256,
304 /* nRF51422 Devices (IC rev 3). */
309 .flash_size_kb
= 256,
315 .flash_size_kb
= 128,
321 .flash_size_kb
= 256,
327 .flash_size_kb
= 256,
333 .flash_size_kb
= 128,
339 .flash_size_kb
= 256,
345 .flash_size_kb
= 256,
348 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
349 with built-in jlink seem to use engineering samples not listed
350 in the nRF51 Series Compatibility Matrix V1.0. */
355 .flash_size_kb
= 256,
359 static int nrf51_bank_is_probed(struct flash_bank
*bank
)
361 struct nrf51_info
*chip
= bank
->driver_priv
;
363 assert(chip
!= NULL
);
365 return chip
->bank
[bank
->bank_number
].probed
;
367 static int nrf51_probe(struct flash_bank
*bank
);
369 static int nrf51_get_probed_chip_if_halted(struct flash_bank
*bank
, struct nrf51_info
**chip
)
371 if (bank
->target
->state
!= TARGET_HALTED
) {
372 LOG_ERROR("Target not halted");
373 return ERROR_TARGET_NOT_HALTED
;
376 *chip
= bank
->driver_priv
;
378 int probed
= nrf51_bank_is_probed(bank
);
382 return nrf51_probe(bank
);
387 static int nrf51_wait_for_nvmc(struct nrf51_info
*chip
)
394 res
= target_read_u32(chip
->target
, NRF51_NVMC_READY
, &ready
);
395 if (res
!= ERROR_OK
) {
396 LOG_ERROR("Couldn't read NVMC_READY register");
400 if (ready
== 0x00000001)
406 LOG_DEBUG("Timed out waiting for NVMC_READY");
407 return ERROR_FLASH_BUSY
;
410 static int nrf51_nvmc_erase_enable(struct nrf51_info
*chip
)
413 res
= target_write_u32(chip
->target
,
415 NRF51_NVMC_CONFIG_EEN
);
417 if (res
!= ERROR_OK
) {
418 LOG_ERROR("Failed to enable erase operation");
423 According to NVMC examples in Nordic SDK busy status must be
424 checked after writing to NVMC_CONFIG
426 res
= nrf51_wait_for_nvmc(chip
);
428 LOG_ERROR("Erase enable did not complete");
433 static int nrf51_nvmc_write_enable(struct nrf51_info
*chip
)
436 res
= target_write_u32(chip
->target
,
438 NRF51_NVMC_CONFIG_WEN
);
440 if (res
!= ERROR_OK
) {
441 LOG_ERROR("Failed to enable write operation");
446 According to NVMC examples in Nordic SDK busy status must be
447 checked after writing to NVMC_CONFIG
449 res
= nrf51_wait_for_nvmc(chip
);
451 LOG_ERROR("Write enable did not complete");
456 static int nrf51_nvmc_read_only(struct nrf51_info
*chip
)
459 res
= target_write_u32(chip
->target
,
461 NRF51_NVMC_CONFIG_REN
);
463 if (res
!= ERROR_OK
) {
464 LOG_ERROR("Failed to enable read-only operation");
468 According to NVMC examples in Nordic SDK busy status must be
469 checked after writing to NVMC_CONFIG
471 res
= nrf51_wait_for_nvmc(chip
);
473 LOG_ERROR("Read only enable did not complete");
478 static int nrf51_nvmc_generic_erase(struct nrf51_info
*chip
,
479 uint32_t erase_register
, uint32_t erase_value
)
483 res
= nrf51_nvmc_erase_enable(chip
);
487 res
= target_write_u32(chip
->target
,
493 res
= nrf51_wait_for_nvmc(chip
);
497 return nrf51_nvmc_read_only(chip
);
500 nrf51_nvmc_read_only(chip
);
502 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32
,
503 erase_register
, erase_value
);
507 static int nrf51_protect_check(struct flash_bank
*bank
)
512 /* UICR cannot be write protected so just return early */
513 if (bank
->base
== NRF51_UICR_BASE
)
516 struct nrf51_info
*chip
= bank
->driver_priv
;
518 assert(chip
!= NULL
);
520 res
= target_read_u32(chip
->target
, NRF51_FICR_CLENR0
,
522 if (res
!= ERROR_OK
) {
523 LOG_ERROR("Couldn't read code region 0 size[FICR]");
527 if (clenr0
== 0xFFFFFFFF) {
528 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
530 if (res
!= ERROR_OK
) {
531 LOG_ERROR("Couldn't read code region 0 size[UICR]");
536 for (int i
= 0; i
< bank
->num_sectors
; i
++)
537 bank
->sectors
[i
].is_protected
=
538 clenr0
!= 0xFFFFFFFF && bank
->sectors
[i
].offset
< clenr0
;
543 static int nrf51_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
546 uint32_t clenr0
, ppfc
;
547 struct nrf51_info
*chip
;
549 /* UICR cannot be write protected so just bail out early */
550 if (bank
->base
== NRF51_UICR_BASE
)
553 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
558 LOG_ERROR("Code region 0 must start at the begining of the bank");
562 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
564 if (res
!= ERROR_OK
) {
565 LOG_ERROR("Couldn't read PPFC register");
569 if ((ppfc
& 0xFF) == 0x00) {
570 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
574 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
576 if (res
!= ERROR_OK
) {
577 LOG_ERROR("Couldn't read code region 0 size[UICR]");
581 if (clenr0
== 0xFFFFFFFF) {
582 res
= target_write_u32(chip
->target
, NRF51_UICR_CLENR0
,
584 if (res
!= ERROR_OK
) {
585 LOG_ERROR("Couldn't write code region 0 size[UICR]");
590 LOG_ERROR("You need to perform chip erase before changing the protection settings");
593 nrf51_protect_check(bank
);
598 static int nrf51_probe(struct flash_bank
*bank
)
602 struct nrf51_info
*chip
= bank
->driver_priv
;
604 res
= target_read_u32(chip
->target
, NRF51_FICR_CONFIGID
, &hwid
);
605 if (res
!= ERROR_OK
) {
606 LOG_ERROR("Couldn't read CONFIGID register");
610 hwid
&= 0xFFFF; /* HWID is stored in the lower two
611 * bytes of the CONFIGID register */
613 const struct nrf51_device_spec
*spec
= NULL
;
614 for (size_t i
= 0; i
< ARRAY_SIZE(nrf51_known_devices_table
); i
++)
615 if (hwid
== nrf51_known_devices_table
[i
].hwid
) {
616 spec
= &nrf51_known_devices_table
[i
];
620 if (!chip
->bank
[0].probed
&& !chip
->bank
[1].probed
) {
622 LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
623 spec
->variant
, spec
->build_code
, spec
->flash_size_kb
);
625 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32
")", hwid
);
629 if (bank
->base
== NRF51_FLASH_BASE
) {
630 res
= target_read_u32(chip
->target
, NRF51_FICR_CODEPAGESIZE
,
631 &chip
->code_page_size
);
632 if (res
!= ERROR_OK
) {
633 LOG_ERROR("Couldn't read code page size");
637 res
= target_read_u32(chip
->target
, NRF51_FICR_CODESIZE
,
638 &chip
->code_memory_size
);
639 if (res
!= ERROR_OK
) {
640 LOG_ERROR("Couldn't read code memory size");
644 if (spec
&& chip
->code_memory_size
!= spec
->flash_size_kb
) {
645 LOG_ERROR("Chip's reported Flash capacity does not match expected one");
649 bank
->size
= chip
->code_memory_size
* 1024;
650 bank
->num_sectors
= bank
->size
/ chip
->code_page_size
;
651 bank
->sectors
= calloc(bank
->num_sectors
,
652 sizeof((bank
->sectors
)[0]));
654 return ERROR_FLASH_BANK_NOT_PROBED
;
656 /* Fill out the sector information: all NRF51 sectors are the same size and
657 * there is always a fixed number of them. */
658 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
659 bank
->sectors
[i
].size
= chip
->code_page_size
;
660 bank
->sectors
[i
].offset
= i
* chip
->code_page_size
;
662 /* mark as unknown */
663 bank
->sectors
[i
].is_erased
= -1;
664 bank
->sectors
[i
].is_protected
= -1;
667 nrf51_protect_check(bank
);
669 chip
->bank
[0].probed
= true;
671 bank
->size
= NRF51_UICR_SIZE
;
672 bank
->num_sectors
= 1;
673 bank
->sectors
= calloc(bank
->num_sectors
,
674 sizeof((bank
->sectors
)[0]));
676 return ERROR_FLASH_BANK_NOT_PROBED
;
678 bank
->sectors
[0].size
= bank
->size
;
679 bank
->sectors
[0].offset
= 0;
681 /* mark as unknown */
682 bank
->sectors
[0].is_erased
= 0;
683 bank
->sectors
[0].is_protected
= 0;
685 chip
->bank
[1].probed
= true;
691 static int nrf51_auto_probe(struct flash_bank
*bank
)
693 int probed
= nrf51_bank_is_probed(bank
);
700 return nrf51_probe(bank
);
703 static struct flash_sector
*nrf51_find_sector_by_address(struct flash_bank
*bank
, uint32_t address
)
705 struct nrf51_info
*chip
= bank
->driver_priv
;
707 for (int i
= 0; i
< bank
->num_sectors
; i
++)
708 if (bank
->sectors
[i
].offset
<= address
&&
709 address
< (bank
->sectors
[i
].offset
+ chip
->code_page_size
))
710 return &bank
->sectors
[i
];
714 static int nrf51_erase_all(struct nrf51_info
*chip
)
716 LOG_DEBUG("Erasing all non-volatile memory");
717 return nrf51_nvmc_generic_erase(chip
,
722 static int nrf51_erase_page(struct flash_bank
*bank
,
723 struct nrf51_info
*chip
,
724 struct flash_sector
*sector
)
728 LOG_DEBUG("Erasing page at 0x%"PRIx32
, sector
->offset
);
729 if (sector
->is_protected
) {
730 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32
, sector
->offset
);
734 if (bank
->base
== NRF51_UICR_BASE
) {
736 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
738 if (res
!= ERROR_OK
) {
739 LOG_ERROR("Couldn't read PPFC register");
743 if ((ppfc
& 0xFF) == 0xFF) {
744 /* We can't erase the UICR. Double-check to
745 see if it's already erased before complaining. */
746 default_flash_blank_check(bank
);
747 if (sector
->is_erased
== 1)
750 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
754 res
= nrf51_nvmc_generic_erase(chip
,
755 NRF51_NVMC_ERASEUICR
,
760 res
= nrf51_nvmc_generic_erase(chip
,
761 NRF51_NVMC_ERASEPAGE
,
766 sector
->is_erased
= 1;
771 static const uint8_t nrf51_flash_write_code
[] = {
772 /* See contrib/loaders/flash/cortex-m0.S */
774 0x0d, 0x68, /* ldr r5, [r1, #0] */
775 0x00, 0x2d, /* cmp r5, #0 */
776 0x0b, 0xd0, /* beq.n 1e <exit> */
777 0x4c, 0x68, /* ldr r4, [r1, #4] */
778 0xac, 0x42, /* cmp r4, r5 */
779 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
780 0x20, 0xcc, /* ldmia r4!, {r5} */
781 0x20, 0xc3, /* stmia r3!, {r5} */
782 0x94, 0x42, /* cmp r4, r2 */
783 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
784 0x0c, 0x46, /* mov r4, r1 */
785 0x08, 0x34, /* adds r4, #8 */
787 0x4c, 0x60, /* str r4, [r1, #4] */
788 0x04, 0x38, /* subs r0, #4 */
789 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
791 0x00, 0xbe /* bkpt 0x0000 */
795 /* Start a low level flash write for the specified region */
796 static int nrf51_ll_flash_write(struct nrf51_info
*chip
, uint32_t offset
, const uint8_t *buffer
, uint32_t bytes
)
798 struct target
*target
= chip
->target
;
799 uint32_t buffer_size
= 8192;
800 struct working_area
*write_algorithm
;
801 struct working_area
*source
;
802 uint32_t address
= NRF51_FLASH_BASE
+ offset
;
803 struct reg_param reg_params
[4];
804 struct armv7m_algorithm armv7m_info
;
805 int retval
= ERROR_OK
;
808 LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32
" bytes=0x%"PRIx32
, offset
, bytes
);
809 assert(bytes
% 4 == 0);
811 /* allocate working area with flash programming code */
812 if (target_alloc_working_area(target
, sizeof(nrf51_flash_write_code
),
813 &write_algorithm
) != ERROR_OK
) {
814 LOG_WARNING("no working area available, falling back to slow memory writes");
816 for (; bytes
> 0; bytes
-= 4) {
817 retval
= target_write_memory(chip
->target
, offset
, 4, 1, buffer
);
818 if (retval
!= ERROR_OK
)
821 retval
= nrf51_wait_for_nvmc(chip
);
822 if (retval
!= ERROR_OK
)
832 LOG_WARNING("using fast async flash loader. This is currently supported");
833 LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
834 LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg to disable it");
836 retval
= target_write_buffer(target
, write_algorithm
->address
,
837 sizeof(nrf51_flash_write_code
),
838 nrf51_flash_write_code
);
839 if (retval
!= ERROR_OK
)
843 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
) {
845 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
846 if (buffer_size
<= 256) {
847 /* free working area, write algorithm already allocated */
848 target_free_working_area(target
, write_algorithm
);
850 LOG_WARNING("No large enough working area available, can't do block memory writes");
851 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
855 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
856 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
858 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* byte count */
859 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer start */
860 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer end */
861 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
); /* target address */
863 buf_set_u32(reg_params
[0].value
, 0, 32, bytes
);
864 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
865 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
+ source
->size
);
866 buf_set_u32(reg_params
[3].value
, 0, 32, address
);
868 retval
= target_run_flash_async_algorithm(target
, buffer
, bytes
/4, 4,
871 source
->address
, source
->size
,
872 write_algorithm
->address
, 0,
875 target_free_working_area(target
, source
);
876 target_free_working_area(target
, write_algorithm
);
878 destroy_reg_param(®_params
[0]);
879 destroy_reg_param(®_params
[1]);
880 destroy_reg_param(®_params
[2]);
881 destroy_reg_param(®_params
[3]);
886 /* Check and erase flash sectors in specified range then start a low level page write.
887 start/end must be sector aligned.
889 static int nrf51_write_pages(struct flash_bank
*bank
, uint32_t start
, uint32_t end
, const uint8_t *buffer
)
891 int res
= ERROR_FAIL
;
892 struct nrf51_info
*chip
= bank
->driver_priv
;
893 struct flash_sector
*sector
;
896 assert(start
% chip
->code_page_size
== 0);
897 assert(end
% chip
->code_page_size
== 0);
899 /* Erase all sectors */
900 for (offset
= start
; offset
< end
; offset
+= chip
->code_page_size
) {
901 sector
= nrf51_find_sector_by_address(bank
, offset
);
903 LOG_ERROR("Invalid sector @ 0x%08"PRIx32
, offset
);
904 return ERROR_FLASH_SECTOR_INVALID
;
907 if (sector
->is_protected
) {
908 LOG_ERROR("Can't erase protected sector @ 0x%08"PRIx32
, offset
);
912 if (sector
->is_erased
!= 1) { /* 1 = erased, 0= not erased, -1 = unknown */
913 res
= nrf51_erase_page(bank
, chip
, sector
);
914 if (res
!= ERROR_OK
) {
915 LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32
, sector
->offset
);
919 sector
->is_erased
= 0;
922 res
= nrf51_nvmc_write_enable(chip
);
926 res
= nrf51_ll_flash_write(chip
, start
, buffer
, (end
- start
));
930 return nrf51_nvmc_read_only(chip
);
933 nrf51_nvmc_read_only(chip
);
935 LOG_ERROR("Failed to write to nrf51 flash");
939 static int nrf51_erase(struct flash_bank
*bank
, int first
, int last
)
942 struct nrf51_info
*chip
;
944 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
948 /* For each sector to be erased */
949 for (int s
= first
; s
<= last
&& res
== ERROR_OK
; s
++)
950 res
= nrf51_erase_page(bank
, chip
, &bank
->sectors
[s
]);
955 static int nrf51_code_flash_write(struct flash_bank
*bank
,
956 struct nrf51_info
*chip
,
957 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
961 /* Need to perform reads to fill any gaps we need to preserve in the first page,
962 before the start of buffer, or in the last page, after the end of buffer */
963 uint32_t first_page
= offset
/chip
->code_page_size
;
964 uint32_t last_page
= DIV_ROUND_UP(offset
+count
, chip
->code_page_size
);
966 uint32_t first_page_offset
= first_page
* chip
->code_page_size
;
967 uint32_t last_page_offset
= last_page
* chip
->code_page_size
;
969 LOG_DEBUG("Padding write from 0x%08"PRIx32
"-0x%08"PRIx32
" as 0x%08"PRIx32
"-0x%08"PRIx32
,
970 offset
, offset
+count
, first_page_offset
, last_page_offset
);
972 uint32_t page_cnt
= last_page
- first_page
;
973 uint8_t buffer_to_flash
[page_cnt
*chip
->code_page_size
];
975 /* Fill in any space between start of first page and start of buffer */
976 uint32_t pre
= offset
- first_page_offset
;
978 res
= target_read_memory(bank
->target
,
987 /* Fill in main contents of buffer */
988 memcpy(buffer_to_flash
+pre
, buffer
, count
);
990 /* Fill in any space between end of buffer and end of last page */
991 uint32_t post
= last_page_offset
- (offset
+count
);
993 /* Retrieve the full row contents from Flash */
994 res
= target_read_memory(bank
->target
,
998 buffer_to_flash
+pre
+count
);
1003 return nrf51_write_pages(bank
, first_page_offset
, last_page_offset
, buffer_to_flash
);
1006 static int nrf51_uicr_flash_write(struct flash_bank
*bank
,
1007 struct nrf51_info
*chip
,
1008 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
1011 uint8_t uicr
[NRF51_UICR_SIZE
];
1012 struct flash_sector
*sector
= &bank
->sectors
[0];
1014 if ((offset
+ count
) > NRF51_UICR_SIZE
)
1017 res
= target_read_memory(bank
->target
,
1023 if (res
!= ERROR_OK
)
1026 if (sector
->is_erased
!= 1) {
1027 res
= nrf51_erase_page(bank
, chip
, sector
);
1028 if (res
!= ERROR_OK
)
1032 res
= nrf51_nvmc_write_enable(chip
);
1033 if (res
!= ERROR_OK
)
1036 memcpy(&uicr
[offset
], buffer
, count
);
1038 res
= nrf51_ll_flash_write(chip
, NRF51_UICR_BASE
, uicr
, NRF51_UICR_SIZE
);
1039 if (res
!= ERROR_OK
) {
1040 nrf51_nvmc_read_only(chip
);
1044 return nrf51_nvmc_read_only(chip
);
1048 static int nrf51_write(struct flash_bank
*bank
, const uint8_t *buffer
,
1049 uint32_t offset
, uint32_t count
)
1052 struct nrf51_info
*chip
;
1054 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
1055 if (res
!= ERROR_OK
)
1058 return chip
->bank
[bank
->bank_number
].write(bank
, chip
, buffer
, offset
, count
);
1062 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command
)
1064 static struct nrf51_info
*chip
;
1066 switch (bank
->base
) {
1067 case NRF51_FLASH_BASE
:
1068 bank
->bank_number
= 0;
1070 case NRF51_UICR_BASE
:
1071 bank
->bank_number
= 1;
1074 LOG_ERROR("Invalid bank address 0x%08" PRIx32
, bank
->base
);
1079 /* Create a new chip */
1080 chip
= calloc(1, sizeof(*chip
));
1084 chip
->target
= bank
->target
;
1087 switch (bank
->base
) {
1088 case NRF51_FLASH_BASE
:
1089 chip
->bank
[bank
->bank_number
].write
= nrf51_code_flash_write
;
1091 case NRF51_UICR_BASE
:
1092 chip
->bank
[bank
->bank_number
].write
= nrf51_uicr_flash_write
;
1096 chip
->bank
[bank
->bank_number
].probed
= false;
1097 bank
->driver_priv
= chip
;
1102 COMMAND_HANDLER(nrf51_handle_mass_erase_command
)
1105 struct flash_bank
*bank
= NULL
;
1106 struct target
*target
= get_current_target(CMD_CTX
);
1108 res
= get_flash_bank_by_addr(target
, NRF51_FLASH_BASE
, true, &bank
);
1109 if (res
!= ERROR_OK
)
1112 assert(bank
!= NULL
);
1114 struct nrf51_info
*chip
;
1116 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
1117 if (res
!= ERROR_OK
)
1122 res
= target_read_u32(target
, NRF51_FICR_PPFC
,
1124 if (res
!= ERROR_OK
) {
1125 LOG_ERROR("Couldn't read PPFC register");
1129 if ((ppfc
& 0xFF) == 0x00) {
1130 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1131 "mass erase command won't work.");
1135 res
= nrf51_erase_all(chip
);
1136 if (res
!= ERROR_OK
) {
1137 LOG_ERROR("Failed to erase the chip");
1138 nrf51_protect_check(bank
);
1142 for (int i
= 0; i
< bank
->num_sectors
; i
++)
1143 bank
->sectors
[i
].is_erased
= 1;
1145 res
= nrf51_protect_check(bank
);
1146 if (res
!= ERROR_OK
) {
1147 LOG_ERROR("Failed to check chip's write protection");
1151 res
= get_flash_bank_by_addr(target
, NRF51_UICR_BASE
, true, &bank
);
1152 if (res
!= ERROR_OK
)
1155 bank
->sectors
[0].is_erased
= 1;
1160 static int nrf51_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1164 struct nrf51_info
*chip
;
1166 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
1167 if (res
!= ERROR_OK
)
1171 const uint32_t address
;
1174 { .address
= NRF51_FICR_CODEPAGESIZE
},
1175 { .address
= NRF51_FICR_CODESIZE
},
1176 { .address
= NRF51_FICR_CLENR0
},
1177 { .address
= NRF51_FICR_PPFC
},
1178 { .address
= NRF51_FICR_NUMRAMBLOCK
},
1179 { .address
= NRF51_FICR_SIZERAMBLOCK0
},
1180 { .address
= NRF51_FICR_SIZERAMBLOCK1
},
1181 { .address
= NRF51_FICR_SIZERAMBLOCK2
},
1182 { .address
= NRF51_FICR_SIZERAMBLOCK3
},
1183 { .address
= NRF51_FICR_CONFIGID
},
1184 { .address
= NRF51_FICR_DEVICEID0
},
1185 { .address
= NRF51_FICR_DEVICEID1
},
1186 { .address
= NRF51_FICR_ER0
},
1187 { .address
= NRF51_FICR_ER1
},
1188 { .address
= NRF51_FICR_ER2
},
1189 { .address
= NRF51_FICR_ER3
},
1190 { .address
= NRF51_FICR_IR0
},
1191 { .address
= NRF51_FICR_IR1
},
1192 { .address
= NRF51_FICR_IR2
},
1193 { .address
= NRF51_FICR_IR3
},
1194 { .address
= NRF51_FICR_DEVICEADDRTYPE
},
1195 { .address
= NRF51_FICR_DEVICEADDR0
},
1196 { .address
= NRF51_FICR_DEVICEADDR1
},
1197 { .address
= NRF51_FICR_OVERRIDEN
},
1198 { .address
= NRF51_FICR_NRF_1MBIT0
},
1199 { .address
= NRF51_FICR_NRF_1MBIT1
},
1200 { .address
= NRF51_FICR_NRF_1MBIT2
},
1201 { .address
= NRF51_FICR_NRF_1MBIT3
},
1202 { .address
= NRF51_FICR_NRF_1MBIT4
},
1203 { .address
= NRF51_FICR_BLE_1MBIT0
},
1204 { .address
= NRF51_FICR_BLE_1MBIT1
},
1205 { .address
= NRF51_FICR_BLE_1MBIT2
},
1206 { .address
= NRF51_FICR_BLE_1MBIT3
},
1207 { .address
= NRF51_FICR_BLE_1MBIT4
},
1209 { .address
= NRF51_UICR_CLENR0
, },
1210 { .address
= NRF51_UICR_RBPCONF
},
1211 { .address
= NRF51_UICR_XTALFREQ
},
1212 { .address
= NRF51_UICR_FWID
},
1215 for (size_t i
= 0; i
< ARRAY_SIZE(ficr
); i
++) {
1216 res
= target_read_u32(chip
->target
, ficr
[i
].address
,
1218 if (res
!= ERROR_OK
) {
1219 LOG_ERROR("Couldn't read %" PRIx32
, ficr
[i
].address
);
1224 for (size_t i
= 0; i
< ARRAY_SIZE(uicr
); i
++) {
1225 res
= target_read_u32(chip
->target
, uicr
[i
].address
,
1227 if (res
!= ERROR_OK
) {
1228 LOG_ERROR("Couldn't read %" PRIx32
, uicr
[i
].address
);
1233 snprintf(buf
, buf_size
,
1234 "\n[factory information control block]\n\n"
1235 "code page size: %"PRIu32
"B\n"
1236 "code memory size: %"PRIu32
"kB\n"
1237 "code region 0 size: %"PRIu32
"kB\n"
1238 "pre-programmed code: %s\n"
1239 "number of ram blocks: %"PRIu32
"\n"
1240 "ram block 0 size: %"PRIu32
"B\n"
1241 "ram block 1 size: %"PRIu32
"B\n"
1242 "ram block 2 size: %"PRIu32
"B\n"
1243 "ram block 3 size: %"PRIu32
"B\n"
1244 "config id: %" PRIx32
"\n"
1245 "device id: 0x%"PRIx32
"%08"PRIx32
"\n"
1246 "encryption root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1247 "identity root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1248 "device address type: 0x%"PRIx32
"\n"
1249 "device address: 0x%"PRIx32
"%08"PRIx32
"\n"
1250 "override enable: %"PRIx32
"\n"
1251 "NRF_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1252 "BLE_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1253 "\n[user information control block]\n\n"
1254 "code region 0 size: %"PRIu32
"kB\n"
1255 "read back protection configuration: %"PRIx32
"\n"
1256 "reset value for XTALFREQ: %"PRIx32
"\n"
1257 "firmware id: 0x%04"PRIx32
,
1260 (ficr
[2].value
== 0xFFFFFFFF) ? 0 : ficr
[2].value
/ 1024,
1261 ((ficr
[3].value
& 0xFF) == 0x00) ? "present" : "not present",
1264 (ficr
[6].value
== 0xFFFFFFFF) ? 0 : ficr
[6].value
,
1265 (ficr
[7].value
== 0xFFFFFFFF) ? 0 : ficr
[7].value
,
1266 (ficr
[8].value
== 0xFFFFFFFF) ? 0 : ficr
[8].value
,
1268 ficr
[10].value
, ficr
[11].value
,
1269 ficr
[12].value
, ficr
[13].value
, ficr
[14].value
, ficr
[15].value
,
1270 ficr
[16].value
, ficr
[17].value
, ficr
[18].value
, ficr
[19].value
,
1272 ficr
[21].value
, ficr
[22].value
,
1274 ficr
[24].value
, ficr
[25].value
, ficr
[26].value
, ficr
[27].value
, ficr
[28].value
,
1275 ficr
[29].value
, ficr
[30].value
, ficr
[31].value
, ficr
[32].value
, ficr
[33].value
,
1276 (uicr
[0].value
== 0xFFFFFFFF) ? 0 : uicr
[0].value
/ 1024,
1277 uicr
[1].value
& 0xFFFF,
1278 uicr
[2].value
& 0xFF,
1279 uicr
[3].value
& 0xFFFF);
1284 static const struct command_registration nrf51_exec_command_handlers
[] = {
1286 .name
= "mass_erase",
1287 .handler
= nrf51_handle_mass_erase_command
,
1288 .mode
= COMMAND_EXEC
,
1289 .help
= "Erase all flash contents of the chip.",
1291 COMMAND_REGISTRATION_DONE
1294 static const struct command_registration nrf51_command_handlers
[] = {
1297 .mode
= COMMAND_ANY
,
1298 .help
= "nrf51 flash command group",
1300 .chain
= nrf51_exec_command_handlers
,
1302 COMMAND_REGISTRATION_DONE
1305 struct flash_driver nrf51_flash
= {
1307 .commands
= nrf51_command_handlers
,
1308 .flash_bank_command
= nrf51_flash_bank_command
,
1310 .erase
= nrf51_erase
,
1311 .protect
= nrf51_protect
,
1312 .write
= nrf51_write
,
1313 .read
= default_flash_read
,
1314 .probe
= nrf51_probe
,
1315 .auto_probe
= nrf51_auto_probe
,
1316 .erase_check
= default_flash_blank_check
,
1317 .protect_check
= nrf51_protect_check
,
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